rs6000.c (print_operand): New.
2014-08-17 Segher Boessenkool <segher@kernel.crashing.org> * config/rs6000/rs6000.c (print_operand) <'e'>: New. <'u'>: Also support printing the low-order 16 bits. * config/rs6000/rs6000.md (iorsi3, xorsi3, *boolsi3_internal1, *boolsi3_internal2 and split, *boolsi3_internal3 and split): Delete. (iordi3, xordi3, *booldi3_internal1, *booldi3_internal2 and split, *booldi3_internal3 and split): Delete. (ior<mode>3, xor<mode>3, *bool<mode>3, *bool<mode>3_dot, *bool<mode>3_dot2): New. (two anonymous define_splits for non_logical_cint_operand): Merge. From-SVN: r214077
This commit is contained in:
Segher Boessenkool
Segher Boessenkool
parent
19fe965886
commit
10802beec7
3 changed files with 140 additions and 258 deletions
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@ -1,3 +1,15 @@
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2014-08-17 Segher Boessenkool <segher@kernel.crashing.org>
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* config/rs6000/rs6000.c (print_operand) <'e'>: New.
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<'u'>: Also support printing the low-order 16 bits.
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* config/rs6000/rs6000.md (iorsi3, xorsi3, *boolsi3_internal1,
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*boolsi3_internal2 and split, *boolsi3_internal3 and split): Delete.
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(iordi3, xordi3, *booldi3_internal1, *booldi3_internal2 and split,
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*booldi3_internal3 and split): Delete.
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(ior<mode>3, xor<mode>3, *bool<mode>3, *bool<mode>3_dot,
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*bool<mode>3_dot2): New.
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(two anonymous define_splits for non_logical_cint_operand): Merge.
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2014-08-17 Marek Polacek <polacek@redhat.com>
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Manuel López-Ibáñez <manu@gcc.gnu.org>
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@ -18044,6 +18044,19 @@ print_operand (FILE *file, rtx x, int code)
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fprintf (file, "%d", i + 1);
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return;
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case 'e':
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/* If the low 16 bits are 0, but some other bit is set, write 's'. */
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if (! INT_P (x))
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{
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output_operand_lossage ("invalid %%e value");
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return;
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}
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uval = INTVAL (x);
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if ((uval & 0xffff) == 0 && uval != 0)
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putc ('s', file);
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return;
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case 'E':
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/* X is a CR register. Print the number of the EQ bit of the CR */
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if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
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@ -18346,12 +18359,19 @@ print_operand (FILE *file, rtx x, int code)
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return;
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case 'u':
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/* High-order 16 bits of constant for use in unsigned operand. */
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/* High-order or low-order 16 bits of constant, whichever is non-zero,
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for use in unsigned operand. */
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if (! INT_P (x))
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output_operand_lossage ("invalid %%u value");
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else
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fprintf (file, HOST_WIDE_INT_PRINT_HEX,
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(INTVAL (x) >> 16) & 0xffff);
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{
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output_operand_lossage ("invalid %%u value");
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return;
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}
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uval = INTVAL (x);
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if ((uval & 0xffff) == 0)
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uval >>= 16;
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fprintf (file, HOST_WIDE_INT_PRINT_HEX, uval & 0xffff);
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return;
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case 'v':
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@ -3159,142 +3159,144 @@
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}"
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[(set_attr "length" "8")])
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(define_expand "iorsi3"
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[(set (match_operand:SI 0 "gpc_reg_operand" "")
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(ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
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(match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
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""
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"
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{
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if (GET_CODE (operands[2]) == CONST_INT
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&& ! logical_operand (operands[2], SImode))
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{
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HOST_WIDE_INT value = INTVAL (operands[2]);
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rtx tmp = ((!can_create_pseudo_p ()
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|| rtx_equal_p (operands[0], operands[1]))
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? operands[0] : gen_reg_rtx (SImode));
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emit_insn (gen_iorsi3 (tmp, operands[1],
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GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
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emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
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(define_expand "ior<mode>3"
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[(set (match_operand:SDI 0 "gpc_reg_operand" "")
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(ior:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
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(match_operand:SDI 2 "reg_or_cint_operand" "")))]
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""
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{
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if (<MODE>mode == DImode && !TARGET_POWERPC64)
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{
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rs6000_split_logical (operands, IOR, false, false, false, NULL_RTX);
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DONE;
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}
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}")
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(define_expand "xorsi3"
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[(set (match_operand:SI 0 "gpc_reg_operand" "")
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(xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
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(match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
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""
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"
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{
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if (GET_CODE (operands[2]) == CONST_INT
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&& ! logical_operand (operands[2], SImode))
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if (non_logical_cint_operand (operands[2], <MODE>mode))
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{
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HOST_WIDE_INT value = INTVAL (operands[2]);
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rtx tmp = ((!can_create_pseudo_p ()
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|| rtx_equal_p (operands[0], operands[1]))
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? operands[0] : gen_reg_rtx (SImode));
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? operands[0] : gen_reg_rtx (<MODE>mode));
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HOST_WIDE_INT value = INTVAL (operands[2]);
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emit_insn (gen_xorsi3 (tmp, operands[1],
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emit_insn (gen_ior<mode>3 (tmp, operands[1],
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GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
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emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
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emit_insn (gen_ior<mode>3 (operands[0], tmp, GEN_INT (value & 0xffff)));
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DONE;
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}
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}")
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(define_insn "*boolsi3_internal1"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
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(match_operator:SI 3 "boolean_or_operator"
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[(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
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(match_operand:SI 2 "logical_operand" "r,K,L")]))]
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if (!reg_or_logical_cint_operand (operands[2], <MODE>mode))
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operands[2] = force_reg (<MODE>mode, operands[2]);
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})
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(define_expand "xor<mode>3"
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[(set (match_operand:SDI 0 "gpc_reg_operand" "")
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(xor:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
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(match_operand:SDI 2 "reg_or_cint_operand" "")))]
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""
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{
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if (<MODE>mode == DImode && !TARGET_POWERPC64)
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{
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rs6000_split_logical (operands, XOR, false, false, false, NULL_RTX);
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DONE;
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}
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if (non_logical_cint_operand (operands[2], <MODE>mode))
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{
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rtx tmp = ((!can_create_pseudo_p ()
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|| rtx_equal_p (operands[0], operands[1]))
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? operands[0] : gen_reg_rtx (<MODE>mode));
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HOST_WIDE_INT value = INTVAL (operands[2]);
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emit_insn (gen_xor<mode>3 (tmp, operands[1],
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GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
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emit_insn (gen_xor<mode>3 (operands[0], tmp, GEN_INT (value & 0xffff)));
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DONE;
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}
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if (!reg_or_logical_cint_operand (operands[2], <MODE>mode))
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operands[2] = force_reg (<MODE>mode, operands[2]);
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})
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(define_insn "*bool<mode>3"
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[(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
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(match_operator:GPR 3 "boolean_or_operator"
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[(match_operand:GPR 1 "gpc_reg_operand" "%r,r")
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(match_operand:GPR 2 "logical_operand" "r,n")]))]
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""
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"@
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%q3 %0,%1,%2
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%q3i %0,%1,%b2
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%q3is %0,%1,%u2")
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%q3i%e2 %0,%1,%u2"
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[(set_attr "type" "logical")])
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(define_insn "*boolsi3_internal2"
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[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
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(compare:CC (match_operator:SI 4 "boolean_or_operator"
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[(match_operand:SI 1 "gpc_reg_operand" "%r,r")
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(match_operand:SI 2 "gpc_reg_operand" "r,r")])
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(define_insn_and_split "*bool<mode>3_dot"
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[(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
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(compare:CC (match_operator:GPR 3 "boolean_or_operator"
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[(match_operand:GPR 1 "gpc_reg_operand" "r,r")
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(match_operand:GPR 2 "gpc_reg_operand" "r,r")])
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(const_int 0)))
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(clobber (match_scratch:SI 3 "=r,r"))]
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"TARGET_32BIT"
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(clobber (match_scratch:GPR 0 "=r,r"))]
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"<MODE>mode == Pmode && rs6000_gen_cell_microcode"
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"@
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%q4. %3,%1,%2
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%q3. %0,%1,%2
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#"
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[(set_attr "type" "logical,compare")
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(set_attr "dot" "yes")
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(set_attr "length" "4,8")])
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(define_split
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[(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
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(compare:CC (match_operator:SI 4 "boolean_operator"
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[(match_operand:SI 1 "gpc_reg_operand" "")
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(match_operand:SI 2 "gpc_reg_operand" "")])
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(const_int 0)))
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(clobber (match_scratch:SI 3 ""))]
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"TARGET_32BIT && reload_completed"
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[(set (match_dup 3) (match_dup 4))
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(set (match_dup 0)
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(compare:CC (match_dup 3)
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(const_int 0)))]
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"")
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(define_insn "*boolsi3_internal3"
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[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
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(compare:CC (match_operator:SI 4 "boolean_operator"
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[(match_operand:SI 1 "gpc_reg_operand" "%r,r")
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(match_operand:SI 2 "gpc_reg_operand" "r,r")])
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
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(match_dup 4))]
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"TARGET_32BIT"
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"@
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%q4. %0,%1,%2
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#"
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[(set_attr "type" "logical,compare")
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(set_attr "dot" "yes")
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(set_attr "length" "4,8")])
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(define_split
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[(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
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(compare:CC (match_operator:SI 4 "boolean_operator"
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[(match_operand:SI 1 "gpc_reg_operand" "")
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(match_operand:SI 2 "gpc_reg_operand" "")])
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "")
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(match_dup 4))]
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"TARGET_32BIT && reload_completed"
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[(set (match_dup 0) (match_dup 4))
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(set (match_dup 3)
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"&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
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[(set (match_dup 0)
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(match_dup 3))
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(set (match_dup 4)
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(compare:CC (match_dup 0)
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(const_int 0)))]
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"")
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""
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[(set_attr "type" "logical")
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(set_attr "dot" "yes")
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(set_attr "length" "4,8")])
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(define_insn_and_split "*bool<mode>3_dot2"
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[(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
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(compare:CC (match_operator:GPR 3 "boolean_or_operator"
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[(match_operand:GPR 1 "gpc_reg_operand" "r,r")
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(match_operand:GPR 2 "gpc_reg_operand" "r,r")])
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(const_int 0)))
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(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
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(match_dup 3))]
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"<MODE>mode == Pmode && rs6000_gen_cell_microcode"
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"@
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%q3. %0,%1,%2
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#"
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"&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
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[(set (match_dup 0)
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(match_dup 3))
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(set (match_dup 4)
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(compare:CC (match_dup 0)
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(const_int 0)))]
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""
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[(set_attr "type" "logical")
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(set_attr "dot" "yes")
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(set_attr "length" "4,8")])
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;; Split a logical operation that we can't do in one insn into two insns,
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;; each of which does one 16-bit part. This is used by combine.
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(define_split
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[(set (match_operand:SI 0 "gpc_reg_operand" "")
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(match_operator:SI 3 "boolean_or_operator"
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[(match_operand:SI 1 "gpc_reg_operand" "")
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(match_operand:SI 2 "non_logical_cint_operand" "")]))]
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[(set (match_operand:GPR 0 "gpc_reg_operand" "")
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(match_operator:GPR 3 "boolean_or_operator"
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[(match_operand:GPR 1 "gpc_reg_operand" "")
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(match_operand:GPR 2 "non_logical_cint_operand" "")]))]
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""
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[(set (match_dup 0) (match_dup 4))
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(set (match_dup 0) (match_dup 5))]
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"
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{
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rtx i;
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i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
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operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
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operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode,
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operands[1], i);
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i = GEN_INT (INTVAL (operands[2]) & 0xffff);
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operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
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operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), <MODE>mode,
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operands[0], i);
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}")
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})
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(define_insn "*boolcsi3_internal1"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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@ -7838,158 +7840,6 @@
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build_mask64_2_operands (operands[2], &operands[5]);
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}")
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(define_expand "iordi3"
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[(set (match_operand:DI 0 "gpc_reg_operand" "")
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(ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
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(match_operand:DI 2 "reg_or_cint_operand" "")))]
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""
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{
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if (!TARGET_POWERPC64)
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{
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rs6000_split_logical (operands, IOR, false, false, false, NULL_RTX);
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DONE;
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}
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else if (!reg_or_logical_cint_operand (operands[2], DImode))
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operands[2] = force_reg (DImode, operands[2]);
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else if (non_logical_cint_operand (operands[2], DImode))
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{
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HOST_WIDE_INT value;
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rtx tmp = ((!can_create_pseudo_p ()
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|| rtx_equal_p (operands[0], operands[1]))
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? operands[0] : gen_reg_rtx (DImode));
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value = INTVAL (operands[2]);
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emit_insn (gen_iordi3 (tmp, operands[1],
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GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
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emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
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DONE;
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}
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})
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(define_expand "xordi3"
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[(set (match_operand:DI 0 "gpc_reg_operand" "")
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(xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
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(match_operand:DI 2 "reg_or_cint_operand" "")))]
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""
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{
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if (!TARGET_POWERPC64)
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{
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rs6000_split_logical (operands, XOR, false, false, false, NULL_RTX);
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DONE;
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}
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else if (!reg_or_logical_cint_operand (operands[2], DImode))
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operands[2] = force_reg (DImode, operands[2]);
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if (non_logical_cint_operand (operands[2], DImode))
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{
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HOST_WIDE_INT value;
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rtx tmp = ((!can_create_pseudo_p ()
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|| rtx_equal_p (operands[0], operands[1]))
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? operands[0] : gen_reg_rtx (DImode));
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value = INTVAL (operands[2]);
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emit_insn (gen_xordi3 (tmp, operands[1],
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GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
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emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
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DONE;
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}
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})
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(define_insn "*booldi3_internal1"
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[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
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(match_operator:DI 3 "boolean_or_operator"
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[(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
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(match_operand:DI 2 "logical_operand" "r,K,JF")]))]
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"TARGET_POWERPC64"
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"@
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%q3 %0,%1,%2
|
||||
%q3i %0,%1,%b2
|
||||
%q3is %0,%1,%u2")
|
||||
|
||||
(define_insn "*booldi3_internal2"
|
||||
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
|
||||
(compare:CC (match_operator:DI 4 "boolean_or_operator"
|
||||
[(match_operand:DI 1 "gpc_reg_operand" "%r,r")
|
||||
(match_operand:DI 2 "gpc_reg_operand" "r,r")])
|
||||
(const_int 0)))
|
||||
(clobber (match_scratch:DI 3 "=r,r"))]
|
||||
"TARGET_64BIT"
|
||||
"@
|
||||
%q4. %3,%1,%2
|
||||
#"
|
||||
[(set_attr "type" "logical,compare")
|
||||
(set_attr "dot" "yes")
|
||||
(set_attr "length" "4,8")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
|
||||
(compare:CC (match_operator:DI 4 "boolean_operator"
|
||||
[(match_operand:DI 1 "gpc_reg_operand" "")
|
||||
(match_operand:DI 2 "gpc_reg_operand" "")])
|
||||
(const_int 0)))
|
||||
(clobber (match_scratch:DI 3 ""))]
|
||||
"TARGET_POWERPC64 && reload_completed"
|
||||
[(set (match_dup 3) (match_dup 4))
|
||||
(set (match_dup 0)
|
||||
(compare:CC (match_dup 3)
|
||||
(const_int 0)))]
|
||||
"")
|
||||
|
||||
(define_insn "*booldi3_internal3"
|
||||
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
|
||||
(compare:CC (match_operator:DI 4 "boolean_or_operator"
|
||||
[(match_operand:DI 1 "gpc_reg_operand" "%r,r")
|
||||
(match_operand:DI 2 "gpc_reg_operand" "r,r")])
|
||||
(const_int 0)))
|
||||
(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
|
||||
(match_dup 4))]
|
||||
"TARGET_64BIT"
|
||||
"@
|
||||
%q4. %0,%1,%2
|
||||
#"
|
||||
[(set_attr "type" "logical,compare")
|
||||
(set_attr "dot" "yes")
|
||||
(set_attr "length" "4,8")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
|
||||
(compare:CC (match_operator:DI 4 "boolean_operator"
|
||||
[(match_operand:DI 1 "gpc_reg_operand" "")
|
||||
(match_operand:DI 2 "gpc_reg_operand" "")])
|
||||
(const_int 0)))
|
||||
(set (match_operand:DI 0 "gpc_reg_operand" "")
|
||||
(match_dup 4))]
|
||||
"TARGET_POWERPC64 && reload_completed"
|
||||
[(set (match_dup 0) (match_dup 4))
|
||||
(set (match_dup 3)
|
||||
(compare:CC (match_dup 0)
|
||||
(const_int 0)))]
|
||||
"")
|
||||
|
||||
;; Split a logical operation that we can't do in one insn into two insns,
|
||||
;; each of which does one 16-bit part. This is used by combine.
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:DI 0 "gpc_reg_operand" "")
|
||||
(match_operator:DI 3 "boolean_or_operator"
|
||||
[(match_operand:DI 1 "gpc_reg_operand" "")
|
||||
(match_operand:DI 2 "non_logical_cint_operand" "")]))]
|
||||
"TARGET_POWERPC64"
|
||||
[(set (match_dup 0) (match_dup 4))
|
||||
(set (match_dup 0) (match_dup 5))]
|
||||
"
|
||||
{
|
||||
rtx i3,i4;
|
||||
|
||||
i3 = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
|
||||
i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
|
||||
operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
|
||||
operands[1], i3);
|
||||
operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
|
||||
operands[0], i4);
|
||||
}")
|
||||
|
||||
(define_insn "*boolcdi3_internal1"
|
||||
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
|
||||
(match_operator:DI 3 "boolean_operator"
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue