i386.c (ix86_lea_outperforms): Fix formatting.
* config/i386/i386.c (ix86_lea_outperforms): Fix formatting. (ix86_avoid_lea_for_addr): Likewise. (exact_dependency_1): Likewise. (ix86_adjust_cost): Likewise. (swap_top_of_ready_list): Fix formatting and !reload_completed check removed. (do_reorder_for_imul): Fix typo, formatting and !reload_completed check removed. (ix86_sched_reorder): Fix typo and formatting. (fold_builtin_cpu): Move M_INTEL_SLM at the end of processor types list. * config/i386/cpuinfo.c (INTEL_SLM): New enum value. From-SVN: r199611
This commit is contained in:
Yuri Rumyantsev
Jakub Jelinek
parent
3bc30db4f1
commit
0f1d3965bd
6 changed files with 137 additions and 125 deletions
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@ -1,3 +1,17 @@
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2013-06-03 Yuri Rumyantsev <yuri.s.rumyantsev@intel.com>
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* config/i386/i386.c (ix86_lea_outperforms): Fix formatting.
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(ix86_avoid_lea_for_addr): Likewise.
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(exact_dependency_1): Likewise.
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(ix86_adjust_cost): Likewise.
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(swap_top_of_ready_list): Fix formatting and !reload_completed check
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removed.
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(do_reorder_for_imul): Fix typo, formatting and
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!reload_completed check removed.
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(ix86_sched_reorder): Fix typo and formatting.
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(fold_builtin_cpu): Move M_INTEL_SLM at the end of processor types
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list.
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2013-06-03 Sofiane Naci <sofiane.naci@arm.com>
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* config/aarch64/aarch64.md (*movdi_aarch64): Define "simd" attribute.
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@ -269,8 +283,6 @@
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* config/i386/i386.md (cpu): Add new value "slm".
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(slm.md): Include slm.md.
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* libgcc/config/i386/cpuinfo.c (INTEL_SLM): New enum value.
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2013-05-30 Bernd Schmidt <bernds@codesourcery.com>
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Zhenqiang Chen <zhenqiang.chen@linaro.org>
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@ -17407,11 +17407,11 @@ ix86_lea_outperforms (rtx insn, unsigned int regno0, unsigned int regno1,
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if (ix86_tune == PROCESSOR_SLM)
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{
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if (has_scale)
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return true;
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return true;
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if (split_cost < 1)
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return false;
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return false;
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if (regno0 == regno1 || regno0 == regno2)
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return false;
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return false;
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return true;
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}
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@ -17605,7 +17605,7 @@ ix86_avoid_lea_for_addr (rtx insn, rtx operands[])
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}
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return !ix86_lea_outperforms (insn, regno0, regno1, regno2, split_cost,
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parts.scale > 1);
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parts.scale > 1);
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}
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/* Emit x86 binary operand CODE in mode MODE, where the first operand
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@ -24402,7 +24402,7 @@ exact_dependency_1 (rtx addr, rtx insn)
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{
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case MEM:
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if (rtx_equal_p (addr, insn))
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return true;
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return true;
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break;
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case REG:
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CASE_CONST_ANY:
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@ -24420,17 +24420,17 @@ exact_dependency_1 (rtx addr, rtx insn)
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for (i = 0; i < GET_RTX_LENGTH (code); i++)
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{
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switch (*format_ptr++)
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{
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case 'e':
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if (exact_dependency_1 (addr, XEXP (insn, i)))
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return true;
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break;
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case 'E':
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for (j = 0; j < XVECLEN (insn, i); j++)
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if (exact_dependency_1 (addr, XVECEXP (insn, i, j)))
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return true;
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break;
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}
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{
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case 'e':
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if (exact_dependency_1 (addr, XEXP (insn, i)))
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return true;
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break;
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case 'E':
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for (j = 0; j < XVECLEN (insn, i); j++)
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if (exact_dependency_1 (addr, XVECEXP (insn, i, j)))
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return true;
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break;
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}
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}
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return false;
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}
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@ -24610,35 +24610,35 @@ ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
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case PROCESSOR_SLM:
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if (!reload_completed)
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return cost;
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return cost;
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/* Increase cost of integer loads. */
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memory = get_attr_memory (dep_insn);
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if (memory == MEMORY_LOAD || memory == MEMORY_BOTH)
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{
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enum attr_unit unit = get_attr_unit (dep_insn);
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if (unit == UNIT_INTEGER && cost == 1)
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{
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if (memory == MEMORY_LOAD)
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cost = 3;
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else
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{
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/* Increase cost of ld/st for short int types only
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because of store forwarding issue. */
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rtx set = single_set (dep_insn);
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if (set && (GET_MODE (SET_DEST (set)) == QImode
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|| GET_MODE (SET_DEST (set)) == HImode))
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{
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/* Increase cost of store/load insn if exact
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dependence exists and it is load insn. */
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enum attr_memory insn_memory = get_attr_memory (insn);
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if (insn_memory == MEMORY_LOAD
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&& exact_store_load_dependency (dep_insn, insn))
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cost = 3;
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}
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}
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}
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}
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{
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enum attr_unit unit = get_attr_unit (dep_insn);
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if (unit == UNIT_INTEGER && cost == 1)
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{
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if (memory == MEMORY_LOAD)
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cost = 3;
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else
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{
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/* Increase cost of ld/st for short int types only
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because of store forwarding issue. */
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rtx set = single_set (dep_insn);
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if (set && (GET_MODE (SET_DEST (set)) == QImode
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|| GET_MODE (SET_DEST (set)) == HImode))
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{
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/* Increase cost of store/load insn if exact
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dependence exists and it is load insn. */
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enum attr_memory insn_memory = get_attr_memory (insn);
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if (insn_memory == MEMORY_LOAD
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&& exact_store_load_dependency (dep_insn, insn))
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cost = 3;
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}
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}
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}
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}
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default:
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break;
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@ -24688,7 +24688,7 @@ ia32_multipass_dfa_lookahead (void)
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ready list.
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Return index of IMUL producer if it was found and -1 otherwise. */
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static int
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do_reoder_for_imul(rtx *ready, int n_ready)
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do_reorder_for_imul (rtx *ready, int n_ready)
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{
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rtx insn, set, insn1, insn2;
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sd_iterator_def sd_it;
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@ -24699,10 +24699,6 @@ do_reoder_for_imul(rtx *ready, int n_ready)
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if (ix86_tune != PROCESSOR_ATOM)
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return index;
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/* Do not perform ready list reodering for pre-reload schedule pass. */
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if (!reload_completed)
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return index;
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/* Check that IMUL instruction is on the top of ready list. */
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insn = ready[n_ready - 1];
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set = single_set (insn);
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@ -24713,53 +24709,53 @@ do_reoder_for_imul(rtx *ready, int n_ready)
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return index;
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/* Search for producer of independent IMUL instruction. */
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for (i = n_ready - 2; i>= 0; i--)
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for (i = n_ready - 2; i >= 0; i--)
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{
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insn = ready[i];
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if (!NONDEBUG_INSN_P (insn))
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continue;
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continue;
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/* Skip IMUL instruction. */
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insn2 = PATTERN (insn);
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if (GET_CODE (insn2) == PARALLEL)
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insn2 = XVECEXP (insn2, 0, 0);
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insn2 = XVECEXP (insn2, 0, 0);
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if (GET_CODE (insn2) == SET
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&& GET_CODE (SET_SRC (insn2)) == MULT
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&& GET_MODE (SET_SRC (insn2)) == SImode)
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continue;
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&& GET_CODE (SET_SRC (insn2)) == MULT
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&& GET_MODE (SET_SRC (insn2)) == SImode)
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continue;
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FOR_EACH_DEP (insn, SD_LIST_FORW, sd_it, dep)
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{
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rtx con;
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{
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rtx con;
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con = DEP_CON (dep);
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if (!NONDEBUG_INSN_P (con))
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continue;
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insn1 = PATTERN (con);
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if (GET_CODE (insn1) == PARALLEL)
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insn1 = XVECEXP (insn1, 0, 0);
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insn1 = PATTERN (con);
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if (GET_CODE (insn1) == PARALLEL)
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insn1 = XVECEXP (insn1, 0, 0);
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if (GET_CODE (insn1) == SET
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&& GET_CODE (SET_SRC (insn1)) == MULT
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&& GET_MODE (SET_SRC (insn1)) == SImode)
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{
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sd_iterator_def sd_it1;
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dep_t dep1;
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/* Check if there is no other dependee for IMUL. */
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index = i;
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FOR_EACH_DEP (con, SD_LIST_BACK, sd_it1, dep1)
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{
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rtx pro;
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pro = DEP_PRO (dep1);
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if (GET_CODE (insn1) == SET
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&& GET_CODE (SET_SRC (insn1)) == MULT
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&& GET_MODE (SET_SRC (insn1)) == SImode)
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{
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sd_iterator_def sd_it1;
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dep_t dep1;
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/* Check if there is no other dependee for IMUL. */
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index = i;
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FOR_EACH_DEP (con, SD_LIST_BACK, sd_it1, dep1)
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{
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rtx pro;
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pro = DEP_PRO (dep1);
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if (!NONDEBUG_INSN_P (pro))
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continue;
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if (pro != insn)
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index = -1;
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}
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if (index >= 0)
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break;
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}
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}
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if (pro != insn)
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index = -1;
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}
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if (index >= 0)
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break;
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}
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}
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if (index >= 0)
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break;
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break;
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}
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return index;
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}
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@ -24769,7 +24765,7 @@ do_reoder_for_imul(rtx *ready, int n_ready)
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scheduled earlier. Applied for Silvermont only.
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Return true if top 2 insns must be interchanged. */
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static bool
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swap_top_of_ready_list(rtx *ready, int n_ready)
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swap_top_of_ready_list (rtx *ready, int n_ready)
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{
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rtx top = ready[n_ready - 1];
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rtx next = ready[n_ready - 2];
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@ -24782,8 +24778,6 @@ swap_top_of_ready_list(rtx *ready, int n_ready)
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if (ix86_tune != PROCESSOR_SLM)
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return false;
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if (!reload_completed)
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return false;
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if (!NONDEBUG_INSN_P (top))
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return false;
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@ -24803,37 +24797,37 @@ swap_top_of_ready_list(rtx *ready, int n_ready)
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if (INSN_PRIORITY_KNOWN (top) && INSN_PRIORITY_KNOWN (next))
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{
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if (INSN_PRIORITY (top) != INSN_PRIORITY (next))
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return false;
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return false;
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/* Determine winner more precise. */
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FOR_EACH_DEP (top, SD_LIST_RES_BACK, sd_it, dep)
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{
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rtx pro;
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pro = DEP_PRO (dep);
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if (!NONDEBUG_INSN_P (pro))
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continue;
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if (INSN_TICK (pro) > clock1)
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clock1 = INSN_TICK (pro);
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}
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{
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rtx pro;
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pro = DEP_PRO (dep);
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if (!NONDEBUG_INSN_P (pro))
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continue;
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if (INSN_TICK (pro) > clock1)
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clock1 = INSN_TICK (pro);
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}
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FOR_EACH_DEP (next, SD_LIST_RES_BACK, sd_it, dep)
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{
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rtx pro;
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pro = DEP_PRO (dep);
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if (!NONDEBUG_INSN_P (pro))
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continue;
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if (INSN_TICK (pro) > clock2)
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clock2 = INSN_TICK (pro);
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}
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{
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rtx pro;
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pro = DEP_PRO (dep);
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if (!NONDEBUG_INSN_P (pro))
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continue;
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if (INSN_TICK (pro) > clock2)
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clock2 = INSN_TICK (pro);
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}
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if (clock1 == clock2)
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{
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/* Determine winner - load must win. */
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enum attr_memory memory1, memory2;
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memory1 = get_attr_memory (top);
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memory2 = get_attr_memory (next);
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if (memory2 == MEMORY_LOAD && memory1 != MEMORY_LOAD)
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return true;
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}
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return (bool) (clock2 < clock1);
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{
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/* Determine winner - load must win. */
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enum attr_memory memory1, memory2;
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memory1 = get_attr_memory (top);
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memory2 = get_attr_memory (next);
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if (memory2 == MEMORY_LOAD && memory1 != MEMORY_LOAD)
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return true;
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}
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return (bool) (clock2 < clock1);
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}
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return false;
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#undef INSN_TICK
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@ -24842,8 +24836,8 @@ swap_top_of_ready_list(rtx *ready, int n_ready)
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/* Perform possible reodering of ready list for Atom/Silvermont only.
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Return issue rate. */
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static int
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ix86_sched_reorder(FILE *dump, int sched_verbose, rtx *ready, int *pn_ready,
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int clock_var)
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ix86_sched_reorder (FILE *dump, int sched_verbose, rtx *ready, int *pn_ready,
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int clock_var)
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{
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int issue_rate = -1;
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int n_ready = *pn_ready;
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@ -24852,7 +24846,7 @@ ix86_sched_reorder(FILE *dump, int sched_verbose, rtx *ready, int *pn_ready,
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int index = -1;
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/* Set up issue rate. */
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issue_rate = ix86_issue_rate();
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issue_rate = ix86_issue_rate ();
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/* Do reodering for Atom/SLM only. */
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if (ix86_tune != PROCESSOR_ATOM && ix86_tune != PROCESSOR_SLM)
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@ -24866,24 +24860,24 @@ ix86_sched_reorder(FILE *dump, int sched_verbose, rtx *ready, int *pn_ready,
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if (!reload_completed)
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return issue_rate;
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if ((index = do_reoder_for_imul (ready, n_ready)) >= 0)
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if ((index = do_reorder_for_imul (ready, n_ready)) >= 0)
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{
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if (sched_verbose > 1)
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fprintf(dump, ";;\tatom sched_reorder: put %d insn on top\n",
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INSN_UID (ready[index]));
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fprintf (dump, ";;\tatom sched_reorder: put %d insn on top\n",
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INSN_UID (ready[index]));
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/* Put IMUL producer (ready[index]) at the top of ready list. */
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insn= ready[index];
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insn = ready[index];
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for (i = index; i < n_ready - 1; i++)
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ready[i] = ready[i + 1];
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ready[i] = ready[i + 1];
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ready[n_ready - 1] = insn;
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return issue_rate;
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}
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if (clock_var != 0 && swap_top_of_ready_list (ready, n_ready))
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{
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if (sched_verbose > 1)
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fprintf(dump, ";;\tslm sched_reorder: swap %d and %d insns\n",
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INSN_UID (ready[n_ready - 1]), INSN_UID (ready[n_ready - 2]));
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fprintf (dump, ";;\tslm sched_reorder: swap %d and %d insns\n",
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INSN_UID (ready[n_ready - 1]), INSN_UID (ready[n_ready - 2]));
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/* Swap 2 top elements of ready list. */
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insn = ready[n_ready - 1];
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ready[n_ready - 1] = ready[n_ready - 2];
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|
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@ -30054,11 +30048,11 @@ fold_builtin_cpu (tree fndecl, tree *args)
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M_AMD,
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M_CPU_TYPE_START,
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M_INTEL_ATOM,
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M_INTEL_SLM,
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M_INTEL_CORE2,
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M_INTEL_COREI7,
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M_AMDFAM10H,
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M_AMDFAM15H,
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M_INTEL_SLM,
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M_CPU_SUBTYPE_START,
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M_INTEL_COREI7_NEHALEM,
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M_INTEL_COREI7_WESTMERE,
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|
|
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|||
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|
@ -445,7 +445,7 @@ extern unsigned char ix86_tune_features[X86_TUNE_LAST];
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#define TARGET_AVOID_MEM_OPND_FOR_CMOVE \
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ix86_tune_features[X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE]
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#define TARGET_SPLIT_MEM_OPND_FOR_FP_CONVERTS \
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ix86_tune_features[X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS]
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ix86_tune_features[X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS]
|
||||
|
||||
/* Feature tests against the various architecture variations. */
|
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enum ix86_arch_indices {
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||||
|
|
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|||
|
|
@ -3628,8 +3628,8 @@
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|||
;; It's more profitable to split and then extend in the same register.
|
||||
(define_peephole2
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[(set (match_operand:DF 0 "register_operand")
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||||
(float_extend:DF
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||||
(match_operand:SF 1 "memory_operand")))]
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||||
(float_extend:DF
|
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(match_operand:SF 1 "memory_operand")))]
|
||||
"TARGET_SPLIT_MEM_OPND_FOR_FP_CONVERTS
|
||||
&& optimize_insn_for_speed_p ()
|
||||
&& SSE_REG_P (operands[0])"
|
||||
|
|
@ -3781,8 +3781,8 @@
|
|||
;; It's more profitable to split and then extend in the same register.
|
||||
(define_peephole2
|
||||
[(set (match_operand:SF 0 "register_operand")
|
||||
(float_truncate:SF
|
||||
(match_operand:DF 1 "memory_operand")))]
|
||||
(float_truncate:SF
|
||||
(match_operand:DF 1 "memory_operand")))]
|
||||
"TARGET_SPLIT_MEM_OPND_FOR_FP_CONVERTS
|
||||
&& optimize_insn_for_speed_p ()
|
||||
&& SSE_REG_P (operands[0])"
|
||||
|
|
|
|||
|
|
@ -1,3 +1,7 @@
|
|||
2013-06-03 Yuri Rumyantsev <yuri.s.rumyantsev@intel.com>
|
||||
|
||||
* config/i386/cpuinfo.c (INTEL_SLM): New enum value.
|
||||
|
||||
2013-05-28 Eric Botcazou <ebotcazou@adacore.com>
|
||||
|
||||
* config/sparc/sol2-unwind.h (MD_FALLBACK_FRAME_STATE_FOR): Do not set
|
||||
|
|
|
|||
|
|
@ -47,14 +47,16 @@ enum processor_vendor
|
|||
VENDOR_MAX
|
||||
};
|
||||
|
||||
/* Any new types or subtypes have to be inserted at the end. */
|
||||
|
||||
enum processor_types
|
||||
{
|
||||
INTEL_ATOM = 1,
|
||||
INTEL_SLM,
|
||||
INTEL_CORE2,
|
||||
INTEL_COREI7,
|
||||
AMDFAM10H,
|
||||
AMDFAM15H,
|
||||
INTEL_SLM,
|
||||
CPU_TYPE_MAX
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue