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i386: Do not sanitize upper part of V2HFmode and V4HFmode reg with -fno-trapping-math [PR110832]

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Also add ix86_partial_vec_fp_math to to condition of V2HF/V4HF named
patterns in order to avoid generation of partial vector V8HFmode
trapping instructions.

gcc/ChangeLog:

	PR target/110832
	* config/i386/mmx.md: (movq_<mode>_to_sse): Also do not
	sanitize upper part of V4HFmode register with
	-fno-trapping-math.
	(<insn>v4hf3): Enable for ix86_partial_vec_fp_math.
	(<divv4hf3): Ditto.
	(<insn>v2hf3): Ditto.
	(divv2hf3): Ditto.
	(movd_v2hf_to_sse): Do not sanitize upper part of V2HFmode
	register with -fno-trapping-math.
This commit is contained in:
liuhongt 2023-08-09 14:25:53 +08:00
parent 4cede0de9a
commit 0c563a935c
1 changed files with 14 additions and 6 deletions
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20
gcc/config/i386/mmx.md
View file

@ -596,7 +596,7 @@
(match_dup 2)))] (match_dup 2)))]
"TARGET_SSE2" "TARGET_SSE2"
{ {
if (<MODE>mode == V2SFmode if (<MODE>mode != V2SImode
&& !flag_trapping_math) && !flag_trapping_math)
{ {
rtx op1 = force_reg (<MODE>mode, operands[1]); rtx op1 = force_reg (<MODE>mode, operands[1]);
@ -1941,7 +1941,7 @@
(plusminusmult:V4HF (plusminusmult:V4HF
(match_operand:V4HF 1 "nonimmediate_operand") (match_operand:V4HF 1 "nonimmediate_operand")
(match_operand:V4HF 2 "nonimmediate_operand")))] (match_operand:V4HF 2 "nonimmediate_operand")))]
"TARGET_AVX512FP16 && TARGET_AVX512VL" "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math"
{ {
rtx op2 = gen_reg_rtx (V8HFmode); rtx op2 = gen_reg_rtx (V8HFmode);
rtx op1 = gen_reg_rtx (V8HFmode); rtx op1 = gen_reg_rtx (V8HFmode);
@ -1961,7 +1961,7 @@
(div:V4HF (div:V4HF
(match_operand:V4HF 1 "nonimmediate_operand") (match_operand:V4HF 1 "nonimmediate_operand")
(match_operand:V4HF 2 "nonimmediate_operand")))] (match_operand:V4HF 2 "nonimmediate_operand")))]
"TARGET_AVX512FP16 && TARGET_AVX512VL" "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math"
{ {
rtx op2 = gen_reg_rtx (V8HFmode); rtx op2 = gen_reg_rtx (V8HFmode);
rtx op1 = gen_reg_rtx (V8HFmode); rtx op1 = gen_reg_rtx (V8HFmode);
@ -1983,14 +1983,22 @@
(match_operand:V2HF 1 "nonimmediate_operand")) (match_operand:V2HF 1 "nonimmediate_operand"))
(match_operand:V8HF 2 "reg_or_0_operand") (match_operand:V8HF 2 "reg_or_0_operand")
(const_int 3)))] (const_int 3)))]
"TARGET_SSE") "TARGET_SSE"
{
if (!flag_trapping_math && operands[2] == CONST0_RTX (V8HFmode))
{
rtx op1 = force_reg (V2HFmode, operands[1]);
emit_move_insn (operands[0], lowpart_subreg (V8HFmode, op1, V2HFmode));
DONE;
}
})
(define_expand "<insn>v2hf3" (define_expand "<insn>v2hf3"
[(set (match_operand:V2HF 0 "register_operand") [(set (match_operand:V2HF 0 "register_operand")
(plusminusmult:V2HF (plusminusmult:V2HF
(match_operand:V2HF 1 "nonimmediate_operand") (match_operand:V2HF 1 "nonimmediate_operand")
(match_operand:V2HF 2 "nonimmediate_operand")))] (match_operand:V2HF 2 "nonimmediate_operand")))]
"TARGET_AVX512FP16 && TARGET_AVX512VL" "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math"
{ {
rtx op2 = gen_reg_rtx (V8HFmode); rtx op2 = gen_reg_rtx (V8HFmode);
rtx op1 = gen_reg_rtx (V8HFmode); rtx op1 = gen_reg_rtx (V8HFmode);
@ -2009,7 +2017,7 @@
(div:V2HF (div:V2HF
(match_operand:V2HF 1 "nonimmediate_operand") (match_operand:V2HF 1 "nonimmediate_operand")
(match_operand:V2HF 2 "nonimmediate_operand")))] (match_operand:V2HF 2 "nonimmediate_operand")))]
"TARGET_AVX512FP16 && TARGET_AVX512VL" "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math"
{ {
rtx op2 = gen_reg_rtx (V8HFmode); rtx op2 = gen_reg_rtx (V8HFmode);
rtx op1 = gen_reg_rtx (V8HFmode); rtx op1 = gen_reg_rtx (V8HFmode);