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iterators.md (VMAXMINFNM): New int iterator.

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2015-12-23  David Sherwood  <david.sherwood@arm.com>

    gcc/
        * config/arm/iterators.md (VMAXMINFNM): New int iterator.
        (fmaxmin): New int attribute.
        (fmaxmin_op): Likewise.
        * config/arm/unspecs.md (UNSPEC_VMAXNM): New unspec.
        (UNSPEC_VMINNM): Likewise.
        * config/arm/neon.md (fmaxmin): New pattern.
        * config/arm/vfp.md (fmaxmin): Likewise.
    gcc/testsuite
        * gcc.target/arm/fmaxmin.x: New file used by tests below.
        * gcc.target/arm/fmaxmin.c: New test.
        * gcc.target/arm/vect-fmaxmin.c: Likewise.

From-SVN: r231924
This commit is contained in:
David Sherwood 2015-12-23 10:28:18 +00:00 • committed by David Sherwood
parent fa87d16dcf
commit 0a18c19f75
9 changed files with 131 additions and 0 deletions
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10
gcc/ChangeLog
View file

@ -1,3 +1,13 @@
2015-12-23 David Sherwood <david.sherwood@arm.com>
* config/arm/iterators.md (VMAXMINFNM): New int iterator.
(fmaxmin): New int attribute.
(fmaxmin_op): Likewise.
* config/arm/unspecs.md (UNSPEC_VMAXNM): New unspec.
(UNSPEC_VMINNM): Likewise.
* config/arm/neon.md (fmaxmin): New pattern.
* config/arm/vfp.md (fmaxmin): Likewise.
2015-12-23 H.J. Lu <hongjiu.lu@intel.com>
PR target/66232

9
gcc/config/arm/iterators.md
View file

@ -308,6 +308,8 @@
(define_int_iterator VMAXMINF [UNSPEC_VMAX UNSPEC_VMIN])
(define_int_iterator VMAXMINFNM [UNSPEC_VMAXNM UNSPEC_VMINNM])
(define_int_iterator VPADDL [UNSPEC_VPADDL_S UNSPEC_VPADDL_U])
(define_int_iterator VPADAL [UNSPEC_VPADAL_S UNSPEC_VPADAL_U])
@ -745,6 +747,13 @@
(UNSPEC_VPMIN "min") (UNSPEC_VPMIN_U "min")
])
(define_int_attr fmaxmin [
(UNSPEC_VMAXNM "fmax") (UNSPEC_VMINNM "fmin")])
(define_int_attr fmaxmin_op [
(UNSPEC_VMAXNM "vmaxnm") (UNSPEC_VMINNM "vminnm")
])
(define_int_attr shift_op [
(UNSPEC_VSHL_S "shl") (UNSPEC_VSHL_U "shl")
(UNSPEC_VRSHL_S "rshl") (UNSPEC_VRSHL_U "rshl")

11
gcc/config/arm/neon.md
View file

@ -2366,6 +2366,17 @@
[(set_attr "type" "neon_fp_minmax_s<q>")]
)
;; Vector forms for the IEEE-754 fmax()/fmin() functions
(define_insn "<fmaxmin><mode>3"
[(set (match_operand:VCVTF 0 "s_register_operand" "=w")
(unspec:VCVTF [(match_operand:VCVTF 1 "s_register_operand" "w")
(match_operand:VCVTF 2 "s_register_operand" "w")]
VMAXMINFNM))]
"TARGET_NEON && TARGET_FPU_ARMV8"
"<fmaxmin_op>.<V_s_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set_attr "type" "neon_fp_minmax_s<q>")]
)
(define_expand "neon_vpadd<mode>"
[(match_operand:VD 0 "s_register_operand" "=w")
(match_operand:VD 1 "s_register_operand" "w")

2
gcc/config/arm/unspecs.md
View file

@ -226,8 +226,10 @@
UNSPEC_VLD4_LANE
UNSPEC_VMAX
UNSPEC_VMAX_U
UNSPEC_VMAXNM
UNSPEC_VMIN
UNSPEC_VMIN_U
UNSPEC_VMINNM
UNSPEC_VMLA
UNSPEC_VMLA_LANE
UNSPEC_VMLAL_S

12
gcc/config/arm/vfp.md
View file

@ -1366,6 +1366,18 @@
(set_attr "conds" "unconditional")]
)
;; Scalar forms for the IEEE-754 fmax()/fmin() functions
(define_insn "<fmaxmin><mode>3"
[(set (match_operand:SDF 0 "s_register_operand" "=<F_constraint>")
(unspec:SDF [(match_operand:SDF 1 "s_register_operand" "<F_constraint>")
(match_operand:SDF 2 "s_register_operand" "<F_constraint>")]
VMAXMINFNM))]
"TARGET_HARD_FLOAT && TARGET_VFP5 <vfp_double_cond>"
"<fmaxmin_op>.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set_attr "type" "f_minmax<vfp_type>")
(set_attr "conds" "unconditional")]
)
;; Write Floating-point Status and Control Register.
(define_insn "set_fpscr"
[(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] VUNSPEC_SET_FPSCR)]

6
gcc/testsuite/ChangeLog
View file

@ -1,3 +1,9 @@
2015-12-23 David Sherwood <david.sherwood@arm.com>
* gcc.target/arm/fmaxmin.x: New file used by tests below.
* gcc.target/arm/fmaxmin.c: New test.
* gcc.target/arm/vect-fmaxmin.c: Likewise.
2015-12-23 H.J. Lu <hongjiu.lu@intel.com>
PR target/66232

13
gcc/testsuite/gcc.target/arm/fmaxmin.c Normal file
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@ -0,0 +1,13 @@
/* { dg-do run } */
/* { dg-require-effective-target arm_v8_neon_ok } */
/* { dg-options "-O2 -fno-inline -march=armv8-a -save-temps" } */
/* { dg-add-options arm_v8_neon } */
#include "fmaxmin.x"
/* { dg-final { scan-assembler-times "vmaxnm.f32\ts\[0-9\]+, s\[0-9\]+, s\[0-9\]+" 1 } } */
/* { dg-final { scan-assembler-times "vminnm.f32\ts\[0-9\]+, s\[0-9\]+, s\[0-9\]+" 1 } } */
/* { dg-final { scan-assembler-times "vmaxnm.f64\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */
/* { dg-final { scan-assembler-times "vminnm.f64\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */

54
gcc/testsuite/gcc.target/arm/fmaxmin.x Normal file
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@ -0,0 +1,54 @@
extern void abort (void);
double fmax (double, double);
float fmaxf (float, float);
double fmin (double, double);
float fminf (float, float);
#define isnan __builtin_isnan
#define isinf __builtin_isinf
#define NAN __builtin_nan ("")
#define INFINITY __builtin_inf ()
#define DEF_MAXMIN(TYPE,FUN)\
void test_##FUN (TYPE *__restrict__ r, TYPE *__restrict__ a,\
TYPE *__restrict__ b)\
{\
int i;\
for (i = 0; i < 4; i++)\
r[i] = FUN (a[i], b[i]);\
}\
DEF_MAXMIN (float, fmaxf)
DEF_MAXMIN (double, fmax)
DEF_MAXMIN (float, fminf)
DEF_MAXMIN (double, fmin)
int main ()
{
float a_f[4] = { 4, NAN, -3, INFINITY };
float b_f[4] = { 1, 7,NAN, 0 };
float r_f[4];
double a_d[4] = { 4, NAN, -3, INFINITY };
double b_d[4] = { 1, 7, NAN, 0 };
double r_d[4];
test_fmaxf (r_f, a_f, b_f);
if (r_f[0] != 4 || isnan (r_f[1]) || isnan (r_f[2]) || !isinf (r_f[3]))
abort ();
test_fminf (r_f, a_f, b_f);
if (r_f[0] != 1 || isnan (r_f[1]) || isnan (r_f[2]) || isinf (r_f[3]))
abort ();
test_fmax (r_d, a_d, b_d);
if (r_d[0] != 4 || isnan (r_d[1]) || isnan (r_d[2]) || !isinf (r_d[3]))
abort ();
test_fmin (r_d, a_d, b_d);
if (r_d[0] != 1 || isnan (r_d[1]) || isnan (r_d[2]) || isinf (r_d[3]))
abort ();
return 0;
}

14
gcc/testsuite/gcc.target/arm/vect-fmaxmin.c Normal file
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@ -0,0 +1,14 @@
/* { dg-do run } */
/* { dg-require-effective-target arm_v8_neon_ok } */
/* { dg-options "-O2 -ftree-vectorize -fno-inline -march=armv8-a -save-temps" } */
/* { dg-add-options arm_v8_neon } */
#include "fmaxmin.x"
/* { dg-final { scan-assembler-times "vmaxnm.f32\tq\[0-9\]+, q\[0-9\]+, q\[0-9\]+" 1 } } */
/* { dg-final { scan-assembler-times "vminnm.f32\tq\[0-9\]+, q\[0-9\]+, q\[0-9\]+" 1 } } */
/* NOTE: There are no double precision vector versions of vmaxnm/vminnm. */
/* { dg-final { scan-assembler-times "vmaxnm.f64\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */
/* { dg-final { scan-assembler-times "vminnm.f64\td\[0-9\]+, d\[0-9\]+, d\[0-9\]+" 1 } } */