rs6000: Add split pattern to replace

7: r120:V4SI=const_vector
8: r121:V4SI=unspec[r120:V4SI,r120:V4SI,0xc] 260

with r121:v4SI = r120:V4SI when r120 is a vector with same element.

gcc/ChangeLog:

	* config/rs6000/altivec.md (sldoi_to_mov<mode>): New.

gcc/testsuite/ChangeLog:

	* gcc.target/powerpc/sldoi_to_mov.c: New test.
This commit is contained in:
Xionghu Luo 2022-01-12 18:36:54 -06:00
parent 02a8a01bf3
commit 080a06fcb0
2 changed files with 26 additions and 0 deletions

View file

@ -383,6 +383,17 @@
}
})
(define_insn_and_split "sldoi_to_mov<mode>"
[(set (match_operand:VM 0 "altivec_register_operand")
(unspec:VM [(match_operand:VM 1 "easy_vector_constant")
(match_dup 1)
(match_operand:QI 2 "u5bit_cint_operand")]
UNSPEC_VSLDOI))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode) && can_create_pseudo_p ()"
"#"
"&& 1"
[(set (match_dup 0) (match_dup 1))])
(define_insn "get_vrsave_internal"
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI [(reg:SI VRSAVE_REGNO)] UNSPEC_GET_VRSAVE))]

View file

@ -0,0 +1,15 @@
/* { dg-do compile } */
/* { dg-options "-O2" } */
#include <altivec.h>
vector signed int foo1 (vector signed int a) {
vector signed int b = {0};
return vec_sum2s(a, b);
}
vector signed int foo2 (vector signed int a) {
vector signed int b = {0};
return vec_sld(b, b, 4);
}
/* { dg-final { scan-assembler-times {\mvsldoi\M} 1 {target le} } } */