i386.md (attribute isa): New.
* config/i386/i386.md (attribute isa): New.
(attribute enabled): New.
(setcc_<mode>_sse): Merge from *{avx,sse}_setcc<mode>.
(*fop_<mode>_comm_mixed): Merge with *fop_<mode>_comm_mixed_avx.
(*fop_<mode>_comm_sse): Merge with *fop_<mode>_comm_avx.
(*fop_<mode>_1_mixed): Merge with *fop_<mode>_1_mixed_avx.
(*fop_<mode>_1_sse): Merge with *fop_<mode>_1_avx.
(<smaxmin:code><mode>3): Merge with *avx_<smaxmin:code><mode>3.
(*ieee_smin<mode>3): Merge with *avx_ieee_smin<mode>3.
(*ieee_smax<mode>3): Merge with *avx_ieee_smax<mode>3.
* config/i386/sse.md (VF): New mode iterator.
(VF1): Ditto.
(VF2): Ditto.
(VF_128): Ditto.
(SSEMODEF4): Remove.
(attribute sse): Handle V8SF and V4DF modes.
(<absneg:code><mode>2): Use VF mode iterator.
(*absneg<mode>2): Merge from *{avx,sse}_absneg<mode>2. Use VF
mode iterator.
(<plusminus_insn><mode>3): Use VF mode iterator.
(*<plusminus_insn><mode>3): Merge with *avx_<plusminus_insn><mode>3.
Use VF mode iterator.
(<sse>_vm<plusminus_insn><mode>3): Merge with
*avx_vm<plusminus_insn><mode>3. Use VF_128 mode iterator.
(mul<mode>3): Use VF mode iterator.
(*mul<mode>3): Merge with *avx_mul<mode>3. Use VF mode iterator.
(<sse>_vmmul<mode>3): Merge with *avx_vmmul<mode>3. Use VF_128
mode iterator.
(div<VF2:mode>3): Merge from divv2df3 and divv4df3.
(div<VF1:mode>3): Merge from divv4sf3 and divv8sf3.
(<sse>_div<mode>3): Merge with *avx_div<mode>3. Use VF mode iterator.
(<sse>_vmdiv<mode>3): Merge with *avx_vmdiv<mode>3. Use VF_128
mode iterator.
(<sse>_rcp<mode>2): Merge from avx_rcpv8sf2 and sse_rcpv4sf2.
Use VF1 mode iterator.
(sse_vmrcpv4sf2): Merge with *avx_vmrcpv4sf2.
(sqrt<VF2:mode>2): New expander.
(sqrt<VF1:mode>2): Merge from sqrtv4sf2 and sqrtv8sf2.
(<sse>_sqrt<mode>2): Merge from avx_sqrtv8sf2, sse_sqrtv4sf, sqrtv4df2
and sqrtv2df2. Use VF mode iterator.
(<sse>_vmsqrt<mode>2): Merge with *avx_vmsqrt<mode>2. Use VF_128
mode iterator.
(rsqrt<VF1:mode>2): Merge from rsqrtv4sf2 and rsqrtv8sf2.
(<sse>_rsqrt<mode>2): Merge from avx_rsqrtv8sf2 and sse_rsqrt4sf2.
Use VF1 mode iterator.
(sse_vmrsqrtv4sf2): Merge with *avx_vmrsqrtv4sf2.
(<smaxmin:code><mode>3): Use VF mode iterator.
(*<smaxmin:code><mode>3_finite): Merge with
*avx_<smaxmin:code><mode>3_finite. Use VF mode iterator.
(*<smaxmin:code><mode>3): Merge with *avx_<smaxmin:code><mode>3.
(<sse>_vm<smaxmin:code><mode>2): Merge with
*avx_vm<smaxmin:code><mode>2. Use VF_128 mode iterator.
(*ieee_smin<mode>3): Merge with *avx_ieee_smin<mode>3. Use VF
mode iterator.
(*ieee_smax<mode>3): Merge with *avx_ieee_smax<mode>3. Use VF
mode iterator.
(sse3_addsubv2df3): Merge with *avx_addsubv2df3.
(sse3_addsubv4sf3): Merge with *avx_addsubv4sf3.
(sse3_h<plusminus_insn>v2df3): Merge with *avx_h<plusminus_insn>v2df3.
(sse3_h<plusminus_insn>v4sf3): Merge with *avx_h<plusminus_insn>v4sf3.
(avx_cmp<mode>3): Rename from avx_cmp<ssemodesuffix><mode>3. Use
VF mode iterator.
(avx_vmcmp<mode>3): Rename from avx_cmp<ssescalarmodesuffix><mode>3.
Use VF_128 mode iterator.
(<sse>_maskcmp<mode>3): Merge with *avx_maskcmp<mode>3. Use VF
mode iterator.
(<sse>_vmmaskcmp<mode>3): Merge with *avx_vmmaskcmp<mode>3. Use
VF_128 mode iterator.
(vcond<mode>): Use VF mode iterator.
* config/i386/predicates.md (sse_comparison_operator): Merge with
avx_comparison_float_operator. Do not declare as special_predicate.
* config/i386/i386.c (struct builtin_description): Update for renamed
compare patterns.
(ix86_expand_args_builtin): Ditto.
(ix86_expand_sse_compare_mask): Ditto.
From-SVN: r172028
This commit is contained in:
Uros Bizjak
parent
ff5d142c9e
commit
07c0852e00
5 changed files with 572 additions and 912 deletions
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@ -1,10 +1,89 @@
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2011-04-06 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/i386.md (attribute isa): New.
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(attribute enabled): New.
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(setcc_<mode>_sse): Merge from *{avx,sse}_setcc<mode>.
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(*fop_<mode>_comm_mixed): Merge with *fop_<mode>_comm_mixed_avx.
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(*fop_<mode>_comm_sse): Merge with *fop_<mode>_comm_avx.
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(*fop_<mode>_1_mixed): Merge with *fop_<mode>_1_mixed_avx.
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(*fop_<mode>_1_sse): Merge with *fop_<mode>_1_avx.
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(<smaxmin:code><mode>3): Merge with *avx_<smaxmin:code><mode>3.
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(*ieee_smin<mode>3): Merge with *avx_ieee_smin<mode>3.
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(*ieee_smax<mode>3): Merge with *avx_ieee_smax<mode>3.
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* config/i386/sse.md (VF): New mode iterator.
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(VF1): Ditto.
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(VF2): Ditto.
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(VF_128): Ditto.
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(SSEMODEF4): Remove.
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(attribute sse): Handle V8SF and V4DF modes.
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(<absneg:code><mode>2): Use VF mode iterator.
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(*absneg<mode>2): Merge from *{avx,sse}_absneg<mode>2. Use VF
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mode iterator.
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(<plusminus_insn><mode>3): Use VF mode iterator.
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(*<plusminus_insn><mode>3): Merge with *avx_<plusminus_insn><mode>3.
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Use VF mode iterator.
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(<sse>_vm<plusminus_insn><mode>3): Merge with
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*avx_vm<plusminus_insn><mode>3. Use VF_128 mode iterator.
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(mul<mode>3): Use VF mode iterator.
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(*mul<mode>3): Merge with *avx_mul<mode>3. Use VF mode iterator.
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(<sse>_vmmul<mode>3): Merge with *avx_vmmul<mode>3. Use VF_128
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mode iterator.
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(div<VF2:mode>3): Merge from divv2df3 and divv4df3.
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(div<VF1:mode>3): Merge from divv4sf3 and divv8sf3.
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(<sse>_div<mode>3): Merge with *avx_div<mode>3. Use VF mode iterator.
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(<sse>_vmdiv<mode>3): Merge with *avx_vmdiv<mode>3. Use VF_128
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mode iterator.
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(<sse>_rcp<mode>2): Merge from avx_rcpv8sf2 and sse_rcpv4sf2.
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Use VF1 mode iterator.
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(sse_vmrcpv4sf2): Merge with *avx_vmrcpv4sf2.
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(sqrt<VF2:mode>2): New expander.
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(sqrt<VF1:mode>2): Merge from sqrtv4sf2 and sqrtv8sf2.
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(<sse>_sqrt<mode>2): Merge from avx_sqrtv8sf2, sse_sqrtv4sf, sqrtv4df2
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and sqrtv2df2. Use VF mode iterator.
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(<sse>_vmsqrt<mode>2): Merge with *avx_vmsqrt<mode>2. Use VF_128
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mode iterator.
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(rsqrt<VF1:mode>2): Merge from rsqrtv4sf2 and rsqrtv8sf2.
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(<sse>_rsqrt<mode>2): Merge from avx_rsqrtv8sf2 and sse_rsqrt4sf2.
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Use VF1 mode iterator.
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(sse_vmrsqrtv4sf2): Merge with *avx_vmrsqrtv4sf2.
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(<smaxmin:code><mode>3): Use VF mode iterator.
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(*<smaxmin:code><mode>3_finite): Merge with
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*avx_<smaxmin:code><mode>3_finite. Use VF mode iterator.
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(*<smaxmin:code><mode>3): Merge with *avx_<smaxmin:code><mode>3.
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(<sse>_vm<smaxmin:code><mode>2): Merge with
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*avx_vm<smaxmin:code><mode>2. Use VF_128 mode iterator.
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(*ieee_smin<mode>3): Merge with *avx_ieee_smin<mode>3. Use VF
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mode iterator.
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(*ieee_smax<mode>3): Merge with *avx_ieee_smax<mode>3. Use VF
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mode iterator.
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(sse3_addsubv2df3): Merge with *avx_addsubv2df3.
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(sse3_addsubv4sf3): Merge with *avx_addsubv4sf3.
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(sse3_h<plusminus_insn>v2df3): Merge with *avx_h<plusminus_insn>v2df3.
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(sse3_h<plusminus_insn>v4sf3): Merge with *avx_h<plusminus_insn>v4sf3.
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(avx_cmp<mode>3): Rename from avx_cmp<ssemodesuffix><mode>3. Use
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VF mode iterator.
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(avx_vmcmp<mode>3): Rename from avx_cmp<ssescalarmodesuffix><mode>3.
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Use VF_128 mode iterator.
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(<sse>_maskcmp<mode>3): Merge with *avx_maskcmp<mode>3. Use VF
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mode iterator.
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(<sse>_vmmaskcmp<mode>3): Merge with *avx_vmmaskcmp<mode>3. Use
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VF_128 mode iterator.
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(vcond<mode>): Use VF mode iterator.
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* config/i386/predicates.md (sse_comparison_operator): Merge with
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avx_comparison_float_operator. Do not declare as special_predicate.
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* config/i386/i386.c (struct builtin_description): Update for renamed
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compare patterns.
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(ix86_expand_args_builtin): Ditto.
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(ix86_expand_sse_compare_mask): Ditto.
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2011-04-06 Richard Guenther <rguenther@suse.de>
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* tree-inline.c (estimate_num_insns): For calls simply account
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for all passed arguments and a used return value.
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2011-04-06 Richard Guenther <rguenther@suse.de>
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PR tree-optimization/47663
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* cgraph.h (struct cgraph_edge): Add call_stmt_size and
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call_stmt_time fields.
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@ -618,7 +697,7 @@
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* config.gcc (*-*-mingw*): Allow as option the
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posix threading model.
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* config/i386/mingw32.h ( SPEC_PTHREAD1, SPEC_PTHREAD2):
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* config/i386/mingw32.h (SPEC_PTHREAD1, SPEC_PTHREAD2):
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New macros defined dependent to TARGET_USE_PTHREAD_BY_DEFAULT
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definition.
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(CPP_SPEC): Add pthread/no-pthread handling.
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@ -25342,12 +25342,12 @@ static const struct builtin_description bdesc_args[] =
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{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
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{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
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{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
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{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpsdv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
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{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpssv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
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{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
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{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
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{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
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{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
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{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
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{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
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{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
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{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
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{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
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{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
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{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
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{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
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{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
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@ -26994,12 +26994,12 @@ ix86_expand_args_builtin (const struct builtin_description *d,
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error ("the last argument must be a 1-bit immediate");
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return const0_rtx;
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case CODE_FOR_avx_cmpsdv2df3:
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case CODE_FOR_avx_cmpssv4sf3:
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case CODE_FOR_avx_cmppdv2df3:
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case CODE_FOR_avx_cmppsv4sf3:
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case CODE_FOR_avx_cmppdv4df3:
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case CODE_FOR_avx_cmppsv8sf3:
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case CODE_FOR_avx_vmcmpv2df3:
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case CODE_FOR_avx_vmcmpv4sf3:
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case CODE_FOR_avx_cmpv2df3:
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case CODE_FOR_avx_cmpv4sf3:
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case CODE_FOR_avx_cmpv4df3:
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case CODE_FOR_avx_cmpv8sf3:
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error ("the last argument must be a 5-bit immediate");
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return const0_rtx;
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@ -32359,6 +32359,7 @@ static rtx
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ix86_expand_sse_compare_mask (enum rtx_code code, rtx op0, rtx op1,
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bool swap_operands)
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{
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rtx (*insn)(rtx, rtx, rtx, rtx);
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enum machine_mode mode = GET_MODE (op0);
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rtx mask = gen_reg_rtx (mode);
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@ -32369,13 +32370,10 @@ ix86_expand_sse_compare_mask (enum rtx_code code, rtx op0, rtx op1,
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op1 = tmp;
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}
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if (mode == DFmode)
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emit_insn (gen_sse2_maskcmpdf3 (mask, op0, op1,
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gen_rtx_fmt_ee (code, mode, op0, op1)));
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else
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emit_insn (gen_sse_maskcmpsf3 (mask, op0, op1,
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gen_rtx_fmt_ee (code, mode, op0, op1)));
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insn = mode == DFmode ? gen_setcc_df_sse : gen_setcc_sf_sse;
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emit_insn (insn (mask, op0, op1,
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gen_rtx_fmt_ee (code, mode, op0, op1)));
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return mask;
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}
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@ -698,6 +698,16 @@
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;; Define attribute to indicate unaligned ssemov insns
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(define_attr "movu" "0,1" (const_string "0"))
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;; Used to control the "enabled" attribute on a per-instruction basis.
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(define_attr "isa" "base,noavx,avx"
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(const_string "base"))
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(define_attr "enabled" ""
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(cond [(eq_attr "isa" "noavx") (symbol_ref "!TARGET_AVX")
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(eq_attr "isa" "avx") (symbol_ref "TARGET_AVX")
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]
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(const_int 1)))
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;; Describe a user's asm statement.
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(define_asm_attributes
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[(set_attr "length" "128")
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@ -10708,27 +10718,19 @@
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;; 0xffffffff is NaN, but not in normalized form, so we can't represent
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;; it directly.
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(define_insn "*avx_setcc<mode>"
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[(set (match_operand:MODEF 0 "register_operand" "=x")
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(match_operator:MODEF 1 "avx_comparison_float_operator"
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[(match_operand:MODEF 2 "register_operand" "x")
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(match_operand:MODEF 3 "nonimmediate_operand" "xm")]))]
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"TARGET_AVX"
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"vcmp%D1s<ssemodefsuffix>\t{%3, %2, %0|%0, %2, %3}"
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[(set_attr "type" "ssecmp")
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(set_attr "prefix" "vex")
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(set_attr "length_immediate" "1")
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(set_attr "mode" "<MODE>")])
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(define_insn "*sse_setcc<mode>"
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[(set (match_operand:MODEF 0 "register_operand" "=x")
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(match_operator:MODEF 1 "sse_comparison_operator"
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[(match_operand:MODEF 2 "register_operand" "0")
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(match_operand:MODEF 3 "nonimmediate_operand" "xm")]))]
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(define_insn "setcc_<mode>_sse"
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[(set (match_operand:MODEF 0 "register_operand" "=x,x")
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(match_operator:MODEF 3 "sse_comparison_operator"
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[(match_operand:MODEF 1 "register_operand" "0,x")
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(match_operand:MODEF 2 "nonimmediate_operand" "xm,xm")]))]
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"SSE_FLOAT_MODE_P (<MODE>mode)"
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"cmp%D1s<ssemodefsuffix>\t{%3, %0|%0, %3}"
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[(set_attr "type" "ssecmp")
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"@
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cmp%D3s<ssemodefsuffix>\t{%2, %0|%0, %2}
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vcmp%D3s<ssemodefsuffix>\t{%2, %1, %0|%0, %1, %2}"
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[(set_attr "isa" "noavx,avx")
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(set_attr "type" "ssecmp")
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(set_attr "length_immediate" "1")
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(set_attr "prefix" "orig,vex")
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(set_attr "mode" "<MODE>")])
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;; Basic conditional jump instructions.
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@ -12865,66 +12867,32 @@
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;; Gcc is slightly more smart about handling normal two address instructions
|
||||
;; so use special patterns for add and mull.
|
||||
|
||||
(define_insn "*fop_<mode>_comm_mixed_avx"
|
||||
[(set (match_operand:MODEF 0 "register_operand" "=f,x")
|
||||
(match_operator:MODEF 3 "binary_fp_operator"
|
||||
[(match_operand:MODEF 1 "nonimmediate_operand" "%0,x")
|
||||
(match_operand:MODEF 2 "nonimmediate_operand" "fm,xm")]))]
|
||||
"AVX_FLOAT_MODE_P (<MODE>mode) && TARGET_MIX_SSE_I387
|
||||
&& COMMUTATIVE_ARITH_P (operands[3])
|
||||
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
|
||||
"* return output_387_binary_op (insn, operands);"
|
||||
[(set (attr "type")
|
||||
(if_then_else (eq_attr "alternative" "1")
|
||||
(if_then_else (match_operand:MODEF 3 "mult_operator" "")
|
||||
(const_string "ssemul")
|
||||
(const_string "sseadd"))
|
||||
(if_then_else (match_operand:MODEF 3 "mult_operator" "")
|
||||
(const_string "fmul")
|
||||
(const_string "fop"))))
|
||||
(set_attr "prefix" "orig,maybe_vex")
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
(define_insn "*fop_<mode>_comm_mixed"
|
||||
[(set (match_operand:MODEF 0 "register_operand" "=f,x")
|
||||
[(set (match_operand:MODEF 0 "register_operand" "=f,x,x")
|
||||
(match_operator:MODEF 3 "binary_fp_operator"
|
||||
[(match_operand:MODEF 1 "nonimmediate_operand" "%0,0")
|
||||
(match_operand:MODEF 2 "nonimmediate_operand" "fm,xm")]))]
|
||||
[(match_operand:MODEF 1 "nonimmediate_operand" "%0,0,x")
|
||||
(match_operand:MODEF 2 "nonimmediate_operand" "fm,xm,xm")]))]
|
||||
"SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_MIX_SSE_I387
|
||||
&& COMMUTATIVE_ARITH_P (operands[3])
|
||||
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
|
||||
"* return output_387_binary_op (insn, operands);"
|
||||
[(set (attr "type")
|
||||
(if_then_else (eq_attr "alternative" "1")
|
||||
(if_then_else (eq_attr "alternative" "1,2")
|
||||
(if_then_else (match_operand:MODEF 3 "mult_operator" "")
|
||||
(const_string "ssemul")
|
||||
(const_string "sseadd"))
|
||||
(if_then_else (match_operand:MODEF 3 "mult_operator" "")
|
||||
(const_string "fmul")
|
||||
(const_string "fop"))))
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
(define_insn "*fop_<mode>_comm_avx"
|
||||
[(set (match_operand:MODEF 0 "register_operand" "=x")
|
||||
(match_operator:MODEF 3 "binary_fp_operator"
|
||||
[(match_operand:MODEF 1 "nonimmediate_operand" "%x")
|
||||
(match_operand:MODEF 2 "nonimmediate_operand" "xm")]))]
|
||||
"AVX_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
|
||||
&& COMMUTATIVE_ARITH_P (operands[3])
|
||||
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
|
||||
"* return output_387_binary_op (insn, operands);"
|
||||
[(set (attr "type")
|
||||
(if_then_else (match_operand:MODEF 3 "mult_operator" "")
|
||||
(const_string "ssemul")
|
||||
(const_string "sseadd")))
|
||||
(set_attr "prefix" "vex")
|
||||
(set_attr "isa" "base,noavx,avx")
|
||||
(set_attr "prefix" "orig,orig,vex")
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
(define_insn "*fop_<mode>_comm_sse"
|
||||
[(set (match_operand:MODEF 0 "register_operand" "=x")
|
||||
[(set (match_operand:MODEF 0 "register_operand" "=x,x")
|
||||
(match_operator:MODEF 3 "binary_fp_operator"
|
||||
[(match_operand:MODEF 1 "nonimmediate_operand" "%0")
|
||||
(match_operand:MODEF 2 "nonimmediate_operand" "xm")]))]
|
||||
[(match_operand:MODEF 1 "nonimmediate_operand" "%0,x")
|
||||
(match_operand:MODEF 2 "nonimmediate_operand" "xm,xm")]))]
|
||||
"SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
|
||||
&& COMMUTATIVE_ARITH_P (operands[3])
|
||||
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
|
||||
|
|
@ -12933,6 +12901,8 @@
|
|||
(if_then_else (match_operand:MODEF 3 "mult_operator" "")
|
||||
(const_string "ssemul")
|
||||
(const_string "sseadd")))
|
||||
(set_attr "isa" "noavx,avx")
|
||||
(set_attr "prefix" "orig,vex")
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
(define_insn "*fop_<mode>_comm_i387"
|
||||
|
|
@ -12950,50 +12920,23 @@
|
|||
(const_string "fop")))
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
(define_insn "*fop_<mode>_1_mixed_avx"
|
||||
[(set (match_operand:MODEF 0 "register_operand" "=f,f,x")
|
||||
(match_operator:MODEF 3 "binary_fp_operator"
|
||||
[(match_operand:MODEF 1 "nonimmediate_operand" "0,fm,x")
|
||||
(match_operand:MODEF 2 "nonimmediate_operand" "fm,0,xm")]))]
|
||||
"AVX_FLOAT_MODE_P (<MODE>mode) && TARGET_MIX_SSE_I387
|
||||
&& !COMMUTATIVE_ARITH_P (operands[3])
|
||||
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
|
||||
"* return output_387_binary_op (insn, operands);"
|
||||
[(set (attr "type")
|
||||
(cond [(and (eq_attr "alternative" "2")
|
||||
(match_operand:MODEF 3 "mult_operator" ""))
|
||||
(const_string "ssemul")
|
||||
(and (eq_attr "alternative" "2")
|
||||
(match_operand:MODEF 3 "div_operator" ""))
|
||||
(const_string "ssediv")
|
||||
(eq_attr "alternative" "2")
|
||||
(const_string "sseadd")
|
||||
(match_operand:MODEF 3 "mult_operator" "")
|
||||
(const_string "fmul")
|
||||
(match_operand:MODEF 3 "div_operator" "")
|
||||
(const_string "fdiv")
|
||||
]
|
||||
(const_string "fop")))
|
||||
(set_attr "prefix" "orig,orig,maybe_vex")
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
(define_insn "*fop_<mode>_1_mixed"
|
||||
[(set (match_operand:MODEF 0 "register_operand" "=f,f,x")
|
||||
[(set (match_operand:MODEF 0 "register_operand" "=f,f,x,x")
|
||||
(match_operator:MODEF 3 "binary_fp_operator"
|
||||
[(match_operand:MODEF 1 "nonimmediate_operand" "0,fm,0")
|
||||
(match_operand:MODEF 2 "nonimmediate_operand" "fm,0,xm")]))]
|
||||
[(match_operand:MODEF 1 "nonimmediate_operand" "0,fm,0,x")
|
||||
(match_operand:MODEF 2 "nonimmediate_operand" "fm,0,xm,xm")]))]
|
||||
"SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_MIX_SSE_I387
|
||||
&& !COMMUTATIVE_ARITH_P (operands[3])
|
||||
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
|
||||
"* return output_387_binary_op (insn, operands);"
|
||||
[(set (attr "type")
|
||||
(cond [(and (eq_attr "alternative" "2")
|
||||
(cond [(and (eq_attr "alternative" "2,3")
|
||||
(match_operand:MODEF 3 "mult_operator" ""))
|
||||
(const_string "ssemul")
|
||||
(and (eq_attr "alternative" "2")
|
||||
(and (eq_attr "alternative" "2,3")
|
||||
(match_operand:MODEF 3 "div_operator" ""))
|
||||
(const_string "ssediv")
|
||||
(eq_attr "alternative" "2")
|
||||
(eq_attr "alternative" "2,3")
|
||||
(const_string "sseadd")
|
||||
(match_operand:MODEF 3 "mult_operator" "")
|
||||
(const_string "fmul")
|
||||
|
|
@ -13001,6 +12944,8 @@
|
|||
(const_string "fdiv")
|
||||
]
|
||||
(const_string "fop")))
|
||||
(set_attr "isa" "base,base,noavx,avx")
|
||||
(set_attr "prefix" "orig,orig,orig,vex")
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
(define_insn "*rcpsf2_sse"
|
||||
|
|
@ -13014,29 +12959,11 @@
|
|||
(set_attr "prefix" "maybe_vex")
|
||||
(set_attr "mode" "SF")])
|
||||
|
||||
(define_insn "*fop_<mode>_1_avx"
|
||||
[(set (match_operand:MODEF 0 "register_operand" "=x")
|
||||
(match_operator:MODEF 3 "binary_fp_operator"
|
||||
[(match_operand:MODEF 1 "register_operand" "x")
|
||||
(match_operand:MODEF 2 "nonimmediate_operand" "xm")]))]
|
||||
"AVX_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
|
||||
&& !COMMUTATIVE_ARITH_P (operands[3])"
|
||||
"* return output_387_binary_op (insn, operands);"
|
||||
[(set (attr "type")
|
||||
(cond [(match_operand:MODEF 3 "mult_operator" "")
|
||||
(const_string "ssemul")
|
||||
(match_operand:MODEF 3 "div_operator" "")
|
||||
(const_string "ssediv")
|
||||
]
|
||||
(const_string "sseadd")))
|
||||
(set_attr "prefix" "vex")
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
(define_insn "*fop_<mode>_1_sse"
|
||||
[(set (match_operand:MODEF 0 "register_operand" "=x")
|
||||
[(set (match_operand:MODEF 0 "register_operand" "=x,x")
|
||||
(match_operator:MODEF 3 "binary_fp_operator"
|
||||
[(match_operand:MODEF 1 "register_operand" "0")
|
||||
(match_operand:MODEF 2 "nonimmediate_operand" "xm")]))]
|
||||
[(match_operand:MODEF 1 "register_operand" "0,x")
|
||||
(match_operand:MODEF 2 "nonimmediate_operand" "xm,xm")]))]
|
||||
"SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
|
||||
&& !COMMUTATIVE_ARITH_P (operands[3])"
|
||||
"* return output_387_binary_op (insn, operands);"
|
||||
|
|
@ -13047,6 +12974,8 @@
|
|||
(const_string "ssediv")
|
||||
]
|
||||
(const_string "sseadd")))
|
||||
(set_attr "isa" "noavx,avx")
|
||||
(set_attr "prefix" "orig,vex")
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
;; This pattern is not fully shadowed by the pattern above.
|
||||
|
|
@ -16473,25 +16402,18 @@
|
|||
;; Since both the tree-level MAX_EXPR and the rtl-level SMAX operator
|
||||
;; are undefined in this condition, we're certain this is correct.
|
||||
|
||||
(define_insn "*avx_<code><mode>3"
|
||||
[(set (match_operand:MODEF 0 "register_operand" "=x")
|
||||
(smaxmin:MODEF
|
||||
(match_operand:MODEF 1 "nonimmediate_operand" "%x")
|
||||
(match_operand:MODEF 2 "nonimmediate_operand" "xm")))]
|
||||
"AVX_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
|
||||
"v<maxmin_float>s<ssemodefsuffix>\t{%2, %1, %0|%0, %1, %2}"
|
||||
[(set_attr "type" "sseadd")
|
||||
(set_attr "prefix" "vex")
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
(define_insn "<code><mode>3"
|
||||
[(set (match_operand:MODEF 0 "register_operand" "=x")
|
||||
[(set (match_operand:MODEF 0 "register_operand" "=x,x")
|
||||
(smaxmin:MODEF
|
||||
(match_operand:MODEF 1 "nonimmediate_operand" "%0")
|
||||
(match_operand:MODEF 2 "nonimmediate_operand" "xm")))]
|
||||
(match_operand:MODEF 1 "nonimmediate_operand" "%0,x")
|
||||
(match_operand:MODEF 2 "nonimmediate_operand" "xm,xm")))]
|
||||
"SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
|
||||
"<maxmin_float>s<ssemodefsuffix>\t{%2, %0|%0, %2}"
|
||||
[(set_attr "type" "sseadd")
|
||||
"@
|
||||
<maxmin_float>s<ssemodefsuffix>\t{%2, %0|%0, %2}
|
||||
v<maxmin_float>s<ssemodefsuffix>\t{%2, %1, %0|%0, %1, %2}"
|
||||
[(set_attr "isa" "noavx,avx")
|
||||
(set_attr "prefix" "orig,vex")
|
||||
(set_attr "type" "sseadd")
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
;; These versions of the min/max patterns implement exactly the operations
|
||||
|
|
@ -16500,50 +16422,34 @@
|
|||
;; Their operands are not commutative, and thus they may be used in the
|
||||
;; presence of -0.0 and NaN.
|
||||
|
||||
(define_insn "*avx_ieee_smin<mode>3"
|
||||
[(set (match_operand:MODEF 0 "register_operand" "=x")
|
||||
(unspec:MODEF
|
||||
[(match_operand:MODEF 1 "register_operand" "x")
|
||||
(match_operand:MODEF 2 "nonimmediate_operand" "xm")]
|
||||
UNSPEC_IEEE_MIN))]
|
||||
"AVX_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
|
||||
"vmins<ssemodefsuffix>\t{%2, %1, %0|%0, %1, %2}"
|
||||
[(set_attr "type" "sseadd")
|
||||
(set_attr "prefix" "vex")
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
(define_insn "*ieee_smin<mode>3"
|
||||
[(set (match_operand:MODEF 0 "register_operand" "=x")
|
||||
[(set (match_operand:MODEF 0 "register_operand" "=x,x")
|
||||
(unspec:MODEF
|
||||
[(match_operand:MODEF 1 "register_operand" "0")
|
||||
(match_operand:MODEF 2 "nonimmediate_operand" "xm")]
|
||||
[(match_operand:MODEF 1 "register_operand" "0,x")
|
||||
(match_operand:MODEF 2 "nonimmediate_operand" "xm,xm")]
|
||||
UNSPEC_IEEE_MIN))]
|
||||
"SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
|
||||
"mins<ssemodefsuffix>\t{%2, %0|%0, %2}"
|
||||
[(set_attr "type" "sseadd")
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
(define_insn "*avx_ieee_smax<mode>3"
|
||||
[(set (match_operand:MODEF 0 "register_operand" "=x")
|
||||
(unspec:MODEF
|
||||
[(match_operand:MODEF 1 "register_operand" "0")
|
||||
(match_operand:MODEF 2 "nonimmediate_operand" "xm")]
|
||||
UNSPEC_IEEE_MAX))]
|
||||
"AVX_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
|
||||
"vmaxs<ssemodefsuffix>\t{%2, %1, %0|%0, %1, %2}"
|
||||
[(set_attr "type" "sseadd")
|
||||
(set_attr "prefix" "vex")
|
||||
"@
|
||||
mins<ssemodefsuffix>\t{%2, %0|%0, %2}
|
||||
vmins<ssemodefsuffix>\t{%2, %1, %0|%0, %1, %2}"
|
||||
[(set_attr "isa" "noavx,avx")
|
||||
(set_attr "prefix" "orig,vex")
|
||||
(set_attr "type" "sseadd")
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
(define_insn "*ieee_smax<mode>3"
|
||||
[(set (match_operand:MODEF 0 "register_operand" "=x")
|
||||
[(set (match_operand:MODEF 0 "register_operand" "=x,x")
|
||||
(unspec:MODEF
|
||||
[(match_operand:MODEF 1 "register_operand" "0")
|
||||
(match_operand:MODEF 2 "nonimmediate_operand" "xm")]
|
||||
[(match_operand:MODEF 1 "register_operand" "0,x")
|
||||
(match_operand:MODEF 2 "nonimmediate_operand" "xm,xm")]
|
||||
UNSPEC_IEEE_MAX))]
|
||||
"SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
|
||||
"maxs<ssemodefsuffix>\t{%2, %0|%0, %2}"
|
||||
[(set_attr "type" "sseadd")
|
||||
"@
|
||||
maxs<ssemodefsuffix>\t{%2, %0|%0, %2}
|
||||
vmaxs<ssemodefsuffix>\t{%2, %1, %0|%0, %1, %2}"
|
||||
[(set_attr "isa" "noavx,avx")
|
||||
(set_attr "prefix" "orig,vex")
|
||||
(set_attr "type" "sseadd")
|
||||
(set_attr "mode" "<MODE>")])
|
||||
|
||||
;; Make two stack loads independent:
|
||||
|
|
|
|||
|
|
@ -969,19 +969,11 @@
|
|||
;; Return true if OP is a comparison that can be used in the CMPSS/CMPPS insns.
|
||||
;; The first set are supported directly; the second set can't be done with
|
||||
;; full IEEE support, i.e. NaNs.
|
||||
;;
|
||||
;; ??? It would seem that we have a lot of uses of this predicate that pass
|
||||
;; it the wrong mode. We got away with this because the old function didn't
|
||||
;; check the mode at all. Mirror that for now by calling this a special
|
||||
;; predicate.
|
||||
|
||||
(define_special_predicate "sse_comparison_operator"
|
||||
(match_code "eq,lt,le,unordered,ne,unge,ungt,ordered"))
|
||||
|
||||
;; Return true if OP is a comparison operator that can be issued by
|
||||
;; avx predicate generation instructions
|
||||
(define_predicate "avx_comparison_float_operator"
|
||||
(match_code "ne,eq,ge,gt,le,lt,unordered,ordered,uneq,unge,ungt,unle,unlt,ltgt"))
|
||||
(define_predicate "sse_comparison_operator"
|
||||
(ior (match_code "eq,ne,lt,le,unordered,unge,ungt,ordered")
|
||||
(and (match_code "ge,gt,uneq,unle,unlt,ltgt")
|
||||
(match_test "TARGET_AVX"))))
|
||||
|
||||
(define_predicate "ix86_comparison_int_operator"
|
||||
(match_code "ne,eq,ge,gt,le,lt"))
|
||||
|
|
|
|||
File diff suppressed because it is too large
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Add table
Reference in a new issue