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rs6000: Fix more testsuite fallout from rs6000_legitimate_address_p() fix. [PR93913]

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PR target/93913
	* gcc.target/powerpc/fold-vec-st-char.c (scan-assembler-times): Allow
	stxv and stxvx instructions as well.
	* gcc.target/powerpc/fold-vec-st-float.c: Likewise.
	* gcc.target/powerpc/fold-vec-st-int.c: Likewise.
	* gcc.target/powerpc/fold-vec-st-short.c: Likewise.
This commit is contained in:
Peter Bergner 2020-02-26 11:58:08 -06:00
parent 44f6b7fb57
commit 051b9873e7
5 changed files with 13 additions and 4 deletions
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9
gcc/testsuite/ChangeLog
View file

@ -1,3 +1,12 @@
2020-02-26 Peter Bergner <bergner@linux.ibm.com>
PR target/93913
* gcc.target/powerpc/fold-vec-st-char.c (scan-assembler-times): Allow
stxv and stxvx instructions as well.
* gcc.target/powerpc/fold-vec-st-float.c: Likewise.
* gcc.target/powerpc/fold-vec-st-int.c: Likewise.
* gcc.target/powerpc/fold-vec-st-short.c: Likewise.
2020-02-26 Patrick Palka <ppalka@redhat.com>
* g++.dg/concepts/diagnostic2.C: New test.

2
gcc/testsuite/gcc.target/powerpc/fold-vec-st-char.c
View file

@ -91,4 +91,4 @@ testst_cst7 (vector bool char vbc1, int i1, signed char * vscp)
return vec_st(vbc1, 36, vscp);
}
/* { dg-final { scan-assembler-times {\mstvx\M} 14 } } */
/* { dg-final { scan-assembler-times {\m(?:stvx|stxv|stxvx)\M} 14 } } */

2
gcc/testsuite/gcc.target/powerpc/fold-vec-st-float.c
View file

@ -31,4 +31,4 @@ testst_cst2 (vector float vf1, int i1, float * fp)
return vec_st(vf1, 24, fp);
}
/* { dg-final { scan-assembler-times {\mstvx\M} 4 } } */
/* { dg-final { scan-assembler-times {\m(?:stvx|stxv|stxvx)\M} 4 } } */

2
gcc/testsuite/gcc.target/powerpc/fold-vec-st-int.c
View file

@ -80,5 +80,5 @@ testst_cst7 (vector bool int vbi1, int i1, signed int * vsip)
return vec_st(vbi1, 36, vsip);
}
/* { dg-final { scan-assembler-times {\mstvx\M} 14 } } */
/* { dg-final { scan-assembler-times {\m(?:stvx|stxv|stxvx)\M} 14 } } */

2
gcc/testsuite/gcc.target/powerpc/fold-vec-st-short.c
View file

@ -80,4 +80,4 @@ testst_cst7 (vector bool short vbs1, int i1, signed short * vssp)
return vec_st(vbs1, 36, vssp);
}
/* { dg-final { scan-assembler-times {\mstvx\M} 14} } */
/* { dg-final { scan-assembler-times {\m(?:stvx|stxv|stxvx)\M} 14} } */