aarch64: Add -mtune=neoverse-512tvb
This patch adds an option to tune for Neoverse cores that have a total vector bandwidth of 512 bits (4x128 for Advanced SIMD and a vector-length-dependent equivalent for SVE). This is intended to be a compromise between tuning aggressively for a single core like Neoverse V1 (which can be too narrow) and tuning for AArch64 cores in general (which can be too wide). -mcpu=neoverse-512tvb is equivalent to -mcpu=neoverse-v1 -mtune=neoverse-512tvb. gcc/ * doc/invoke.texi: Document -mtune=neoverse-512tvb and -mcpu=neoverse-512tvb. * config/aarch64/aarch64-cores.def (neoverse-512tvb): New entry. * config/aarch64/aarch64-tune.md: Regenerate. * config/aarch64/aarch64.c (neoverse512tvb_sve_vector_cost) (neoverse512tvb_sve_issue_info, neoverse512tvb_vec_issue_info) (neoverse512tvb_vector_cost, neoverse512tvb_tunings): New structures. (aarch64_adjust_body_cost_sve): Handle -mtune=neoverse-512tvb. (aarch64_adjust_body_cost): Likewise.
This commit is contained in:
Richard Sandiford
parent
9690309baf
commit
048039c49b
4 changed files with 202 additions and 12 deletions
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@ -139,6 +139,7 @@ AARCH64_CORE("thunderx3t110", thunderx3t110, thunderx3t110, 8_3A, AARCH64_FL_
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/* Arm ('A') cores. */
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AARCH64_CORE("zeus", zeus, cortexa57, 8_4A, AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_SVE | AARCH64_FL_RCPC | AARCH64_FL_I8MM | AARCH64_FL_BF16 | AARCH64_FL_F16 | AARCH64_FL_PROFILE | AARCH64_FL_SSBS | AARCH64_FL_RNG, neoversev1, 0x41, 0xd40, -1)
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AARCH64_CORE("neoverse-v1", neoversev1, cortexa57, 8_4A, AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_SVE | AARCH64_FL_RCPC | AARCH64_FL_I8MM | AARCH64_FL_BF16 | AARCH64_FL_F16 | AARCH64_FL_PROFILE | AARCH64_FL_SSBS | AARCH64_FL_RNG, neoversev1, 0x41, 0xd40, -1)
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AARCH64_CORE("neoverse-512tvb", neoverse512tvb, cortexa57, 8_4A, AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_SVE | AARCH64_FL_RCPC | AARCH64_FL_I8MM | AARCH64_FL_BF16 | AARCH64_FL_F16 | AARCH64_FL_PROFILE | AARCH64_FL_SSBS | AARCH64_FL_RNG, neoverse512tvb, INVALID_IMP, INVALID_CORE, -1)
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/* Qualcomm ('Q') cores. */
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AARCH64_CORE("saphira", saphira, saphira, 8_4A, AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_CRYPTO | AARCH64_FL_RCPC, saphira, 0x51, 0xC01, -1)
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@ -1,5 +1,5 @@
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;; -*- buffer-read-only: t -*-
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;; Generated automatically by gentune.sh from aarch64-cores.def
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(define_attr "tune"
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"cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunderxt81,thunderxt83,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortexa76ae,cortexa77,cortexa78,cortexa78ae,cortexa78c,cortexa65,cortexa65ae,cortexx1,ares,neoversen1,neoversee1,octeontx2,octeontx2t98,octeontx2t96,octeontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95mm,a64fx,tsv110,thunderx3t110,zeus,neoversev1,saphira,neoversen2,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55,cortexr82"
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"cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunderxt81,thunderxt83,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortexa76ae,cortexa77,cortexa78,cortexa78ae,cortexa78c,cortexa65,cortexa65ae,cortexx1,ares,neoversen1,neoversee1,octeontx2,octeontx2t98,octeontx2t96,octeontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95mm,a64fx,tsv110,thunderx3t110,zeus,neoversev1,neoverse512tvb,saphira,neoversen2,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55,cortexr82"
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(const (symbol_ref "((enum attr_tune) aarch64_tune)")))
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@ -1842,6 +1842,136 @@ static const struct tune_params neoversev1_tunings =
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&generic_prefetch_tune
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};
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static const sve_vec_cost neoverse512tvb_sve_vector_cost =
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{
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{
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2, /* int_stmt_cost */
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2, /* fp_stmt_cost */
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4, /* ld2_st2_permute_cost */
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5, /* ld3_st3_permute_cost */
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5, /* ld4_st4_permute_cost */
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3, /* permute_cost */
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/* Theoretically, a reduction involving 15 scalar ADDs could
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complete in ~5 cycles and would have a cost of 15. Assume that
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[SU]ADDV completes in 11 cycles and so give it a cost of 15 + 6. */
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21, /* reduc_i8_cost */
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/* Likewise for 7 scalar ADDs (~3 cycles) vs. 9: 7 + 6. */
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13, /* reduc_i16_cost */
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/* Likewise for 3 scalar ADDs (~2 cycles) vs. 8: 3 + 6. */
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9, /* reduc_i32_cost */
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/* Likewise for 1 scalar ADD (1 cycle) vs. 8: 1 + 7. */
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8, /* reduc_i64_cost */
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/* Theoretically, a reduction involving 7 scalar FADDs could
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complete in ~6 cycles and would have a cost of 14. Assume that
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FADDV completes in 8 cycles and so give it a cost of 14 + 2. */
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16, /* reduc_f16_cost */
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/* Likewise for 3 scalar FADDs (~4 cycles) vs. 6: 6 + 2. */
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8, /* reduc_f32_cost */
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/* Likewise for 1 scalar FADD (2 cycles) vs. 4: 2 + 2. */
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4, /* reduc_f64_cost */
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2, /* store_elt_extra_cost */
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/* This value is just inherited from the Cortex-A57 table. */
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8, /* vec_to_scalar_cost */
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/* This depends very much on what the scalar value is and
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where it comes from. E.g. some constants take two dependent
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instructions or a load, while others might be moved from a GPR.
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4 seems to be a reasonable compromise in practice. */
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4, /* scalar_to_vec_cost */
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4, /* align_load_cost */
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4, /* unalign_load_cost */
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/* Although stores generally have a latency of 2 and compete for the
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vector pipes, in practice it's better not to model that. */
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1, /* unalign_store_cost */
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1 /* store_cost */
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},
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3, /* clast_cost */
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10, /* fadda_f16_cost */
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6, /* fadda_f32_cost */
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4, /* fadda_f64_cost */
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/* A strided Advanced SIMD x64 load would take two parallel FP loads
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(6 cycles) plus an insertion (2 cycles). Assume a 64-bit SVE gather
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is 1 cycle more. The Advanced SIMD version is costed as 2 scalar loads
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(cost 8) and a vec_construct (cost 2). Add a full vector operation
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(cost 2) to that, to avoid the difference being lost in rounding.
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There is no easy comparison between a strided Advanced SIMD x32 load
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and an SVE 32-bit gather, but cost an SVE 32-bit gather as 1 vector
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operation more than a 64-bit gather. */
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14, /* gather_load_x32_cost */
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12, /* gather_load_x64_cost */
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3 /* scatter_store_elt_cost */
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};
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static const aarch64_sve_vec_issue_info neoverse512tvb_sve_issue_info =
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{
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{
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{
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3, /* loads_per_cycle */
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2, /* stores_per_cycle */
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4, /* general_ops_per_cycle */
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0, /* fp_simd_load_general_ops */
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1 /* fp_simd_store_general_ops */
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},
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2, /* ld2_st2_general_ops */
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2, /* ld3_st3_general_ops */
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3 /* ld4_st4_general_ops */
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},
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2, /* pred_ops_per_cycle */
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2, /* while_pred_ops */
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2, /* int_cmp_pred_ops */
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1, /* fp_cmp_pred_ops */
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1, /* gather_scatter_pair_general_ops */
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1 /* gather_scatter_pair_pred_ops */
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};
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static const aarch64_vec_issue_info neoverse512tvb_vec_issue_info =
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{
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&neoversev1_scalar_issue_info,
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&neoversev1_advsimd_issue_info,
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&neoverse512tvb_sve_issue_info
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};
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static const struct cpu_vector_cost neoverse512tvb_vector_cost =
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{
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1, /* scalar_int_stmt_cost */
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2, /* scalar_fp_stmt_cost */
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4, /* scalar_load_cost */
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1, /* scalar_store_cost */
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1, /* cond_taken_branch_cost */
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1, /* cond_not_taken_branch_cost */
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&neoversev1_advsimd_vector_cost, /* advsimd */
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&neoverse512tvb_sve_vector_cost, /* sve */
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&neoverse512tvb_vec_issue_info /* issue_info */
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};
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static const struct tune_params neoverse512tvb_tunings =
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{
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&cortexa76_extra_costs,
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&neoversev1_addrcost_table,
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&generic_regmove_cost,
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&neoverse512tvb_vector_cost,
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&generic_branch_cost,
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&generic_approx_modes,
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SVE_128 | SVE_256, /* sve_width */
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4, /* memmov_cost */
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3, /* issue_rate */
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(AARCH64_FUSE_AES_AESMC | AARCH64_FUSE_CMP_BRANCH), /* fusible_ops */
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"32:16", /* function_align. */
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"4", /* jump_align. */
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"32:16", /* loop_align. */
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2, /* int_reassoc_width. */
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4, /* fp_reassoc_width. */
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2, /* vec_reassoc_width. */
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2, /* min_div_recip_mul_sf. */
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2, /* min_div_recip_mul_df. */
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0, /* max_case_values. */
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tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */
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(AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS
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| AARCH64_EXTRA_TUNE_USE_NEW_VECTOR_COSTS
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| AARCH64_EXTRA_TUNE_MATCHED_VECTOR_THROUGHPUT), /* tune_flags. */
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&generic_prefetch_tune
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};
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static const struct tune_params neoversen2_tunings =
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{
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&cortexa76_extra_costs,
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@ -15569,10 +15699,32 @@ aarch64_adjust_body_cost_sve (const aarch64_vector_costs *costs,
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{
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/* Estimate the minimum number of cycles per iteration needed to issue
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non-predicate operations. */
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fractional_cost sve_nonpred_cycles_per_iter
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fractional_cost sve_nonpred_issue_cycles_per_iter
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= aarch64_estimate_min_cycles_per_iter (&costs->sve_ops,
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issue_info->sve);
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/* Estimate the minimum number of cycles per iteration needed to rename
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SVE instructions.
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??? For now this is done inline rather than via cost tables, since it
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isn't clear how it should be parameterized for the general case. */
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fractional_cost sve_rename_cycles_per_iter = 0;
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if (issue_info == &neoverse512tvb_vec_issue_info)
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/* + 1 for an addition. We've already counted a general op for each
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store, so we don't need to account for stores separately. The branch
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reads no registers and so does not need to be counted either.
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??? This value is very much on the pessimistic side, but seems to work
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pretty well in practice. */
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sve_rename_cycles_per_iter
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= { costs->sve_ops.general_ops
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+ costs->sve_ops.loads
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+ costs->sve_ops.pred_ops + 1, 5 };
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/* Combine the rename and non-predicate issue limits into a single value. */
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fractional_cost sve_nonpred_cycles_per_iter
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= std::max (sve_nonpred_issue_cycles_per_iter, sve_rename_cycles_per_iter);
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/* Separately estimate the minimum number of cycles per iteration needed
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to issue the predicate operations. */
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fractional_cost sve_pred_issue_cycles_per_iter
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@ -15588,14 +15740,17 @@ aarch64_adjust_body_cost_sve (const aarch64_vector_costs *costs,
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dump_printf_loc (MSG_NOTE, vect_location,
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" estimated cycles per iteration = %f\n",
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sve_cycles_per_iter.as_double ());
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dump_printf_loc (MSG_NOTE, vect_location,
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" estimated cycles per iteration for non-predicate"
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" operations = %f\n",
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sve_nonpred_cycles_per_iter.as_double ());
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if (costs->sve_ops.pred_ops)
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dump_printf_loc (MSG_NOTE, vect_location, " estimated cycles per"
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" iteration for predicate operations = %d\n",
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dump_printf_loc (MSG_NOTE, vect_location,
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" predicate issue = %f\n",
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sve_pred_issue_cycles_per_iter.as_double ());
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if (costs->sve_ops.pred_ops || sve_rename_cycles_per_iter)
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dump_printf_loc (MSG_NOTE, vect_location,
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" non-predicate issue = %f\n",
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sve_nonpred_issue_cycles_per_iter.as_double ());
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if (sve_rename_cycles_per_iter)
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dump_printf_loc (MSG_NOTE, vect_location, " rename = %f\n",
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sve_rename_cycles_per_iter.as_double ());
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}
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/* If the scalar version of the loop could issue at least as
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@ -15770,6 +15925,21 @@ aarch64_adjust_body_cost (aarch64_vector_costs *costs, unsigned int body_cost)
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advsimd_cycles_per_iter,
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could_use_advsimd, orig_body_cost,
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&body_cost, &should_disparage);
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if (aarch64_tune_params.vec_costs == &neoverse512tvb_vector_cost)
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{
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/* Also take Neoverse V1 tuning into account, doubling the
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scalar and Advanced SIMD estimates to account for the
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doubling in SVE vector length. */
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if (dump_enabled_p ())
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dump_printf_loc (MSG_NOTE, vect_location,
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"Neoverse V1 estimate:\n");
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aarch64_adjust_body_cost_sve (costs, &neoversev1_vec_issue_info,
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scalar_cycles_per_iter * 2,
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advsimd_cycles_per_iter * 2,
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could_use_advsimd, orig_body_cost,
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&body_cost, &should_disparage);
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}
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}
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/* Decide whether to stick to latency-based costs or whether to try to
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@ -18407,10 +18407,10 @@ performance of the code. Permissible values for this option are:
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@samp{cortex-a65}, @samp{cortex-a65ae}, @samp{cortex-a34},
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@samp{cortex-a78}, @samp{cortex-a78ae}, @samp{cortex-a78c},
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@samp{ares}, @samp{exynos-m1}, @samp{emag}, @samp{falkor},
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@samp{neoverse-e1}, @samp{neoverse-n1}, @samp{neoverse-n2},
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@samp{neoverse-v1}, @samp{qdf24xx}, @samp{saphira},
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@samp{phecda}, @samp{xgene1}, @samp{vulcan}, @samp{octeontx},
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@samp{octeontx81}, @samp{octeontx83},
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@samp{neoverse-512tvb}, @samp{neoverse-e1}, @samp{neoverse-n1},
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@samp{neoverse-n2}, @samp{neoverse-v1}, @samp{qdf24xx},
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@samp{saphira}, @samp{phecda}, @samp{xgene1}, @samp{vulcan},
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@samp{octeontx}, @samp{octeontx81}, @samp{octeontx83},
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@samp{octeontx2}, @samp{octeontx2t98}, @samp{octeontx2t96}
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@samp{octeontx2t93}, @samp{octeontx2f95}, @samp{octeontx2f95n},
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@samp{octeontx2f95mm},
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@ -18428,6 +18428,15 @@ The values @samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53},
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@samp{cortex-a75.cortex-a55}, @samp{cortex-a76.cortex-a55} specify that GCC
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should tune for a big.LITTLE system.
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The value @samp{neoverse-512tvb} specifies that GCC should tune
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for Neoverse cores that (a) implement SVE and (b) have a total vector
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bandwidth of 512 bits per cycle. In other words, the option tells GCC to
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tune for Neoverse cores that can execute 4 128-bit Advanced SIMD arithmetic
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instructions a cycle and that can execute an equivalent number of SVE
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arithmetic instructions per cycle (2 for 256-bit SVE, 4 for 128-bit SVE).
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This is more general than tuning for a specific core like Neoverse V1
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but is more specific than the default tuning described below.
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Additionally on native AArch64 GNU/Linux systems the value
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@samp{native} tunes performance to the host system. This option has no effect
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if the compiler is unable to recognize the processor of the host system.
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@ -18457,6 +18466,16 @@ by @option{-mtune}). Where this option is used in conjunction
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with @option{-march} or @option{-mtune}, those options take precedence
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over the appropriate part of this option.
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@option{-mcpu=neoverse-512tvb} is special in that it does not refer
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to a specific core, but instead refers to all Neoverse cores that
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(a) implement SVE and (b) have a total vector bandwidth of 512 bits
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a cycle. Unless overridden by @option{-march},
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@option{-mcpu=neoverse-512tvb} generates code that can run on a
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Neoverse V1 core, since Neoverse V1 is the first Neoverse core with
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these properties. Unless overridden by @option{-mtune},
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@option{-mcpu=neoverse-512tvb} tunes code in the same way as for
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@option{-mtune=neoverse-512tvb}.
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@item -moverride=@var{string}
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@opindex moverride
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Override tuning decisions made by the back-end in response to a
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