aarch64: Enable the use of LDAPR for load-acquire semantics
This patch enables the use of LDAPR for load-acquire semantics. 2022-11-15 Andre Vieira <andre.simoesdiasvieira@arm.com> Kyrylo Tkachov <kyrylo.tkachov@arm.com> gcc/ChangeLog: * config/aarch64/aarch64.h (AARCH64_ISA_RCPC): New Macro. (TARGET_RCPC): New Macro. * config/aarch64/atomics.md (atomic_load<mode>): Change into an expand. (aarch64_atomic_load<mode>_rcpc): New define_insn for ldapr. (aarch64_atomic_load<mode>): Rename of old define_insn for ldar. * config/aarch64/iterators.md (UNSPEC_LDAP): New unspec enum value. * doc/invoke.texi (rcpc): Ammend documentation to mention the effects on code generation. gcc/testsuite/ChangeLog: * gcc.target/aarch64/ldapr.c: New test.
This commit is contained in:
Andre Vieira
parent
9a4129f5c5
commit
0431e8ae5b
5 changed files with 74 additions and 4 deletions
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@ -222,6 +222,7 @@ enum class aarch64_feature : unsigned char {
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#define AARCH64_ISA_MOPS (aarch64_isa_flags & AARCH64_FL_MOPS)
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#define AARCH64_ISA_LS64 (aarch64_isa_flags & AARCH64_FL_LS64)
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#define AARCH64_ISA_CSSC (aarch64_isa_flags & AARCH64_FL_CSSC)
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#define AARCH64_ISA_RCPC (aarch64_isa_flags & AARCH64_FL_RCPC)
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/* Crypto is an optional extension to AdvSIMD. */
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#define TARGET_CRYPTO (AARCH64_ISA_CRYPTO)
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@ -332,6 +333,9 @@ enum class aarch64_feature : unsigned char {
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/* SB instruction is enabled through +sb. */
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#define TARGET_SB (AARCH64_ISA_SB)
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/* RCPC loads from Armv8.3-a. */
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#define TARGET_RCPC (AARCH64_ISA_RCPC)
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/* Apply the workaround for Cortex-A53 erratum 835769. */
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#define TARGET_FIX_ERR_A53_835769 \
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((aarch64_fix_a53_err835769 == 2) \
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@ -657,7 +657,38 @@
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}
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)
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(define_insn "atomic_load<mode>"
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(define_expand "atomic_load<mode>"
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[(match_operand:ALLI 0 "register_operand" "=r")
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(match_operand:ALLI 1 "aarch64_sync_memory_operand" "Q")
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(match_operand:SI 2 "const_int_operand")]
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""
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{
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/* If TARGET_RCPC and this is an ACQUIRE load, then expand to a pattern
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using UNSPECV_LDAP. */
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enum memmodel model = memmodel_from_int (INTVAL (operands[2]));
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if (TARGET_RCPC
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&& (is_mm_acquire (model)
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|| is_mm_acq_rel (model)))
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emit_insn (gen_aarch64_atomic_load<mode>_rcpc (operands[0], operands[1],
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operands[2]));
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else
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emit_insn (gen_aarch64_atomic_load<mode> (operands[0], operands[1],
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operands[2]));
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DONE;
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}
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)
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(define_insn "aarch64_atomic_load<mode>_rcpc"
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[(set (match_operand:ALLI 0 "register_operand" "=r")
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(unspec_volatile:ALLI
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[(match_operand:ALLI 1 "aarch64_sync_memory_operand" "Q")
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(match_operand:SI 2 "const_int_operand")] ;; model
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UNSPECV_LDAP))]
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"TARGET_RCPC"
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"ldapr<atomic_sfx>\t%<w>0, %1"
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)
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(define_insn "aarch64_atomic_load<mode>"
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[(set (match_operand:ALLI 0 "register_operand" "=r")
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(unspec_volatile:ALLI
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[(match_operand:ALLI 1 "aarch64_sync_memory_operand" "Q")
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@ -988,6 +988,7 @@
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UNSPECV_LX ; Represent a load-exclusive.
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UNSPECV_SX ; Represent a store-exclusive.
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UNSPECV_LDA ; Represent an atomic load or load-acquire.
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UNSPECV_LDAP ; Represent an atomic acquire load with RCpc semantics.
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UNSPECV_STL ; Represent an atomic store or store-release.
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UNSPECV_ATOMIC_CMPSW ; Represent an atomic compare swap.
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UNSPECV_ATOMIC_EXCHG ; Represent an atomic exchange.
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@ -20147,9 +20147,9 @@ Enable FP16 fmla extension. This also enables FP16 extensions and
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floating-point instructions. This option is enabled by default for @option{-march=armv8.4-a}. Use of this option with architectures prior to Armv8.2-A is not supported.
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@item rcpc
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Enable the RcPc extension. This does not change code generation from GCC,
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but is passed on to the assembler, enabling inline asm statements to use
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instructions from the RcPc extension.
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Enable the RCpc extension. This enables the use of the LDAPR instructions for
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load-acquire atomic semantics, and passes it on to the assembler, enabling
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inline asm statements to use instructions from the RCpc extension.
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@item dotprod
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Enable the Dot Product extension. This also enables Advanced SIMD instructions.
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@item aes
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34
gcc/testsuite/gcc.target/aarch64/ldapr.c
Normal file
34
gcc/testsuite/gcc.target/aarch64/ldapr.c
Normal file
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@ -0,0 +1,34 @@
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/* { dg-do compile } */
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/* { dg-options "-O1 -std=c99" } */
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#include <stdatomic.h>
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#pragma GCC target "+rcpc"
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atomic_ullong u64;
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atomic_llong s64;
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atomic_uint u32;
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atomic_int s32;
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atomic_ushort u16;
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atomic_short s16;
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atomic_uchar u8;
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atomic_schar s8;
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#define TEST(size, rettype) \
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rettype \
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test_##size (void) \
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{ \
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return atomic_load_explicit (&size, memory_order_acquire); \
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} \
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TEST(u64, unsigned long long)
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TEST(s64, long long)
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TEST(u32, unsigned int)
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TEST(s32, int)
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TEST(u16, unsigned short)
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TEST(s16, short)
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TEST(u8, unsigned char)
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TEST(s8, signed char)
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/* { dg-final { scan-assembler-times "ldapr\tx" 2 } } */
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/* { dg-final { scan-assembler-times "ldapr\tw" 2 } } */
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/* { dg-final { scan-assembler-times "ldaprh\tw" 2 } } */
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/* { dg-final { scan-assembler-times "ldaprb\tw" 2 } } */
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