binutils-gdb/sim/example-synacor
Mike Frysinger f9a4d54332 sim: overhaul & unify endian settings management
The m4 macro has 2 args: the "wire" settings (which represents the
hardwired port behavior), and the default settings (which are used
if nothing else is specified).  If none are specified, the arch is
expected to support both, and the value will be probed based on the
user runtime options or the input program.

Only two arches today set the default value (bpf & mips).  We can
probably let this go as it only shows up in one scenario: the sim
is invoked, but with no inputs, and no user endian selection.  This
means bpf will not behave like the other arches: an error is shown
and forces the user to make a choice.  If an input program is used
though, we'll still switch the default to that.  This allows us to
remove the WITH_DEFAULT_TARGET_BYTE_ORDER setting.

For the ports that set a "wire" endian, move it to the runtime init
of the respective sim_open calls.  This allows us to change the
WITH_TARGET_BYTE_ORDER to purely a user-selected configure setting
if they want to force a specific endianness.

With all the endian logic moved to runtime selection, we can move
the configure call up to the common dir so we only process it once
across all ports.

The ppc arch was picking the wire endian based on the target used,
but since we weren't doing that for other biendian arches, we can
let this go too.  We'll rely on the input selecting the endian, or
make the user decide.
2021-06-17 23:20:13 -04:00
..
aclocal.m4 sim: overhaul & unify endian settings management 2021-06-17 23:20:13 -04:00
ChangeLog sim: overhaul & unify endian settings management 2021-06-17 23:20:13 -04:00
configure sim: overhaul & unify endian settings management 2021-06-17 23:20:13 -04:00
configure.ac sim: overhaul & unify endian settings management 2021-06-17 23:20:13 -04:00
interp.c sim: overhaul & unify endian settings management 2021-06-17 23:20:13 -04:00
Makefile.in
README
README.arch-spec
sim-main.c sim: switch config.h usage to defs.h 2021-05-16 22:38:41 -04:00
sim-main.h sim: fully merge sim_state_base into sim_state 2021-05-17 01:05:08 -04:00

= OVERVIEW =

The Synacor Challenge is a fun programming exercise with a number of puzzles
built into it.  You can find more details about it here:
https://challenge.synacor.com/

The first puzzle is writing an interpreter for their custom ISA.  This is a
simulator for that custom CPU.  The CPU is quite basic: it's 16-bit with only
8 registers and a limited set of instructions.  This means the port will never
grow new features.  See README.arch-spec for more details.

Implementing it here ends up being quite useful: it acts as a simple constrained
"real world" example for people who want to implement a new simulator for their
own architecture.  We demonstrate all the basic fundamentals (registers, memory,
branches, and tracing) that all ports should have.