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binutils-gdb/sim
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Mike Frysinger cfc6061bd8 sim: nrun: tweak init of callback endian 
Allow ports to initialize the callback endian if they want.  This will
allow delegation of the logic out of common code in the future.

Also switch from the CURRENT_TARGET_BYTE_ORDER macro to the underlying
current_target_byte_order storage since the latter has been setup by
the sim-config module based on the same macros.  This will allow the
nrun module to be moved to common building for sharing.
2021-06-09 18:24:59 -04:00
..
aarch64 sim: fully merge sim_state_base into sim_state 2021-05-17 01:05:08 -04:00
arm sim: fully merge sim_state_base into sim_state 2021-05-17 01:05:08 -04:00
avr sim: fully merge sim_state_base into sim_state 2021-05-17 01:05:08 -04:00
bfin sim: bfin: fix the otp fix fix 2021-05-28 23:31:24 -04:00
bpf sim: bpf: use CURRENT_TARGET_BYTE_ORDER 2021-06-09 18:23:48 -04:00
common sim: nrun: tweak init of callback endian 2021-06-09 18:24:59 -04:00
cr16 sim: fully merge sim_state_base into sim_state 2021-05-17 01:05:08 -04:00
cris sim: cgen: inline cgen_init logic 2021-06-09 18:21:28 -04:00
d10v sim/d10v: Use offsetof in a static assertion about structure layout. 2021-05-21 17:27:05 -07:00
erc32 sim: switch config.h usage to defs.h 2021-05-16 22:38:41 -04:00
example-synacor sim: fully merge sim_state_base into sim_state 2021-05-17 01:05:08 -04:00
frv sim: cgen: inline cgen_init logic 2021-06-09 18:21:28 -04:00
ft32 sim: fully merge sim_state_base into sim_state 2021-05-17 01:05:08 -04:00
h8300 sim: h8300 Fixed different behavior in preinc/predec. 2021-05-28 21:14:24 +09:00
igen sim: common: start dedicated local.mk 2021-06-05 10:09:27 -04:00
iq2000 sim: cgen: inline cgen_init logic 2021-06-09 18:21:28 -04:00
lm32 sim: cgen: inline cgen_init logic 2021-06-09 18:21:28 -04:00
m4 sim: riscv: move __int128 check to configure 2021-05-16 00:04:17 -04:00
m32c sim m32c: Include defs.h in m32c.opc and r8c.opc. 2021-06-02 08:48:09 -07:00
m32r sim: cgen: inline cgen_init logic 2021-06-09 18:21:28 -04:00
m68hc11 sim: fully merge sim_state_base into sim_state 2021-05-17 01:05:08 -04:00
mcore sim: fully merge sim_state_base into sim_state 2021-05-17 01:05:08 -04:00
microblaze sim: fully merge sim_state_base into sim_state 2021-05-17 01:05:08 -04:00
mips sim: igen: harmonize tool variables 2021-06-08 00:57:58 -04:00
mn10300 sim: igen: harmonize tool variables 2021-06-08 00:57:58 -04:00
moxie sim: fully merge sim_state_base into sim_state 2021-05-17 01:05:08 -04:00
msp430 sim: fully merge sim_state_base into sim_state 2021-05-17 01:05:08 -04:00
or1k sim: cgen: inline cgen_init logic 2021-06-09 18:21:28 -04:00
ppc sim: ppc: enable -Wno-format for mingw targets 2021-05-29 18:09:02 -04:00
pru sim: fully merge sim_state_base into sim_state 2021-05-17 01:05:08 -04:00
riscv sim: fully merge sim_state_base into sim_state 2021-05-17 01:05:08 -04:00
rl78 sim: rl78: rename open symbol to avoid collisions 2021-05-23 17:40:32 -04:00
rx sim: switch config.h usage to defs.h 2021-05-16 22:38:41 -04:00
sh sim: sh: fix a few compiler warnings 2021-05-29 13:06:26 -04:00
testsuite sim: h8300 add special case test. 2021-05-28 21:14:24 +09:00
v850 sim: igen: harmonize tool variables 2021-06-08 00:57:58 -04:00
.gitignore sim: drop common/cconfig.h in favor of a single config.h 2016-01-09 03:52:30 -05:00
aclocal.m4 sim: unify toolchain settings 2021-04-02 23:31:14 -04:00
ChangeLog sim: common: start dedicated local.mk 2021-06-05 10:09:27 -04:00
configure sim: add support for build-time ar & ranlib 2021-05-04 08:22:07 -04:00
configure.ac sim: example-synacor: a simple implementation for reference 2021-04-03 16:19:16 -04:00
MAINTAINERS sim: readd myself as a maintainer 2021-01-29 22:11:45 -05:00
Makefile.am sim: common: start dedicated local.mk 2021-06-05 10:09:27 -04:00
Makefile.in sim: common: start dedicated local.mk 2021-06-05 10:09:27 -04:00
README-HACKING sim: create header namespace 2021-05-14 00:41:05 -04:00