19f6a43c6c
This updates the sim so that it unconditionally uses sys/time.h. This is in agreement with existing code, and a recent change to BFD. I also think that sys/times.h is never needed by the sim, so this patch removes the check and the one spot that was conditionally including it. sim/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * m4/sim_ac_common.m4 (SIM_AC_COMMON): Don't check for sys/time.h or sys/times.h. sim/aarch64/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure, config.in: Rebuild. sim/arm/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure, config.in: Rebuild. sim/avr/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure, config.in: Rebuild. sim/bfin/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure, config.in: Rebuild. sim/bpf/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure, config.in: Rebuild. sim/common/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * sim-utils.c: Update includes. sim/cr16/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * simops.c: Update includes. * configure, config.in: Rebuild. sim/cris/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * rvdummy.c: Update includes. * dv-rv.c: Update includes. * configure, config.in: Rebuild. sim/d10v/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure, config.in: Rebuild. sim/erc32/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure, config.in: Rebuild. sim/example-synacor/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure, config.in: Rebuild. sim/frv/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure, config.in: Rebuild. sim/ft32/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure, config.in: Rebuild. sim/h8300/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure, config.in: Rebuild. sim/iq2000/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure, config.in: Rebuild. sim/lm32/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure, config.in: Rebuild. sim/m32c/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure, config.in: Rebuild. sim/m32r/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure, config.in: Rebuild. sim/m68hc11/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure, config.in: Rebuild. sim/mcore/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure, config.in: Rebuild. sim/microblaze/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure, config.in: Rebuild. sim/mips/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure, config.in: Rebuild. sim/mn10300/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure, config.in: Rebuild. sim/moxie/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure, config.in: Rebuild. sim/msp430/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure, config.in: Rebuild. sim/or1k/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure, config.in: Rebuild. sim/ppc/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * mon.c: Update includes. * emul_unix.c: Update includes. (do_unix_gettimeofday): Update condition. sim/pru/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure, config.in: Rebuild. sim/riscv/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure, config.in: Rebuild. sim/rl78/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure, config.in: Rebuild. sim/rx/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure, config.in: Rebuild. sim/sh/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * interp.c: Update includes. * configure, config.in: Rebuild. sim/v850/ChangeLog 2021-04-22 Tom Tromey <tom@tromey.com> * configure, config.in: Rebuild. |
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| .. | ||
| aclocal.m4 | ||
| ChangeLog | ||
| config.in | ||
| configure | ||
| configure.ac | ||
| interp.c | ||
| Makefile.in | ||
| README | ||
| README.arch-spec | ||
| sim-main.c | ||
| sim-main.h | ||
= OVERVIEW = The Synacor Challenge is a fun programming exercise with a number of puzzles built into it. You can find more details about it here: https://challenge.synacor.com/ The first puzzle is writing an interpreter for their custom ISA. This is a simulator for that custom CPU. The CPU is quite basic: it's 16-bit with only 8 registers and a limited set of instructions. This means the port will never grow new features. See README.arch-spec for more details. Implementing it here ends up being quite useful: it acts as a simple constrained "real world" example for people who want to implement a new simulator for their own architecture. We demonstrate all the basic fundamentals (registers, memory, branches, and tracing) that all ports should have.