binutils-gdb/sim
Jeff Law 76c51bed59 Improve performance of the H8 simulator
Running the H8 port through the GCC testsuite currently takes 4h 30m on my
fastest server -- that's roughly 1.5hrs per multilib tested and many tests are
disabled for various reasons.

To put that 1.5hr/multilib in perspective, that's roughly 3X the time for other
embedded targets.  Clearly something isn't working as well as it should.

A bit of digging with perf shows that we're spending a crazy amount of time
decoding instructions in the H8 simulator.  It's not hard to see why --
basically we take a blob of instruction data, then try to match it to every
instruction in the H8 opcode table starting at the beginning.  That table has
~8000 entries (each different addressing mode is considered a different
instruction in the table).

Naturally my first thought was to sort the table and use a binary search to
find the right entry.  That's made excessively complex due to the encoding on
the H8.  Just getting the sort right would be much more complex than I'd
consider advisable.

Another thought was to build a mapping to the right entry for all the
instructions that can be disambiguated based on the first nibble (4 bits) of
instruction data and a mapping for those which can be disambiguated based on
the first byte of instruction data.

That seemed feasible until I realized that the H8/SX did some truly horrid
things with encoding branches in the 0x4XYY opcode space.  It uses an "always
zero" bit in the offset to encode new semantic information.  So we can't select
on just 0x4X.  Ugh!

We could always to a custom decoder.  I've done several through the years, they
can be very fast.  But no way I can justify the time to do that.

So what I settled on was to first sort the opcode table by the first nibble,
then find the index of the first instruction for each nibble. Decoding uses
that index to start its search.  This cuts the overall build/test by more than
half.

Next I adjusted the sort so that instructions that are not available on the
current sub architecture are put at the end of the table.   This shaves another
~15% off the total cycle time.

The net of the two changes is on my fastest server we've gone from 4:30 to 1:40
running the GCC testsuite.  Same test results before/after, of course.  It's
still not fast, but it's a hell of a lot better.
2023-12-10 13:26:03 -07:00
..
aarch64 sim: aarch64: fix -Wunused-but-set-variable warnings 2023-12-07 22:31:21 -07:00
arm sim: arm: fix -Wunused-but-set-variable warnings 2023-12-07 21:41:27 -07:00
avr sim: modules.c: fix generation after recent refactors 2023-01-15 20:55:48 -05:00
bfin sim: bfin: fix -Wunused-but-set-variable warnings 2023-12-07 21:41:27 -07:00
bpf sim: bpf: remove negi, neg32i insns 2023-08-21 10:07:25 -07:00
common sim: common: fix -Wunused-but-set-variable warnings 2023-12-07 22:31:21 -07:00
cr16 sim: formally assume unistd.h always exists (via gnulib) 2023-01-16 04:35:48 -05:00
cris sim: cris: fix -Wunused-but-set-variable warnings 2023-12-07 21:41:27 -07:00
d10v sim: d10v: fix -Wunused-but-set-variable warnings 2023-12-07 21:41:27 -07:00
erc32 sim: erc32: fix -Wunused-but-set-variable warnings 2023-12-07 21:41:27 -07:00
example-synacor sim: modules.c: fix generation after recent refactors 2023-01-15 20:55:48 -05:00
frv sim: frv: fix -Wunused-but-set-variable warnings 2023-12-07 21:41:27 -07:00
ft32 sim: ft32: fix -Wunused-but-set-variable warnings 2023-12-07 21:41:27 -07:00
h8300 Improve performance of the H8 simulator 2023-12-10 13:26:03 -07:00
igen sim: igen: simplify build logic a little 2023-01-15 02:07:43 -05:00
iq2000 sim regen 2023-08-19 12:41:32 +09:30
lm32 sim regen 2023-08-19 12:41:32 +09:30
m4 sim: warnings: disable -Wenum-conversion fow now [PR sim/29752] 2023-12-07 06:00:25 -07:00
m32c sim: m32c: use UTF-8 encoding 2023-12-05 07:50:56 -05:00
m32r sim: m32r: fix syslog call 2023-12-07 21:41:27 -07:00
m68hc11 sim: m68hc11: fix -Wunused-but-set-variable warnings 2023-12-07 21:41:27 -07:00
mcore sim: mcore: fix -Wunused-but-set-variable warnings 2023-12-07 21:41:27 -07:00
microblaze sim: info: convert verbose field to a bool 2023-01-18 20:47:55 -05:00
mips sim: mips: fix -Wunused-but-set-variable warnings 2023-12-07 21:41:27 -07:00
mn10300 sim: mn10300: fix sim_engine_halt call 2023-12-05 07:56:52 -05:00
moxie sim: modules.c: fix generation after recent refactors 2023-01-15 20:55:48 -05:00
msp430 sim: msp430: fix -Wunused-but-set-variable warnings 2023-12-07 22:31:21 -07:00
or1k sim regen 2023-08-19 12:41:32 +09:30
ppc sim: ppc: fix -Wunused-but-set-variable warnings 2023-12-07 22:31:21 -07:00
pru sim: modules.c: fix generation after recent refactors 2023-01-15 20:55:48 -05:00
riscv sim/riscv: fix JALR instruction simulation 2023-10-18 17:55:31 +01:00
rl78 Rename bfd_bread and bfd_bwrite 2023-08-09 08:48:09 +09:30
rx sim: rx: mark unused static var as unused 2023-12-04 23:49:48 -05:00
sh sim: sh: fix -Wunused-but-set-variable warnings 2023-12-07 22:31:21 -07:00
testsuite Fix right shifts in mcore simulator on 64 bit hosts. 2023-12-01 07:19:50 -07:00
v850 sim: v850: fix -Wunused-but-set-variable warnings 2023-12-07 22:31:21 -07:00
.gitignore sim: drop unused gentmap & nltvals.def logic 2021-11-28 13:24:00 -05:00
aclocal.m4 sim: smp: make option available again 2022-12-25 02:13:30 -05:00
arch-subdir.mk.in sim: build: drop support for creating libsim.a in subdirs 2023-01-10 01:15:26 -05:00
ChangeLog-2021
config.h.in sim: build: stop probing system extensions (ourselves) 2023-01-16 04:22:10 -05:00
configure sim: warnings: disable -Wenum-conversion fow now [PR sim/29752] 2023-12-07 06:00:25 -07:00
configure.ac sim: warnings: enable only for development builds 2023-12-04 23:45:27 -05:00
COPYING
gdbinit.in sim: gdbinit: hoist setup to common code 2022-02-21 13:57:33 -05:00
MAINTAINERS sim: Update mailing list address 2022-09-01 10:15:09 -04:00
Makefile.am sim: warnings: enable only for development builds 2023-12-04 23:45:27 -05:00
Makefile.in sim: cris: fix -Wunused-but-set-variable warnings 2023-12-07 21:41:27 -07:00
README-HACKING sim: build: delete Make-common.in logic 2023-01-13 17:34:53 -05:00