According the rvv spec,
https://github.com/riscv/riscv-v-spec/blob/master/vtype-format.adoc
The bits of vtype immediate from 8 to (xlen - 1) should be reserved.
Therefore, we should also dump the vtype immediate as numbers, when
they are set over 8-bits. I think this is a bug that we used to support
vediv extension and use the bit 8 and 9 of vtype, but forgot to update
the behavior when removing the vediv.
Consider the testcases,
vsetvli a0, a1, 0x700 # the reserved bit 10, 9 and 8 are used.
vsetvli a0, a1, 0x400 # the reserved bit 10 is used.
vsetvli a0, a1, 0x300 # the reserved bit 9 and 8 are used.
vsetvli a0, a1, 0x100 # the reserved bit 8 is used.
vsetivli a0, 0xb, 0x300 # the reserved bit 9 and 8 are used.
vsetivli a0, 0xb, 0x100 # the reserved bit 8 is used.
The original objdump shows the following result,
0000000000000000 <.text>:
0: 7005f557 vsetvli a0,a1,1792
4: 4005f557 vsetvli a0,a1,1024
8: 3005f557 vsetvli a0,a1,e8,m1,tu,mu
c: 1005f557 vsetvli a0,a1,e8,m1,tu,mu
10: f005f557 vsetivli a0,11,e8,m1,tu,mu
14: d005f557 vsetivli a0,11,e8,m1,tu,mu
But in fact the correct result should be,
0000000000000000 <.text>:
0: 7005f557 vsetvli a0,a1,1792
4: 4005f557 vsetvli a0,a1,1024
8: 3005f557 vsetvli a0,a1,768
c: 1005f557 vsetvli a0,a1,256
10: f005f557 vsetivli a0,11,768
14: d005f557 vsetivli a0,11,256
gas/
* testsuite/gas/riscv/vector-insns.d: Added testcases to
test the reserved bit 8 to (xlen-1) of vtype.
* testsuite/gas/riscv/vector-insns.s: Likewise.
include/
* opcode/riscv.h: Removed OP_MASK_VTYPE_RES and OP_SH_VTYPE_RES,
since they are different for operand Vc and Vb.
opcodes/
* riscv-dis.c (print_insn_args): Updated imm_vtype_res to
extract the reserved immediate of vtype correctly.
abfdb09f01