binutils-gdb/include
Richard Sandiford 98907a7049 [AArch64][SVE 26/32] Add SVE MUL VL addressing modes
This patch adds support for addresses of the form:

       [<base>, #<offset>, MUL VL]

This involves adding a new AARCH64_MOD_MUL_VL modifier, which is
why I split it out from the other addressing modes.

For LD2, LD3 and LD4, the offset must be a multiple of the structure
size, so for LD3 the possible values are 0, 3, 6, ....  The patch
therefore extends value_aligned_p to handle non-power-of-2 alignments.

include/
	* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4xVL): New aarch64_opnd.
	(AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, AARCH64_OPND_SVE_ADDR_RI_S4x3xVL)
	(AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, AARCH64_OPND_SVE_ADDR_RI_S6xVL)
	(AARCH64_OPND_SVE_ADDR_RI_S9xVL): Likewise.
	(AARCH64_MOD_MUL_VL): New aarch64_modifier_kind.

opcodes/
	* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
	operands.
	* aarch64-opc.c (aarch64_operand_modifiers): Initialize
	the AARCH64_MOD_MUL_VL entry.
	(value_aligned_p): Cope with non-power-of-two alignments.
	(operand_general_constraint_met_p): Handle the new MUL VL addresses.
	(print_immediate_offset_address): Likewise.
	(aarch64_print_operand): Likewise.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
	(ins_sve_addr_ri_s9xvl): New inserters.
	* aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
	(aarch64_ins_sve_addr_ri_s6xvl): Likewise.
	(aarch64_ins_sve_addr_ri_s9xvl): Likewise.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
	(ext_sve_addr_ri_s9xvl): New extractors.
	* aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
	(aarch64_ext_sve_addr_ri_s4xvl): Likewise.
	(aarch64_ext_sve_addr_ri_s6xvl): Likewise.
	(aarch64_ext_sve_addr_ri_s9xvl): Likewise.
	* aarch64-dis-2.c: Regenerate.

gas/
	* config/tc-aarch64.c (SHIFTED_NONE, SHIFTED_MUL_VL): New
	parse_shift_modes.
	(parse_shift): Handle SHIFTED_MUL_VL.
	(parse_address_main): Add an imm_shift_mode parameter.
	(parse_address, parse_sve_address): Update accordingly.
	(parse_operands): Handle MUL VL addressing modes.
2016-09-21 16:56:15 +01:00
..
aout Copyright update for binutils 2016-01-01 23:00:01 +10:30
cgen Copyright update for binutils 2016-01-01 23:00:01 +10:30
coff sparc-coff writing uninitialized memory 2016-06-11 17:25:35 +09:30
elf Fixes to legacy ARC relocations. 2016-08-26 12:09:17 +02:00
gdb Pass SIGLIBRT directly to child processes. 2016-07-15 06:35:37 -07:00
mach-o Copyright update for binutils 2016-01-01 23:00:01 +10:30
nlm Copyright update for binutils 2016-01-01 23:00:01 +10:30
opcode [AArch64][SVE 26/32] Add SVE MUL VL addressing modes 2016-09-21 16:56:15 +01:00
som Copyright update for binutils 2016-01-01 23:00:01 +10:30
vms Copyright update for binutils 2016-01-01 23:00:01 +10:30
alloca-conf.h Copyright update for binutils 2016-01-01 23:00:01 +10:30
ansidecl.h Copyright update for binutils 2016-01-01 23:00:01 +10:30
bfdlink.h Add support for creating ELF import libraries 2016-07-15 17:50:48 +01:00
binary-io.h Copyright update for binutils 2016-01-01 23:00:01 +10:30
bout.h Copyright update for binutils 2016-01-01 23:00:01 +10:30
ChangeLog [AArch64][SVE 26/32] Add SVE MUL VL addressing modes 2016-09-21 16:56:15 +01:00
ChangeLog-0415 binutils ChangeLog rotation 2016-01-01 22:59:17 +10:30
ChangeLog-9103 Add copyright notices 2012-12-10 12:48:03 +00:00
COPYING
COPYING3 * COPYING3: New file. Contains version 3 of the GNU General Public License. 2007-07-17 13:50:23 +00:00
demangle.h Copyright update for binutils 2016-01-01 23:00:01 +10:30
dis-asm.h Add support to the ARC disassembler for selecting instruction classes. 2016-07-20 17:08:07 +01:00
dwarf2.def Copyright update for binutils 2016-01-01 23:00:01 +10:30
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plugin-api.h Add new plugin hooks to support querying section alignment and size. 2016-03-03 12:09:06 -08:00
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