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Tsukasa OI c6422d7be7 sim/riscv: fix multiply instructions on simulator 
After this commit:

  commit 0938b032da
  Date:   Wed Feb 2 10:06:15 2022 +0900

      RISC-V: Add 'Zmmul' extension in assembler.

some instructions in the RISC-V simulator stopped working as a new
instruction class 'INSN_CLASS_ZMMUL' was added, and some existing
instructions were moved into this class.

The simulator doesn't currently handle this instruction class, and so
the instructions will now cause an illegal instruction trap.

This commit adds support for INSN_CLASS_ZMMUL, and adds a test that
ensures the affected instructions can be executed by the simulator.

Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Andrew Burgess <aburgess@redhat.com>
2022-10-11 12:38:36 +01:00
..
aarch64 sim: testsuite: cleanup the istarget * logic 2022-02-16 00:36:47 -05:00
arm sim: testsuite: cleanup the istarget * logic 2022-02-16 00:36:47 -05:00
avr sim: testsuite: cleanup the istarget * logic 2022-02-16 00:36:47 -05:00
bfin sim: testsuite: cleanup the istarget * logic 2022-02-16 00:36:47 -05:00
bpf sim: testsuite: cleanup the istarget * logic 2022-02-16 00:36:47 -05:00
common sim: testsuite: migrate to standard uintXX_t types 2022-01-06 01:17:38 -05:00
config sim: testsuite: rework sim_init usage 2021-11-26 19:48:05 -05:00
cr16 sim: testsuite: cleanup the istarget * logic 2022-02-16 00:36:47 -05:00
cris sim/testsuite/cris/c/stat3.c: Fix formatting nit 2022-02-16 07:38:38 +01:00
d10v sim: testsuite: cleanup the istarget * logic 2022-02-16 00:36:47 -05:00
example-synacor sim: testsuite: cleanup the istarget * logic 2022-02-16 00:36:47 -05:00
frv sim: testsuite: cleanup the istarget * logic 2022-02-16 00:36:47 -05:00
ft32 sim: testsuite: cleanup the istarget * logic 2022-02-16 00:36:47 -05:00
h8300 sim: testsuite: cleanup the istarget * logic 2022-02-16 00:36:47 -05:00
iq2000 sim: testsuite: cleanup the istarget * logic 2022-02-16 00:36:47 -05:00
lib sim/testsuite: Default global_cc_os and global_cc_works properly 2022-02-15 23:35:23 +01:00
lm32 sim: testsuite: cleanup the istarget * logic 2022-02-16 00:36:47 -05:00
m32c sim: testsuite: cleanup the istarget * logic 2022-02-16 00:36:47 -05:00
m32r sim: testsuite: cleanup the istarget * logic 2022-02-16 00:36:47 -05:00
m68hc11 sim: testsuite: cleanup the istarget * logic 2022-02-16 00:36:47 -05:00
mcore sim: testsuite: cleanup the istarget * logic 2022-02-16 00:36:47 -05:00
microblaze sim: testsuite: cleanup the istarget * logic 2022-02-16 00:36:47 -05:00
mips sim: mips: Add simulator support for mips32r6/mips64r6 2022-02-04 19:37:26 -05:00
mn10300 sim: testsuite: cleanup the istarget * logic 2022-02-16 00:36:47 -05:00
moxie sim: testsuite: cleanup the istarget * logic 2022-02-16 00:36:47 -05:00
msp430 sim: testsuite: cleanup the istarget * logic 2022-02-16 00:36:47 -05:00
or1k sim: testsuite: cleanup the istarget * logic 2022-02-16 00:36:47 -05:00
pru sim: testsuite: cleanup the istarget * logic 2022-02-16 00:36:47 -05:00
riscv sim/riscv: fix multiply instructions on simulator 2022-10-11 12:38:36 +01:00
sh sim: testsuite: cleanup the istarget * logic 2022-02-16 00:36:47 -05:00
v850 Fix for v850e divq instruction 2022-04-06 11:10:40 -04:00
.gitignore
ChangeLog-2021 sim: rename ChangeLog files to ChangeLog-2021 2021-08-17 20:27:36 -04:00
local.mk Automatic Copyright Year update after running gdb/copyright.py 2022-01-01 19:13:23 +04:00