383861bd08
Currently all ports have to declare sim_state themselves in their sim-main.h and then embed the common sim_state_base & sim_cpu in it. This dynamic makes it impossible to share common object code among multiple ports because the core data structure is always different. Let's invert this relationship: common code declares sim_state, and if the port actually needs state on a per-instance basis, it can use the new arch_data field for it. Most ports don't actually use it, so they don't need to declare anything at all. This is the first in a series of changes: it adds a define to select between the old & new layouts, then converts all the ports that don't need custom state over to the new layout. |
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| .. | ||
| aclocal.m4 | ||
| ChangeLog | ||
| config.in | ||
| configure | ||
| configure.ac | ||
| interp.c | ||
| Makefile.in | ||
| README | ||
| README.arch-spec | ||
| sim-main.c | ||
| sim-main.h | ||
= OVERVIEW = The Synacor Challenge is a fun programming exercise with a number of puzzles built into it. You can find more details about it here: https://challenge.synacor.com/ The first puzzle is writing an interpreter for their custom ISA. This is a simulator for that custom CPU. The CPU is quite basic: it's 16-bit with only 8 registers and a limited set of instructions. This means the port will never grow new features. See README.arch-spec for more details. Implementing it here ends up being quite useful: it acts as a simple constrained "real world" example for people who want to implement a new simulator for their own architecture. We demonstrate all the basic fundamentals (registers, memory, branches, and tracing) that all ports should have.