6e4f085c7f
Other than the nice advantage of all sims having to declare one fewer common function, this also fixes leakage in pretty much every sim. Many were not freeing any resources, and a few were inconsistent as to the ones they did. Now we have a single module that takes care of all the logic for us. Most of the non-cgen based ones could be deleted outright. The cgen ones required adding a callback to the arch-specific cleanup func. The few that still have close callbacks are to manage their internal state. We do not convert erc32, m32c, ppc, rl78, or rx as they do not use the common sim core.
470 lines
11 KiB
C
470 lines
11 KiB
C
/* Simulator for Xilinx MicroBlaze processor
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Copyright 2009-2015 Free Software Foundation, Inc.
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This file is part of GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, see <http://www.gnu.org/licenses/>. */
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#include "config.h"
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#include <signal.h>
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#include <stdlib.h>
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#include <string.h>
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#include <unistd.h>
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#include "bfd.h"
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#include "gdb/callback.h"
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#include "libiberty.h"
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#include "gdb/remote-sim.h"
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#include "sim-main.h"
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#include "sim-options.h"
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#include "microblaze-dis.h"
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#define target_big_endian (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
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static unsigned long
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microblaze_extract_unsigned_integer (unsigned char *addr, int len)
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{
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unsigned long retval;
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unsigned char *p;
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unsigned char *startaddr = (unsigned char *)addr;
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unsigned char *endaddr = startaddr + len;
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if (len > (int) sizeof (unsigned long))
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printf ("That operation is not available on integers of more than "
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"%zu bytes.", sizeof (unsigned long));
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/* Start at the most significant end of the integer, and work towards
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the least significant. */
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retval = 0;
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if (!target_big_endian)
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{
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for (p = endaddr; p > startaddr;)
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retval = (retval << 8) | * -- p;
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}
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else
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{
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for (p = startaddr; p < endaddr;)
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retval = (retval << 8) | * p ++;
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}
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return retval;
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}
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static void
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microblaze_store_unsigned_integer (unsigned char *addr, int len,
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unsigned long val)
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{
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unsigned char *p;
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unsigned char *startaddr = (unsigned char *)addr;
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unsigned char *endaddr = startaddr + len;
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if (!target_big_endian)
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{
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for (p = startaddr; p < endaddr;)
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{
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*p++ = val & 0xff;
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val >>= 8;
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}
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}
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else
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{
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for (p = endaddr; p > startaddr;)
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{
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*--p = val & 0xff;
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val >>= 8;
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}
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}
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}
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static void
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set_initial_gprs (SIM_CPU *cpu)
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{
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int i;
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long space;
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/* Set up machine just out of reset. */
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PC = 0;
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MSR = 0;
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/* Clean out the GPRs */
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for (i = 0; i < 32; i++)
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CPU.regs[i] = 0;
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CPU.insts = 0;
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CPU.cycles = 0;
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CPU.imm_enable = 0;
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}
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static int tracing = 0;
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void
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sim_engine_run (SIM_DESC sd,
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int next_cpu_nr, /* ignore */
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int nr_cpus, /* ignore */
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int siggnal) /* ignore */
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{
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SIM_CPU *cpu = STATE_CPU (sd, 0);
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int needfetch;
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word inst;
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enum microblaze_instr op;
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int memops;
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int bonus_cycles;
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int insts;
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int w;
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int cycs;
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word WLhash;
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ubyte carry;
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int imm_unsigned;
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short ra, rb, rd;
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long immword;
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uword oldpc, newpc;
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short delay_slot_enable;
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short branch_taken;
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short num_delay_slot; /* UNUSED except as reqd parameter */
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enum microblaze_instr_type insn_type;
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memops = 0;
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bonus_cycles = 0;
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insts = 0;
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while (1)
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{
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/* Fetch the initial instructions that we'll decode. */
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inst = MEM_RD_WORD (PC & 0xFFFFFFFC);
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op = get_insn_microblaze (inst, &imm_unsigned, &insn_type,
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&num_delay_slot);
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if (op == invalid_inst)
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fprintf (stderr, "Unknown instruction 0x%04x", inst);
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if (tracing)
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fprintf (stderr, "%.4x: inst = %.4x ", PC, inst);
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rd = GET_RD;
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rb = GET_RB;
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ra = GET_RA;
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/* immword = IMM_W; */
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oldpc = PC;
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delay_slot_enable = 0;
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branch_taken = 0;
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if (op == microblaze_brk)
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sim_engine_halt (sd, NULL, NULL, NULL_CIA, sim_stopped, SIM_SIGTRAP);
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else if (inst == MICROBLAZE_HALT_INST)
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{
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insts += 1;
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bonus_cycles++;
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sim_engine_halt (sd, NULL, NULL, NULL_CIA, sim_exited, RETREG);
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}
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else
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{
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switch(op)
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{
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#define INSTRUCTION(NAME, OPCODE, TYPE, ACTION) \
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case NAME: \
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ACTION; \
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break;
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#include "microblaze.isa"
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#undef INSTRUCTION
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default:
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sim_engine_halt (sd, NULL, NULL, NULL_CIA, sim_signalled,
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SIM_SIGILL);
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fprintf (stderr, "ERROR: Unknown opcode\n");
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}
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/* Make R0 consistent */
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CPU.regs[0] = 0;
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/* Check for imm instr */
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if (op == imm)
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IMM_ENABLE = 1;
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else
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IMM_ENABLE = 0;
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/* Update cycle counts */
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insts ++;
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if (insn_type == memory_store_inst || insn_type == memory_load_inst)
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memops++;
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if (insn_type == mult_inst)
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bonus_cycles++;
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if (insn_type == barrel_shift_inst)
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bonus_cycles++;
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if (insn_type == anyware_inst)
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bonus_cycles++;
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if (insn_type == div_inst)
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bonus_cycles += 33;
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if ((insn_type == branch_inst || insn_type == return_inst)
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&& branch_taken)
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{
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/* Add an extra cycle for taken branches */
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bonus_cycles++;
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/* For branch instructions handle the instruction in the delay slot */
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if (delay_slot_enable)
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{
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newpc = PC;
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PC = oldpc + INST_SIZE;
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inst = MEM_RD_WORD (PC & 0xFFFFFFFC);
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op = get_insn_microblaze (inst, &imm_unsigned, &insn_type,
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&num_delay_slot);
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if (op == invalid_inst)
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fprintf (stderr, "Unknown instruction 0x%04x", inst);
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if (tracing)
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fprintf (stderr, "%.4x: inst = %.4x ", PC, inst);
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rd = GET_RD;
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rb = GET_RB;
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ra = GET_RA;
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/* immword = IMM_W; */
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if (op == microblaze_brk)
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{
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if (STATE_VERBOSE_P (sd))
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fprintf (stderr, "Breakpoint set in delay slot "
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"(at address 0x%x) will not be honored\n", PC);
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/* ignore the breakpoint */
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}
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else if (insn_type == branch_inst || insn_type == return_inst)
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{
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if (STATE_VERBOSE_P (sd))
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fprintf (stderr, "Cannot have branch or return instructions "
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"in delay slot (at address 0x%x)\n", PC);
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sim_engine_halt (sd, NULL, NULL, NULL_CIA, sim_signalled,
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SIM_SIGILL);
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}
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else
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{
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switch(op)
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{
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#define INSTRUCTION(NAME, OPCODE, TYPE, ACTION) \
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case NAME: \
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ACTION; \
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break;
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#include "microblaze.isa"
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#undef INSTRUCTION
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default:
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sim_engine_halt (sd, NULL, NULL, NULL_CIA,
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sim_signalled, SIM_SIGILL);
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fprintf (stderr, "ERROR: Unknown opcode at 0x%x\n", PC);
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}
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/* Update cycle counts */
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insts++;
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if (insn_type == memory_store_inst
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|| insn_type == memory_load_inst)
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memops++;
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if (insn_type == mult_inst)
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bonus_cycles++;
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if (insn_type == barrel_shift_inst)
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bonus_cycles++;
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if (insn_type == anyware_inst)
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bonus_cycles++;
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if (insn_type == div_inst)
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bonus_cycles += 33;
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}
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/* Restore the PC */
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PC = newpc;
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/* Make R0 consistent */
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CPU.regs[0] = 0;
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/* Check for imm instr */
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if (op == imm)
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IMM_ENABLE = 1;
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else
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IMM_ENABLE = 0;
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}
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else
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/* no delay slot: increment cycle count */
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bonus_cycles++;
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}
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}
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if (tracing)
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fprintf (stderr, "\n");
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if (sim_events_tick (sd))
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sim_events_process (sd);
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}
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/* Hide away the things we've cached while executing. */
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/* CPU.pc = pc; */
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CPU.insts += insts; /* instructions done ... */
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CPU.cycles += insts; /* and each takes a cycle */
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CPU.cycles += bonus_cycles; /* and extra cycles for branches */
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CPU.cycles += memops; /* and memop cycle delays */
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}
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int
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sim_store_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
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{
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SIM_CPU *cpu = STATE_CPU (sd, 0);
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if (rn < NUM_REGS + NUM_SPECIAL && rn >= 0)
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{
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if (length == 4)
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{
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/* misalignment safe */
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long ival = microblaze_extract_unsigned_integer (memory, 4);
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if (rn < NUM_REGS)
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CPU.regs[rn] = ival;
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else
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CPU.spregs[rn-NUM_REGS] = ival;
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return 4;
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}
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else
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return 0;
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}
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else
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return 0;
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}
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int
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sim_fetch_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
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{
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SIM_CPU *cpu = STATE_CPU (sd, 0);
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long ival;
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if (rn < NUM_REGS + NUM_SPECIAL && rn >= 0)
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{
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if (length == 4)
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{
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if (rn < NUM_REGS)
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ival = CPU.regs[rn];
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else
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ival = CPU.spregs[rn-NUM_REGS];
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/* misalignment-safe */
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microblaze_store_unsigned_integer (memory, 4, ival);
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return 4;
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}
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else
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return 0;
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}
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else
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return 0;
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}
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void
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sim_info (SIM_DESC sd, int verbose)
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{
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SIM_CPU *cpu = STATE_CPU (sd, 0);
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host_callback *callback = STATE_CALLBACK (sd);
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callback->printf_filtered (callback, "\n\n# instructions executed %10d\n",
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CPU.insts);
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callback->printf_filtered (callback, "# cycles %10d\n",
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(CPU.cycles) ? CPU.cycles+2 : 0);
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}
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static sim_cia
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microblaze_pc_get (sim_cpu *cpu)
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{
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return cpu->microblaze_cpu.spregs[0];
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}
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static void
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microblaze_pc_set (sim_cpu *cpu, sim_cia pc)
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{
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cpu->microblaze_cpu.spregs[0] = pc;
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}
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static void
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free_state (SIM_DESC sd)
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{
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if (STATE_MODULES (sd) != NULL)
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sim_module_uninstall (sd);
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sim_cpu_free_all (sd);
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sim_state_free (sd);
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}
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SIM_DESC
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sim_open (SIM_OPEN_KIND kind, host_callback *cb, struct bfd *abfd, char **argv)
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{
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int i;
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SIM_DESC sd = sim_state_alloc (kind, cb);
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SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
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/* The cpu data is kept in a separately allocated chunk of memory. */
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if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK)
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{
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free_state (sd);
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return 0;
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}
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if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
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{
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free_state (sd);
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return 0;
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}
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/* getopt will print the error message so we just have to exit if this fails.
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FIXME: Hmmm... in the case of gdb we need getopt to call
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print_filtered. */
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if (sim_parse_args (sd, argv) != SIM_RC_OK)
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{
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free_state (sd);
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return 0;
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}
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/* Check for/establish the a reference program image. */
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if (sim_analyze_program (sd,
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(STATE_PROG_ARGV (sd) != NULL
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? *STATE_PROG_ARGV (sd)
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: NULL), abfd) != SIM_RC_OK)
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{
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free_state (sd);
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return 0;
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}
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/* Configure/verify the target byte order and other runtime
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configuration options. */
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if (sim_config (sd) != SIM_RC_OK)
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{
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sim_module_uninstall (sd);
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return 0;
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}
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if (sim_post_argv_init (sd) != SIM_RC_OK)
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{
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/* Uninstall the modules to avoid memory leaks,
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file descriptor leaks, etc. */
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sim_module_uninstall (sd);
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return 0;
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}
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/* CPU specific initialization. */
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for (i = 0; i < MAX_NR_PROCESSORS; ++i)
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{
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SIM_CPU *cpu = STATE_CPU (sd, i);
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CPU_PC_FETCH (cpu) = microblaze_pc_get;
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CPU_PC_STORE (cpu) = microblaze_pc_set;
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set_initial_gprs (cpu);
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}
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/* Default to a 8 Mbyte (== 2^23) memory space. */
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sim_do_commandf (sd, "memory-size 0x800000");
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return sd;
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}
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SIM_RC
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sim_create_inferior (SIM_DESC sd, struct bfd *prog_bfd, char **argv, char **env)
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{
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SIM_CPU *cpu = STATE_CPU (sd, 0);
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PC = bfd_get_start_address (prog_bfd);
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return SIM_RC_OK;
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}
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