Many x86 instructions have more than one encodings. Assembler picks
the default one, usually the shortest one. Although the ".s", ".d8"
and ".d32" suffixes can be used to swap register operands or specify
displacement size, they aren't very flexible. This patch adds pseudo
prefixes, {xxx}, to control instruction encoding. The available
pseudo prefixes are {disp8}, {disp32}, {load}, {store}, {vex2}, {vex3}
and {evex}. Pseudo prefixes are preferred over the ".s", ".d8" and
".d32" suffixes, which are deprecated.
gas/
* config/tc-i386.c (_i386_insn): Add dir_encoding and
vec_encoding. Remove swap_operand and need_vrex.
(extra_symbol_chars): Add '}'.
(md_begin): Mark '}' with LEX_BEGIN_NAME. Allow '}' in
mnemonic.
(build_vex_prefix): Don't use 2-byte VEX encoding with
{vex3}. Check dir_encoding and load.
(parse_insn): Check pseudo prefixes. Set dir_encoding.
(VEX_check_operands): Likewise.
(match_template): Check dir_encoding and load.
(parse_real_register): Set vec_encoding instead of need_vrex.
(parse_register): Likewise.
* doc/c-i386.texi: Document {disp8}, {disp32}, {load}, {store},
{vex2}, {vex3} and {evex}. Remove ".s", ".d8" and ".d32"
* testsuite/gas/i386/i386.exp: Run pseudos and x86-64-pseudos.
* testsuite/gas/i386/pseudos.d: New file.
* testsuite/gas/i386/pseudos.s: Likewise.
* testsuite/gas/i386/x86-64-pseudos.d: Likewise.
* testsuite/gas/i386/x86-64-pseudos.s: Likewise.
opcodes/
* i386-gen.c (opcode_modifiers): Replace S with Load.
* i386-opc.h (S): Removed.
(Load): New.
(i386_opcode_modifier): Replace s with load.
* i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
and {evex}. Replace S with Load.
* i386-tbl.h: Regenerated.
Currently, the -maltivec and -mvsx GAS options enable *all* of the altivec
and vsx instructions respecitively that have ever been added. This is in
constract to GCC's -maltivec and -mvsx options, which only enable the oldest
(ie, first) set of altivec and vsx instructions. This patch changes GAS to
mimic GCC's behaviour with respect to -maltivec and -mvsx and it solves a
problem with trying to assemble the lxvx instruction which is different
between POWER8 and POWER9.
opcodes/
* ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
<vsx>: Do not use PPC_OPCODE_VSX3;
gas/
* testsuite/gas/ppc/altivec2.d (as): Use the -mpower8 option.
(objdump): Use the -Mpower8 option.
Assembler displays upper case hex numbers and we need to force a good
alignment to avoid matching NOPs at the end.
* testsuite/gas/i386/x86-64-mpx-inval-2.s: Force a good alignment.
* testsuite/gas/i386/x86-64-mpx-inval-2.l: Expect [0-9A-F]+.
Putting the name, comp_dir and producer strings in the .debug_str section
makes it possible to share them across CUs. This saves a small amount of
space (about ~20K on a glibc libc.so.6 build with debuginfo). And makes
it easier for tools like rpm debugedit to adjust the source paths when
generating separate debuginfo files.
gas/
* dwarf2dbg.c (out_debug_abbrev): Use DW_FORM_strp instead of
DW_FORM_string for DW_AT_name, DW_AT_comp_dir and DW_AT_producer.
(out_debug_info): Accept symbols to name, comp_dir and producer
in the .debug_str section and emit those offsets not full strings.
(out_debug_str): New function that outputs the strings for name,
comp_dir and producer in .debug_str and generates symbols to
those strings.
(out_debug_line): Create a .debug_str section if necessary and
call out_debug_str before calling out_debug_info.
* testsuite/gas/aarch64/dwarf.d: Add extra section symbol to
expected output.
Fix a commit 6afe8e98a6 ("internal error for backwards .org"),
<https://www.sourceware.org/ml/binutils/2008-06/msg00212.html>,
GAS regression that caused legitimate code to fail assembly with an
"attempt to move .org backwards" error.
For example with the `mips-linux' target we get:
$ cat org.s
.set mips16
la $2, foo
.org 0x1000
.align 2
foo:
.half 0
$ as -o org.o org.s
org.s: Assembler messages:
org.s:3: Error: attempt to move .org backwards
$
where the location pointer is obviously not moved backwards with `.org'.
The cause is positive `stretch' in relaxation due to a PC-relative ADDIU
instruction (produced from the LA macro used) getting expanded from 2 to
4 bytes as `foo' is noticed to be out of range for the short encoding.
This in turn triggers logic in `relax_segment' which concludes in the
processing of an `rs_org' frag produced that the location pointer is
moved backwards while in fact only the amount to space forward to the
location requested has shrunk, resulting in a negative growth of the
frag.
Correct the bad logic then and instead verify that the fixed part of an
`rs_org' frag has not overrun the location requested, as per the comment
already included with the error message:
/* Growth may be negative, but variable part of frag
cannot have fewer than 0 chars. That is, we can't
.org backwards. */
which accurately describes the regression scenario. Move the comment
ahead the conditional noted, for clarity.
Add generic and MIPS test cases for the `.org' pseudo-op, including the
test case discussed though not integrated with the offending commit in
particular, adjusted to work across all targets.
gas/
* write.c (relax_segment) <rs_org>: Only bail out if the fixed
part of the frag has overrun the location requested.
* testsuite/gas/all/org-1.d: New test.
* testsuite/gas/all/org-2.d: New test.
* testsuite/gas/all/org-3.d: New test.
* testsuite/gas/all/org-4.d: New test.
* testsuite/gas/all/org-5.d: New test.
* testsuite/gas/all/org-6.d: New test.
* testsuite/gas/all/org-1.l: New stderr output.
* testsuite/gas/all/org-2.l: New stderr output.
* testsuite/gas/all/org-3.l: New stderr output.
* testsuite/gas/all/org-1.s: New test source.
* testsuite/gas/all/org-2.s: New test source.
* testsuite/gas/all/org-3.s: New test source.
* testsuite/gas/all/org-4.s: New test source.
* testsuite/gas/all/org-5.s: New test source.
* testsuite/gas/all/org-6.s: New test source.
* testsuite/gas/all/gas.exp: Run the new tests.
* testsuite/gas/mips/org-1.d: New test.
* testsuite/gas/mips/org-2.d: New test.
* testsuite/gas/mips/org-3.d: New test.
* testsuite/gas/mips/org-4.d: New test.
* testsuite/gas/mips/org-5.d: New test.
* testsuite/gas/mips/org-6.d: New test.
* testsuite/gas/mips/org-7.d: New test.
* testsuite/gas/mips/org-8.d: New test.
* testsuite/gas/mips/org-9.d: New test.
* testsuite/gas/mips/org-10.d: New test.
* testsuite/gas/mips/org-11.d: New test.
* testsuite/gas/mips/org-12.d: New test.
* testsuite/gas/mips/org-1.l: New stderr output.
* testsuite/gas/mips/org-4.l: New stderr output.
* testsuite/gas/mips/org-5.l: New stderr output.
* testsuite/gas/mips/org-6.l: New stderr output.
* testsuite/gas/mips/org-10.l: New stderr output.
* testsuite/gas/mips/org-1.s: New test source.
* testsuite/gas/mips/org-2.s: New test source.
* testsuite/gas/mips/org-3.s: New test source.
* testsuite/gas/mips/org-4.s: New test source.
* testsuite/gas/mips/org-5.s: New test source.
* testsuite/gas/mips/org-6.s: New test source.
* testsuite/gas/mips/org-7.s: New test source.
* testsuite/gas/mips/org-8.s: New test source.
* testsuite/gas/mips/org-9.s: New test source.
* testsuite/gas/mips/org-10.s: New test source.
* testsuite/gas/mips/org-11.s: New test source.
* testsuite/gas/mips/org-12.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Just like REX.W affects operand size of the implicit rAX/rDX inputs to
PCMPESTR{I,M}, VEX.W does for VPCMPESTR{I,M}. Allow Q or L suffixes on
the instructions.
Similarly the disassembler needs to be adjusted to no longer require
VEX.W to be zero for the instructions to be valid, and to emit proper
suffixes.
Note, however, that this doesn't address the problem of there being no
way to control (at least) {,E}VEX.W for 32- or 16-bit code. Nor does it
address the problem of the many WIG instructions not getting properly
disassembled when VEX.W=1.
Interpret the `jalr $0, $25' instruction encoding with an R_MIPS_JALR
relocation attached as an alias to `jr $25' and convert the jump to an
equivalent branch where possible, consequently covering the MIPSr6
architecture for the purpose of this optimization too.
bfd/
* elfxx-mips.c (mips_elf_perform_relocation): Also handle the
`jalr $0, $25' instruction encoding.
gas/
* testsuite/gas/mips/jalr4.s: Add `jalr $0, $25' instructions.
* testsuite/gas/mips/jalr4.d: Adjust accordingly. Remove MIPSr6
encoding patterns.
* testsuite/gas/mips/jalr4-n64.d: Likewise.
* testsuite/gas/mips/mipsr6@jalr4.d: New test.
* testsuite/gas/mips/mipsr6@jalr4-n32.d: New test.
* testsuite/gas/mips/mipsr6@jalr4-n64.d: New test.
ld/
* testsuite/ld-mips-elf/jalr4.dd: Adjust for `jalr $0, $25'
instructions.
* testsuite/ld-mips-elf/jalr4-r6.dd: New test.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new test.
HPUX has a different .comm syntax, and anything in the first column
is a label.
gas/
* testsuite/gas/elf/strtab.s: Don't put directives on first
column or continuation with labels not in first column.
ld/
* testsuite/ld-elf/elf.exp: Xfail pr20995 tests on hppa64-hpux.
Set up HPUX defsym. Run pr14170 tests and build symbol3 objects,
defining HPUX where necessary. Define HPUX for implib tests.
* testsuite/ld-elf/comm-data4.d: Run for hpux.
* testsuite/ld-elf/endsym.d: Likewise.
* testsuite/ld-elf/linkoncerdiff.d: Likewise.
* testsuite/ld-elf/comm-data4.s: Add alternate .comm when HPUX.
* testsuite/ld-elf/comm-data5.s: Likewise.
* testsuite/ld-elf/endsym.s: Likewise.
* testsuite/ld-elf/pr14170c.s: Likewise.
* testsuite/ld-elf/symbol3.s: Likewise.
* testsuite/ld-elf/implib.s: Likewise. Don't start directives
in first column.
* testsuite/ld-elf/linkoncerdiff2.s: Don't use numeric labels.
* testsuite/ld-elf/warn3.d: Run for hpux.
* testsuite/ld-scripts/rgn-at10.d: Xfail for hpux.
* testsuite/ld-scripts/rgn-at11.d: Likewise.
* testsuite/ld-scripts/size-2.d: Remove xfail for hpux.
This patch supports some additions to the SVE architecture prior to
its public release.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4x16)
(AARCH64_OPND_SVE_IMM_ROT1, AARCH64_OPND_SVE_IMM_ROT2)
(AARCH64_OPND_SVE_Zm3_INDEX, AARCH64_OPND_SVE_Zm3_22_INDEX)
(AARCH64_OPND_SVE_Zm4_INDEX): New aarch64_opnds.
opcodes/
* aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
(OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
(OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
(OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
(OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
(OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
(OP_SVE_V_HSD): New macros.
(OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
(OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
(OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
(aarch64_opcode_table): Add new SVE instructions.
(aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
for rotation operands. Add new SVE operands.
* aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
(ins_sve_quad_index): Likewise.
(ins_imm_rotate): Split into...
(ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
* aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
(aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
functions.
(aarch64_ins_sve_addr_ri_s4): New function.
(aarch64_ins_sve_quad_index): Likewise.
(do_misc_encoding): Handle "MOV Zn.Q, Qm".
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
(ext_sve_quad_index): Likewise.
(ext_imm_rotate): Split into...
(ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
* aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
(aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
functions.
(aarch64_ext_sve_addr_ri_s4): New function.
(aarch64_ext_sve_quad_index): Likewise.
(aarch64_ext_sve_index): Allow quad indices.
(do_misc_decoding): Likewise.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
aarch64_field_kinds.
(OPD_F_OD_MASK): Widen by one bit.
(OPD_F_NO_ZR): Bump accordingly.
(get_operand_field_width): New function.
* aarch64-opc.c (fields): Add new SVE fields.
(operand_general_constraint_met_p): Handle new SVE operands.
(aarch64_print_operand): Likewise.
* aarch64-opc-2.c: Regenerate.
gas/
* doc/c-aarch64.texi: Document that sve implies fp16, simd and compnum.
* config/tc-aarch64.c (parse_vector_type_for_operand): Allow .q
to be used with SVE registers.
(parse_operands): Handle new SVE operands.
(aarch64_features): Make "sve" require F16 rather than FP. Also
require COMPNUM.
* testsuite/gas/aarch64/sve.s: Add tests for new instructions.
Include compnum tests.
* testsuite/gas/aarch64/sve.d: Update accordingly.
* testsuite/gas/aarch64/sve-invalid.s: Add tests for new instructions.
* testsuite/gas/aarch64/sve-invalid.l: Update accordingly. Also
update expected output for new FMOV and MOV alternatives.
This patch adds a named "compnum" feature for the ARMv8.3-A FCADD
and FCMLA extensions.
include/
* opcode/aarch64.h (AARCH64_FEATURE_COMPNUM): New macro.
(AARCH64_ARCH_V8_3): Include AARCH64_FEATURE_COMPNUM.
opcodes/
* aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
(aarch64_feature_compnum): ...this.
(SIMD_V8_3): Replace with...
(COMPNUM): ...this.
(CNUM_INSN): New macro.
(aarch64_opcode_table): Use it for the complex number instructions.
gas/
* doc/c-aarch64.texi: Add a "compnum" entry.
* config/tc-aarch64.c (aarch64_features): Likewise,
* testsuite/gas/aarch64/advsimd-compnum.s: New test.
* testsuite/gas/aarch64/advsimd-compnum.d: Likewise.
Opcodes F6/1 and F7/1 are aliases of F6/0 and F7/0 in all modes. This
complements commit 8b89fe14b5 ("X86: Decode opcode 0x82 as opcode 0x80
in 32-bit mode"), just that here 64-bit mode is also covered.
gas/ChangeLog:
Test cases for the architecture level aware SPARC ASI work.
* gas/testsuite/gas/sparc/sparc.exp: 2 new tests
* gas/testsuite/gas/sparc/asi-bump-warn.s: New test
* gas/testsuite/gas/sparc/asi-bump-warn.l: Likewise
* gas/testsuite/gas/sparc/asi-arch-error.s: Likewise
* gas/testsuite/gas/sparc/asi-arch-error.l: Likewise
Discard R_MIPS_JALR and R_MICROMIPS_JALR relocations associated with
jumps that cannot be converted to an equivalent branch right away in
`mips_elf_calculate_relocation' rather than letting them through to
`mips_elf_perform_relocation'. This includes cross-mode jumps which
need to flip the ISA bit or jumps to a misaligned location that cannot
be encoded with a branch, in addition to preemptible symbol references
already handled.
Cross-mode jumps are actually already rejected as the conversion is made
in `mips_elf_perform_relocation', so in this case this change only saves
some processing. Jumps to a misaligned location are however converted,
with bits causing misalignment lost, making resulting code functionally
different even if the lone effect is avoiding an address error exception
with an instruction fetch at the jump destination requested.
Add test cases suitable, also including GAS verification to confirm that
the JALR relocations explicitly requested have indeed been output in the
intermediate objects used.
bfd/
* elfxx-mips.c (mips_elf_calculate_relocation) <R_MIPS_JALR>
<R_MICROMIPS_JALR>: Discard relocation if `cross_mode_jump_p'
or misaligned.
gas/
* testsuite/gas/mips/jalr4.d: New test.
* testsuite/gas/mips/jalr4-n32.d: New test.
* testsuite/gas/mips/jalr4-n64.d: New test.
* testsuite/gas/mips/jalr4.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
ld/
* testsuite/ld-mips-elf/jalr4.dd: New test.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new test.
This adds support of new instructions to the S/390 specific parts.
The important feature of the new instruction set is the support of
single and extended precision floating point vector operations.
Note: arch12 is NOT the official name of the new CPU. It just
continues the series of archXX options supported as alternate names.
The archXX terminology refers to the edition number of the Principle
of Operations manual. The official CPU name will be added later while
keeping support of the arch12 for backwards compatibility.
No testsuite regressions.
Committed to mainline.
Bye,
-Andreas-
opcodes/ChangeLog:
2017-02-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* s390-mkopc.c (main): Accept arch12 as cpu string and vx2 as
facility.
* s390-opc.c: Add new operand description macros, new instruction
types, instruction masks, and new .insn instruction types.
* s390-opc.txt: Add new arch12 instructions.
include/ChangeLog:
2017-02-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* opcode/s390.h (enum s390_opcode_cpu_val): New value
S390_OPCODE_ARCH12.
(S390_INSTR_FLAG_VX2): New macro definition.
gas/ChangeLog:
2017-02-23 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* config/tc-s390.c (s390_parse_cpu): New entry for arch12.
* doc/as.texinfo: Document arch12 as cpu type.
* doc/c-s390.texi: Likewise.
* testsuite/gas/s390/s390.exp: Run arch12 specific tests.
* testsuite/gas/s390/zarch-arch12.d: New test.
* testsuite/gas/s390/zarch-arch12.s: New test.
* testsuite/gas/s390/zarch-z13.d: Rename some mnemonics in the
output patterns.
Fix a functional regression with the `.end' pseudo-op, introduced with
commit ecb4347ade ("Last take: approval for MIPS_STABS_ELF killing"),
<https://sourceware.org/ml/binutils/2002-06/msg00443.html>, and commit
dcd410fe15 ("GNU as 2.14 on IRIX 6: crashes with shared libs"),
<https://sourceware.org/ml/binutils/2003-07/msg00415.html>, which caused
symbol values for labels placed between the end of a function's contents
and its terminating `.end' followed by one of the alignment pseudo-ops
to be different depending on whether either `-mdebug', or `-mno-pdr', or
neither of the command-line options is in effect, be it implied or
specified.
Given debug-label-end.s as follows and the `mips-linux' target we have:
$ cat debug-label-end.s
.text
.globl foo
.globl bar
.align 4, 0
.ent foo
foo:
nop
.aent bar
bar:
.insn
.end foo
.align 4, 0
.space 16
.globl baz
.ent baz
baz:
nop
.end baz
.align 4, 0
.space 16
$ as -o debug-label-end.o debug-label-end.s
$ readelf -s debug-label-end.o | grep bar
9: 00000004 0 FUNC GLOBAL DEFAULT 1 bar
$ as -mdebug -o debug-label-end.o debug-label-end.s
$ readelf -s debug-label-end.o | grep bar
9: 00000010 0 FUNC GLOBAL DEFAULT 1 bar
$ as -mno-pdr -o debug-label-end.o debug-label-end.s
$ readelf -s debug-label-end.o | grep bar
8: 00000010 0 FUNC GLOBAL DEFAULT 1 bar
$
The reason is the call to `md_flush_pending_output', which in the case
of `mips*-*-*' targets expands to `mips_emit_delays', which in turn
calls `mips_no_prev_insn', which calls `mips_clear_insn_labels', which
clears the list of outstanding labels. That list is in turn consulted
in `mips_align', called in the interpretation of alignment directives,
and the labels adjusted to the current location.
A call to `md_flush_pending_output' is only made from `s_mips_end' and
then only if `-mpdr' is in effect, which is the default for `*-*-linux*'
and some other `mips*-*-*' targets. A call to `md_flush_pending_output'
is never made from `ecoff_directive_end', which is used in place of
`s_mips_end' when `-mdebug' is in effect. Consequently if `-mno-pdr' or
`-mdebug' is in effect the list of outstanding labels makes it through
to any alignment directive that follows and the labels are differently
interpreted depending on the command-lines options used. And we want
code produced to be always the same.
Call `md_flush_pending_output' unconditionally then in `s_mips_end' and
add such a call from `ecoff_directive_end' as well, as long as the macro
is defined. While `ecoff_directive_end' is shared among targets, the
only one other than `mips*-*-*' actually using it is `alpha*-*-*' and it
does not define `md_flush_pending_output'. So the semantics isn't going
to change for it and neither it has to have its `s_alpha_end' updated
or have code in `ecoff_directive_end' conditionalized.
gas/
* ecoff.c (ecoff_directive_end) [md_flush_pending_output]: Call
`md_flush_pending_output'.
* config/tc-mips.c (s_mips_end) [md_flush_pending_output]: Call
`md_flush_pending_output' unconditionally.
* testsuite/gas/mips/debug-label-end-1.d: New test.
* testsuite/gas/mips/debug-label-end-2.d: New test.
* testsuite/gas/mips/debug-label-end-3.d: New test.
* testsuite/gas/mips/debug-label-end.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Implement the ECOFF `.aent' pseudo-op for ECOFF-style `.mdebug' section
support with ELF objects and, for consistency, also with ECOFF objects.
This is so that the same MIPS source can be assembled without and with
`.mdebug' section generation enabled.
Taking the `gas/testsuite/gas/mips/aent.s' test case source as an
example and the `mips-linux' target we have:
$ as -o aent.o aent.s
$ as -mdebug -o aent.o aent.s
aent.s: Assembler messages:
aent.s:10: Error: unknown pseudo-op: `.aent'
$
because for the !ECOFF_DEBUGGING case (which is the default) the
pseudo-op is already handled by the MIPS backend with `s_mips_ent',
however no handler is present for the opposite case.
For the MIPS target this is a functional regression introduced with
commit ecb4347ade ("Last take: approval for MIPS_STABS_ELF killing"),
<https://sourceware.org/ml/binutils/2002-06/msg00443.html>, where
support for the `.mdebug' section was added along with its associated
`-mdebug'/`-no-mdebug' command-line options, bringing an inconsistency
between the assembly syntax supported for each of these options as far
as the `.aent' pseudo-op is concerned.
Assembly language documentation available describes the pseudo-op
respectively as follows[1]:
"
.aent name, symno Sets an alternate entry point for the current
procedure. Use this information when you want
to generate information for the debugger. It must
appear inside an .ent/.end pair."
and[2]:
"
.aent name [,symno]
Sets an alternate entry point for the current procedure. Use this
information when you want to generate information for the debugger.
This directive must appear between a pair of .ent and .end directives.
(The optional symno is for compiler use only. It refers to a dense
number in a .T file (symbol table).)"
Copy the approach from `s_mips_ent' then and add `.aent' support to the
`.ent' pseudo-op handler shared between the ELF and ECOFF object file
format backends, by setting BSF_FUNCTION for the symbol requested.
References:
[1] "MIPSpro Assembly Language Programmer's Guide", Silicon Graphics,
Inc., Document Number 007-2418-004, Section 8.1 "Op-Codes", p. 96
<http://techpubs.sgi.com/library/manuals/2000/007-2418-004/pdf/007-2418-004.pdf>
[2] "Digital UNIX Assembly Language Programmer's Guide", Digital
Equipment Corporation, Order Number: AA-PS31D-TE, March 1996,
Chapter 5 "Assembler Directives", p. 5-2
<http://h41361.www4.hpe.com/docs/base_doc/DOCUMENTATION/V40G_PDF/APS31DTE.PDF>
gas/
* ecoff.c (ecoff_directive_ent, add_procedure): Handle `.aent'.
* config/obj-ecoff.c (obj_pseudo_table): Add "aent" entry.
* config/obj-elf.c (ecoff_debug_pseudo_table): Likewise.
* testsuite/gas/mips/aent-2.d: New test.
* testsuite/gas/mips/aent-mdebug.d: New test.
* testsuite/gas/mips/aent-mdebug-2.d: New test.
* testsuite/gas/mips/mips.exp: Run the new tests.
This patch adds the SVE-specific system registers.
opcodes/
* aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
(aarch64_sys_reg_supported_p): Handle them.
gas/
* testsuite/gas/aarch64/sve-sysreg.s,
testsuite/gas/aarch64/sve-sysreg.d,
testsuite/gas/aarch64/sve-sysreg-invalid.d,
testsuite/gas/aarch64/sve-sysreg-invalid.l: New tests.
opcodes * arc-regs.h: Distinguish some of the registers different on
ARC700 and HS38 cpus.
gas * testsuite/gas/arc/st.d: Update for 0xe having a name now
PR 21118 work exposed these errors in the testsuite.
* testsuite/gas/ppc/cell.s: Correct invalid registers.
* testsuite/gas/ppc/vle-simple-1.s: Likewise.
* testsuite/gas/ppc/vle-simple-2.s: Likewise.
2017-02-13 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (parse_ifimm_zero): Make prefix optional in unified
syntax.
* testsuite/gas/arm/vcmp-noprefix-imm.d: New file.
* testsuite/gas/arm/vcmp-noprefix-imm.s: New file.
Complement commit 9d862524f6 ("MIPS: Verify the ISA mode and alignment
of branch and jump targets") and add GAS and LD options to control the
checks for invalid branches between ISA modes introduced there, to help
with some handwritten code lacking `.insn' annotation for labels used as
branch targets and code produced by older versions of GCC which suffers
from the issue with branches to code that has been optimized away,
addressed with GCC commit 242424 ("MIPS/GCC: Mark trailing labels with
`.insn'"), <https://gcc.gnu.org/ml/gcc-patches/2016-11/msg01061.html>.
bfd/
* elfxx-mips.h (_bfd_mips_elf_insn32): Rename prototype to...
(_bfd_mips_elf_linker_flags): ... this. Add another parameter.
* elfxx-mips.c (mips_elf_link_hash_table): Add
`ignore_branch_isa' member.
(mips_elf_perform_relocation): Do not treat an ISA mode mismatch
in branch relocation calculation as an error if
`ignore_branch_isa' has been set.
(_bfd_mips_elf_insn32): Rename to...
(_bfd_mips_elf_linker_flags): ... this. Rename the `on'
parameter to `insn32' and add an `ignore_branch_isa' parameter.
Handle the new parameter.
gas/
* config/tc-mips.c (mips_ignore_branch_isa): New variable.
(options): Add OPTION_IGNORE_BRANCH_ISA and
OPTION_NO_IGNORE_BRANCH_ISA enum values.
(md_longopts): Add "mignore-branch-isa" and
"mno-ignore-branch-isa" options.
(md_parse_option): Handle OPTION_IGNORE_BRANCH_ISA and
OPTION_NO_IGNORE_BRANCH_ISA.
(fix_bad_cross_mode_branch_p): Return FALSE if
`mips_ignore_branch_isa' has been set.
(md_show_usage): Add `-mignore-branch-isa' and
`-mno-ignore-branch-isa'.
* doc/as.texinfo (Target MIPS options): Add
`-mignore-branch-isa' and `-mno-ignore-branch-isa' options.
(-mignore-branch-isa, -mno-ignore-branch-isa): New options.
* doc/c-mips.texi (MIPS Options): Add `-mignore-branch-isa' and
`-mno-ignore-branch-isa' options.
* testsuite/gas/mips/branch-local-ignore-2.d: New test.
* testsuite/gas/mips/branch-local-ignore-3.d: New test.
* testsuite/gas/mips/branch-local-ignore-n32-2.d: New test.
* testsuite/gas/mips/branch-local-ignore-n32-3.d: New test.
* testsuite/gas/mips/branch-local-ignore-n64-2.d: New test.
* testsuite/gas/mips/branch-local-ignore-n64-3.d: New test.
* testsuite/gas/mips/mips.exp: Run the new tests.
ld/
* emultempl/mipself.em (ignore_branch_isa): New variable.
(mips_create_output_section_statements): Rename
`_bfd_mips_elf_insn32' called to `_bfd_mips_elf_linker_flags',
add `ignore_branch_isa' argument.
(PARSE_AND_LIST_PROLOGUE): Add OPTION_IGNORE_BRANCH_ISA and
OPTION_NO_IGNORE_BRANCH_ISA enum values.
(PARSE_AND_LIST_LONGOPTS): Add "ignore-branch-isa" and
"no-ignore-branch-isa" options.
(PARSE_AND_LIST_OPTIONS): Add `--ignore-branch-isa' and
`--no-ignore-branch-isa'.
(PARSE_AND_LIST_ARGS_CASES): Handle OPTION_IGNORE_BRANCH_ISA and
OPTION_NO_IGNORE_BRANCH_ISA.
* ld.texinfo (Options specific to MIPS targets): Add
`--ignore-branch-isa' and `--no-ignore-branch-isa' options.
(ld and the MIPS family): Likewise.
* testsuite/ld-mips-elf/bal-jalx-pic-ignore.d: New test.
* testsuite/ld-mips-elf/bal-jalx-pic-ignore-n32.d: New test.
* testsuite/ld-mips-elf/bal-jalx-pic-ignore-n64.d: New test.
* testsuite/ld-mips-elf/unaligned-branch-ignore-2.d: New test.
* testsuite/ld-mips-elf/unaligned-branch-ignore-r6-1: New test.
* testsuite/ld-mips-elf/unaligned-branch-ignore-mips16: New
test.
* testsuite/ld-mips-elf/unaligned-branch-ignore-micromips: New
test.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
gas/
* testsuite/gas/mips/branch-local-2.d: New test.
* testsuite/gas/mips/branch-local-3.d: New test.
* testsuite/gas/mips/branch-local-n32-2.d: New test.
* testsuite/gas/mips/branch-local-n32-3.d: New test.
* testsuite/gas/mips/branch-local-n64-2.d: New test.
* testsuite/gas/mips/branch-local-n64-3.d: New test.
* testsuite/gas/mips/mips.exp: Fold corresponding list tests
into the new tests.
PR 21056
opcodes * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
instructions when the previous fetch packet ends with a 32-bit
instruction.
gas * testsuite/gas/tic6x/insns16-parallel.s: New test case.
* testsuite/gas/tic6x/insns16-parallel.d: New test driver.
Correct a regression from commit 8614eeee67 ("Traditional MIPS
patches"), <https://sourceware.org/ml/binutils/2000-07/msg00018.html>,
which caused symbols in linkonce or what is these days known as comdat
sections to be treated as external for the purpose of PIC relocation
generation even if their binding remains STB_LOCAL. This in turn
disabled GOT16/LO16 relocation pairing with references to such symbols,
as no complementing LO16 relocation is expected for external GOT16
references in the o32 ABI, which ultimately leads to link errors, e.g.:
ld: comdat-reloc.o: Can't find matching LO16 reloc against `foo' for R_MIPS_GOT16 at 0x24 in section `.text.bar[bar]'
as with the LD test case included with this change.
Revert the special case for symbols in comdat sections then, making code
actually match `adjust_reloc_syms' as indicated in its explanatory
comment, and adjust calling code accordingly. Also bring back the
corresponding description of what now is `s_is_linkonce', lost with
commit 5f0fe04bc5 ("Improved MIPS16/MIPS32 code intermixing for
gas."), <https://www.sourceware.org/ml/binutils/2006-07/msg00039.html>.
gas/
PR gas/20649
* config/tc-mips.c (pic_need_relax): Don't check for linkonce
symbols, remove the `segtype' parameter.
(mips_frob_file, md_estimate_size_before_relax): Adjust
accordingly.
(s_is_linkonce): Add an explanatory comment.
* testsuite/gas/mips/comdat-reloc.d: New test.
* testsuite/gas/mips/comdat-reloc.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new test.
ld/
PR gas/20649
* testsuite/ld-mips-elf/mips-elf.exp: Add PIC comdat GOT16/LO16
relocation pairing link test.
Bit 24 of the indexed element vcmla decode mask was incorrectly
left unset. This could cause incorrect disassembly of some
currently undefined instructions as vcmla.
Rotatation immediates were not printed correctly in the disassembly
(could print 170 and 280 instead of 180 and 270).
opcodes/
* arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
gas/
* testsuite/gas/arm/armv8_3-a-simd.s: Add vcmla tests.
* testsuite/gas/arm/armv8_3-a-simd.d: Update.
gas/
* read.c (emit_leb128_expr): Extended unsigned big number for
sleb128.
* testsuite/gas/all/gas.exp (test_cond): Add sleb128-8 test.
* testsuite/gas/all/sleb128.d: New test.
* testsuite/gas/all/sleb128.s: New test source.
The weaker release consistency support of ARMv8.3-A is allowed as an optional
extension for ARMv8.2-A, so separate command line option and feature flag is
added: -march=armv8.2-a+rcpc turns LDAPR, LDAPRB, LDAPRH instructions on.
opcodes/
* aarch64-tbl.h (RCPC, RCPC_INSN): Define.
(aarch64_opcode_table): Use RCPC_INSN.
include/
* opcode/aarch64.h (AARCH64_FEATURE_RCPC): Define.
(AARCH64_ARCH_V8_3): Update.
gas/
* config/tc-aarch64.c (aarch64_features): Add rcpc.
* doc/c-aarch64.texi (AArch64 Extensions): Document rcpc.
* testsuite/gas/aarch64/ldst-exclusive-armv8_3.d: Rename to ...
* testsuite/gas/aarch64/ldst-rcpc.d: This.
* testsuite/gas/aarch64/ldst-exclusive-armv8_3.s: Rename to ...
* testsuite/gas/aarch64/ldst-rcpc.s: This.
* testsuite/gas/aarch64/ldst-rcpc-armv8_2.d: New test.
Add ASMACRO instruction support as per the MIPS16e ASE architecture
specifications [1][2], completing MIPS16e instruction set support.
[1] "MIPS32 Architecture for Programmers, Volume IV-a: The MIPS16e
Application-Specific Extension to the MIPS32 Architecture", MIPS
Technologies, Inc., Document Number: MD00076, Revision 2.63, July
16, 2013, Section 4.1 "MIPS16e Instruction Descriptions", p. 65
[2] "MIPS64 Architecture for Programmers, Volume IV-a: The MIPS16e
Application-Specific Extension to the MIPS64 Architecture", MIPS
Technologies, Inc., Document Number: MD00077, Revision 2.60, June
25, 2008, Section 1.1 "MIPS16e Instruction Descriptions", p. 66
include/
* opcode/mips.h: Document `0', `1', `2', `3', `4' and `s'
operand codes.
opcodes/
* mips16-opc.c (decode_mips16_operand): Add `0', `1', `2', `3',
`4' and `s' operand codes.
(mips16_opcodes): Add "asmacro" entry.
binutils/
* testsuite/binutils-all/mips/mips16-extend-insn.d: Update for
ASMACRO support.
gas/
* testsuite/gas/mips/mips16-asmacro.d: New test.
* testsuite/gas/mips/mips16-32@mips16-asmacro.d: New test.
* testsuite/gas/mips/mips16-64@mips16-asmacro.d: New test.
* testsuite/gas/mips/mips16-asmacro.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Bail out right away when an unextended instruction encoding is required
either with the use of a `.t' suffix or by means of `.set noautoextend',
however an operand supplied requires the extended instruction form to be
used.
This is to avoid messing up with the internal state of the assembler,
even though no actual failures are known to happen as a result. Add
test cases for the situation concerned.
gas/
* config/tc-mips.c (match_mips16_insn): Don't update
`forced_insn_length' or the instruction opcode if an operand
requires an extended instruction form, but an unextended one
has been requested.
* testsuite/gas/mips/mips16-relax-unextended-1.d: New test.
* testsuite/gas/mips/mips16-relax-unextended-2.d: New test.
* testsuite/gas/mips/mips16-relax-unextended-1.l: New stderr
output.
* testsuite/gas/mips/mips16-relax-unextended-2.l: New stderr
output.
* testsuite/gas/mips/mips16-relax-unextended-1.s: New test
source.
* testsuite/gas/mips/mips16-relax-unextended-2.s: New test
source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Identify non-extensible instructions in the MIPS16 opcode table and
disallow their use with the `.e' instruction size suffix in assembly and
do not interpret any EXTEND prefix present as a part of the instruction
in disassembly.
According to all versions of the MIPS16 ASE specifications the following
instructions encodings are not extensible [1][2][3][4][5][6]: I8/MOV32R,
I8/MOVR32, all RRR minor opcodes, all RR minor opcodes except from DSRA
and DSRL, and EXTEND itself, and as from revision 2.50 of the MIPS16e
ASE specifications it has been further clarified what was previously
implied, that non-extesiable instructions when preceded with an EXTEND
prefix must cause a Reserved Instruction exception [3][5].
Therefore in the presence of an EXTEND prefix none of these instructions
are supposed to be handled as extended instructions and supporting these
forms in disassembly causes confusion, and in the case of the RRR major
opcode it also clashes with the ASMACRO encoding.
References:
[1] "Product Description, MIPS16 Application-Specific Extension",
Version 1.3, MIPS Technologies, Inc., 970130, Table 3. "MIPS16
Instruction Set Summary", p. 5
[2] same, Table 5 "RR Minor Opcodes (RR-type instructions)", p.10
[3] "MIPS32 Architecture for Programmers, Volume IV-a: The MIPS16e
Application-Specific Extension to the MIPS32 Architecture", MIPS
Technologies, Inc., Document Number: MD00076, Revision 2.63, July
16, 2013, Section 3.9 "MIPS16e Instruction Summaries", pp. 37-39
[4] same, Section 3.15 "Instruction Bit Encoding", pp. 46-49
[5] "MIPS64 Architecture for Programmers, Volume IV-a: The MIPS16e
Application-Specific Extension to the MIPS64 Architecture", MIPS
Technologies, Inc., Document Number: MD00077, Revision 2.60, June
25, 2008, Section 1.9 "MIPS16e Instruction Summaries", pp. 38-41
[6] same, Section 1.15 "Instruction Bit Encoding", pp. 48-51
include/
* opcode/mips.h (INSN2_SHORT_ONLY): New macro.
gas/
* config/tc-mips.c (is_size_valid_16): Disallow a `.e' suffix
instruction size override for INSN2_SHORT_ONLY opcode table
entries.
* testsuite/gas/mips/mips16-extend-swap.d: Adjust output.
* testsuite/gas/mips/mips16-macro-e.l: Adjust error messages.
* testsuite/gas/mips/mips16-32@mips16-macro-e.l: Adjust error
messages.
* testsuite/gas/mips/mips16e-32@mips16-macro-e.l: Adjust error
messages.
* testsuite/gas/mips/mips16-insn-e.d: New test.
* testsuite/gas/mips/mips16-insn-t.d: New test.
* testsuite/gas/mips/mips16-32@mips16-insn-e.d: New test.
* testsuite/gas/mips/mips16-64@mips16-insn-e.d: New test.
* testsuite/gas/mips/mips16e-32@mips16-insn-e.d: New test.
* testsuite/gas/mips/mips16-32@mips16-insn-t.d: New test.
* testsuite/gas/mips/mips16-64@mips16-insn-t.d: New test.
* testsuite/gas/mips/mips16e-32@mips16-insn-t.d: New test.
* testsuite/gas/mips/mips16-insn-e.l: New stderr output.
* testsuite/gas/mips/mips16-insn-t.l: New stderr output.
* testsuite/gas/mips/mips16-32@mips16-insn-e.l: New stderr
output.
* testsuite/gas/mips/mips16-64@mips16-insn-e.l: New stderr
output.
* testsuite/gas/mips/mips16e-32@mips16-insn-e.l: New stderr
output.
* testsuite/gas/mips/mips16-32@mips16-insn-t.l: New stderr
output.
* testsuite/gas/mips/mips16-64@mips16-insn-t.l: New stderr
output.
* testsuite/gas/mips/mips16e-32@mips16-insn-t.l: New stderr
output.
* testsuite/gas/mips/mips16-insn-e.s: New test source.
* testsuite/gas/mips/mips16-insn-t.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
opcodes/
* mips-dis.c (print_insn_mips16): Disallow EXTEND prefix
matching for INSN2_SHORT_ONLY opcode table entries.
* mips16-opc.c (SH): New macro.
(mips16_opcodes): Set SH in `pinfo2' for non-extensible
instruction entries: "nop", "addu", "and", "break", "cmp",
"daddu", "ddiv", "ddivu", "div", "divu", "dmult", "dmultu",
"drem", "dremu", "dsllv", "dsll", "dsrav", "dsra", "dsrlv",
"dsrl", "dsubu", "exit", "entry", "jalr", "jal", "jr", "j",
"jalrc", "jrc", "mfhi", "mflo", "move", "mult", "multu", "neg",
"not", "or", "rem", "remu", "sllv", "sll", "slt", "sltu",
"srav", "sra", "srlv", "srl", "subu", "xor", "sdbbp", "seb",
"seh", "sew", "zeb", "zeh", "zew" and "extend".
binutils/
* testsuite/binutils-all/mips/mips16-extend-insn.d: New test.
* testsuite/binutils-all/mips/mips16-extend-insn.s: New test
source.
* testsuite/binutils-all/mips/mips.exp: Run the new tests.
Correct the handling of `.e' and `.t' instruction size suffixes with
instruction mnemonics which are not followed by any text on the same
line, such as arguments or white space, e.g.:
$ cat test.s
.set mips16
foo:
entry.t # comment
entry.t
exit.t # comment
exit.t
nop.t # comment
nop.t
$ as -32 -o test.o test.s
test.s: Assembler messages:
test.s:4: Error: unrecognized opcode `entry.t'
test.s:6: Error: unrecognized opcode `exit.t'
test.s:8: Error: unrecognized opcode `nop.t'
$
gas/
* config/tc-mips.c (mips16_ip): Handle `.e' and `.t' instruction
suffixes followed by a null character rather than a space too.
* testsuite/gas/mips/mips16-insn-length-noargs.d: New test.
* testsuite/gas/mips/mips16-insn-length-noargs.s: New test
source.
* testsuite/gas/mips/mips.exp: Run the new test.
Do not allow any explicitly coded EXTEND instruction to be automatically
scheduled into a jump delay slot, as an EXTEND prefix is coupled with
the next regular MIPS16 instruction and therefore swapping it with a
jump would change program's semantics; EXTEND is not architecturally
allowed to be present in a jump delay slot anyway.
opcodes/
* mips16-opc.c (mips16_opcodes): Set NODS in `pinfo' for
"extend".
gas/
* testsuite/gas/mips/mips16-extend-swap.d: New test.
* testsuite/gas/mips/mips16-extend-swap.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new test.
gas/
* doc/c-lm32.texi: Fix chars with high bit set.
* testsuite/gas/bfin/vector2.s: Likewise.
gold/
* arm.cc: Fix comment chars with high bit set.
include/
* coff/pe.h: Fix comment chars with high bit set.
* opcode/xgate.h: Likewise.
ld/
* testsuite/ld-scripts/sysroot-prefix.exp: Fix chars with high bit set.
Limit MIPS16 instruction disassembly according to the ISA level and ASE
set selected, as with the regular MIPS and microMIPS instruction sets.
Retain the property of `objdump -m mips:16' disassembling all MIPS16
instructions however, regardless of any ISA level recorded in the binary
examined.
To validate the disassembler use the GAS test suite for its convenience
of running tests across multiple ISAs, even though placing the tests in
the binutils test suite would be more appropriate. Adjust the single
binutils test which depends on 64-bit instruction disassembly to have
the ISA level required actually recorded in the binary examined.
opcodes/
* mips-dis.c (mips_arch_choices): Use ISA_MIPS64 rather than
ISA_MIPS3 as the `isa' selection in the `bfd_mach_mips16' entry.
(print_insn_mips16): Check opcode entries for validity against
the ISA level and ASE set selected.
binutils/
* testsuite/binutils-all/mips/mips16-undecoded.s: Use `.module'
rather than `.set' to set the ISA level.
gas/
* testsuite/gas/mips/mips16-sub.d: New test.
* testsuite/gas/mips/mips16-32@mips16-sub.d: New test.
* testsuite/gas/mips/mips16e-32@mips16-sub.d: New test.
* testsuite/gas/mips/mips16e-sub.d: New test.
* testsuite/gas/mips/mips16-32@mips16e-sub.d: New test.
* testsuite/gas/mips/mips16-64@mips16e-sub.d: New test.
* testsuite/gas/mips/mips16e-64-sub.d: New test.
* testsuite/gas/mips/mips16-32@mips16e-64-sub.d: New test.
* testsuite/gas/mips/mips16-64@mips16e-64-sub.d: New test.
* testsuite/gas/mips/mips16e-32@mips16e-64-sub.d: New test.
* testsuite/gas/mips/mips16-sub.s: New test source.
* testsuite/gas/mips/mips16e-sub.s: New test source.
* testsuite/gas/mips/mips16e-64-sub.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
Add a RESTORE instruction smoke test to the `mips16e' GAS test.
gas/
* testsuite/gas/mips/mips16e.s: Add a RESTORE instruction.
* testsuite/gas/mips/mips16e.d: Adjust accordingly.
