Commit graph

4742 commits

Author SHA1 Message Date
Jiawei
dac0b8a4af RISC-V: Support Zabha extension.
The Zabha extension[1] supports for byte and halfword
atomic memory operations. This patch add all instructions
include in Zabha. Further work is waiting Zacas[2] merge.

[1] https://github.com/riscv/riscv-zabha/tags
[2] https://sourceware.org/pipermail/binutils/2023-May/127700.html

Version log:
Add new imply relation that Zabha extension implies A extension.

bfd/ChangeLog:

        * elfxx-riscv.c (riscv_implicit_subsets): New imply.
        (riscv_multi_subset_supports): New extension.
        (riscv_multi_subset_supports_ext): Ditto.

gas/ChangeLog:

        * testsuite/gas/riscv/zabha-32.d: New test.
        * testsuite/gas/riscv/zabha.d: New test.
        * testsuite/gas/riscv/zabha.s: New test.

include/ChangeLog:

        * opcode/riscv-opc.h (MATCH_AMOADD_B): New opcodes.
        (MASK_AMOADD_B): Ditto.
        (MATCH_AMOXOR_B): Ditto.
        (MASK_AMOXOR_B): Ditto.
        (MATCH_AMOOR_B): Ditto.
        (MASK_AMOOR_B): Ditto.
        (MATCH_AMOAND_B): Ditto.
        (MASK_AMOAND_B): Ditto.
        (MATCH_AMOMIN_B): Ditto.
        (MASK_AMOMIN_B): Ditto.
        (MATCH_AMOMAX_B): Ditto.
        (MASK_AMOMAX_B): Ditto.
        (MATCH_AMOMINU_B): Ditto.
        (MASK_AMOMINU_B): Ditto.
        (MATCH_AMOMAXU_B): Ditto.
        (MASK_AMOMAXU_B): Ditto.
        (MATCH_AMOSWAP_B): Ditto.
        (MASK_AMOSWAP_B): Ditto.
        (MATCH_AMOADD_H): Ditto.
        (MASK_AMOADD_H): Ditto.
        (MATCH_AMOXOR_H): Ditto.
        (MASK_AMOXOR_H): Ditto.
        (MATCH_AMOOR_H): Ditto.
        (MASK_AMOOR_H): Ditto.
        (MATCH_AMOAND_H): Ditto.
        (MASK_AMOAND_H): Ditto.
        (MATCH_AMOMIN_H): Ditto.
        (MASK_AMOMIN_H): Ditto.
        (MATCH_AMOMAX_H): Ditto.
        (MASK_AMOMAX_H): Ditto.
        (MATCH_AMOMINU_H): Ditto.
        (MASK_AMOMINU_H): Ditto.
        (MATCH_AMOMAXU_H): Ditto.
        (MASK_AMOMAXU_H): Ditto.
        (MATCH_AMOSWAP_H): Ditto.
        (MASK_AMOSWAP_H): Ditto.
        (DECLARE_INSN): New declare.
        * opcode/riscv.h (enum riscv_insn_class): New class.

opcodes/ChangeLog:

        * riscv-opc.c: New instructions.
2024-03-08 10:04:25 +08:00
Jens Remus
75a28d1a97 s390: Print base register 0 as "0" in disassembly
Base and index register 0 have no effect in address computation:

"A value of zero in the B [base] or X [index] field specifies that no
base or index is to be applied, and, thus, general register 0 cannot be
designated as containing a base address or index."
IBM z/Architecture Principles of Operation [1], chapter "Organization",
section "General Registers".

Index register 0 is omitted in the s390 disassembly. Base register 0 is
omitted in D(B), D(L,B) and D(X,B) - the latter only if the index
register is zero.

To make it more apparent print base register 0 as "0" instead of "%r0",
whenever it would still be printed in the disassembly.

[1]: IBM z/Architecture Principles of Operation, SA22-7832-13,
     https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf

opcodes/
	* s390-dis.c: Print base register 0 as "0" in disassembly.

binutils/
	* NEWS: Mention base register 0 now being printed as "0" in s390
	disassembly.

gas/
	* testsuite/gas/s390/zarch-base-index-0.d: Update test case
	output verification patterns to accept "0" as base base
	register due to disassembler output format change.
	* gas/testsuite/gas/s390/zarch-omitted-base-index.d: Likewise.

Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01 12:45:14 +01:00
Jens Remus
dfa4ac9728 s390: Warn when register name type does not match operand
Print a warning message when the register type of a specified register
name does not match with the operand's register type:

operand {#}: expected {access|control|floating-point|general|vector}
  register name [as {base|index} register]

Introduce a s390-specific assembler option "warn-regtype-mismatch"
with the values "strict", "relaxed", and "no" as well as an option
"no-warn-regtype-mismatch" which control whether the assembler
performs register name type checks and generates above warning messages.

warn-regtype-mismatch=strict:
  Perform strict register name type checks.

warn-regtype-mismatch=relaxed:
  Perform relaxed register name type checks, which allow floating-point
  register (FPR) names %f0 to %f15 to be specified as argument to vector
  register (VR) operands and vector register (VR) names %v0 to %v15 to
  be specified as argument to floating-point register (FPR) operands.
  This is acceptable as the FPRs are embedded into the lower halves of
  the VRs. Make "relaxed" the default, as GCC generates assembler code
  using FPR and VR interchangeably, which would cause assembler warnings
  to be generated with "strict".

warn-regtype-mismatch=no:
no-warn-regtype-mismatch:
  Disable any register name type checks.

Tag .insn pseudo mnemonics as such, to skip register name type checks
on those. They need to be skipped, as there do not exist .insn pseudo
mnemonics for every possible operand register type combination. Keep
track of the currently parsed operand number to provide it as reference
in warning messages.

To verify that the introduction of this change does not unnecessarily
affect the compilation of existing code the GNU Binutils, GNU C Library,
and Linux Kernel have been build with the new assembler, verifying that
the assembler did not generate any of the new warning messages.

gas/
	* config/tc-s390.c: Handle new assembler options
	"[no]warn-regtype-mismatch[=strict|relaxed|no". Annotate
	parsed register expressions with register type. Keep track of
	operand number being parsed. Print warning message in case of
	register type mismatch between instruction operand and parsed
	register expression.
	* doc/as.texi: Document new s390-specific assembler options
	"[no-]warn-regtype-mismatch[=strict|relaxed|no]".
	* NEWS: Mention new s390-specific register name type checks and
	related assembler option "warn-regtype-mismatch=strict|
	relaxed|no".
	* testsuite/gas/s390/s390.exp: Add test cases for new assembler
	option "warn-regtype-mismatch={strict|relaxed}".
	* testsuite/gas/s390/esa-g5.s: Fix register types in tests for
	didbr, diebr, tbdr, and tbedr.
	* testsuite/gas/s390/zarch-z13.s: Fix register types in tests
	for vgef, vgeg, vscef, and vsceg.
	* testsuite/gas/s390/zarch-warn-regtype-mismatch-strict.s:
	Tests for assembler option "warn-regtype-mismatch=strict".
	* testsuite/gas/s390/zarch-warn-regtype-mismatch-strict.l:
	Likewise.
	* gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-relaxed.s:
	Tests for assembler option "warn-regtype-mismatch=relaxed".
	* gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-relaxed.l:
	Likewise.
	* gas/testsuite/gas/s390/zarch-omitted-base-index-err.s: Update
	test cases for assembler option "warn-regtype-mismatch"
	defaulting to "relaxed".
	* testsuite/gas/s390/zarch-omitted-base-index-err.l: Likewise.

include/
	* opcode/s390.h (S390_INSTR_FLAG_PSEUDO_MNEMONIC): Add
	instruction flag to tag .insn pseudo-mnemonics.

opcodes/
	* s390-opc.c (s390_opformats): Tag .insn pseudo-mnemonics as
	such.

Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01 12:45:14 +01:00
Jens Remus
bd0ee1ee41 s390: Add test cases for base/index register 0
While at it add comments to logic to omit base and/or index register 0
in s390 disassembly.

opcodes/
	* s390-dis.c: Add comments related to omitting base and/or index
	register 0 in disassembly.
gas/
	* testsuite/gas/s390/s390.exp: Add test cases for base and/or
	index register 0.
	* testsuite/gas/s390/zarch-base-index-0.s: Add test cases for
	base and/or index register 0.
	* testsuite/gas/s390/zarch-base-index-0.d: Likewise.
	* testsuite/gas/s390/zarch-base-index-0-err.s: Add error test
	cases for base and/or index register 0.

Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01 12:45:14 +01:00
Jens Remus
996097d5ca s390: Use proper string lengths when parsing opcode table flags
opcodes/
	* s390-mkopc.c: Use proper string lengths when parsing opcode
	table flags.

Fixes: c5306fed7d ("s390: Support for jump visualization in disassembly")
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
2024-03-01 11:12:40 +01:00
Jens Remus
d9d4fc898d s390: Whitespace fixes in conditional branch flavor descriptions
opcodes/
	* s390-mkopc.c: Whitespace fixes in conditional branch flavor
	descriptions.

Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
2024-03-01 11:12:40 +01:00
Jan Beulich
c73a37b268 x86/APX: optimize certain XOR and SUB forms
While most logic in optimize_encoding() is already covering APX by way
of the earlier NDD->REX2 conversion, there's a remaining set of cases
which wants handling separately.
2024-03-01 09:21:40 +01:00
Srinath Parvathaneni
4b067447e1 aarch64: Fix the 2nd operand in gcsstr and gcssttr instructions.
The assembler wrongly expects plain register name instead of
memory-form 2nd operand for gcsstr and gcssttr instructions.
This patch fixes the issue.
2024-02-29 21:06:35 +00:00
Alan Modra
f757c5cae9 PR21739, Inconsistent diagnostics
PR 21739
cpu/
	* mep.opc (parse_lo16, parse_unsigned7): Mark %function
	message as no-c-format.
opcodes/
	* mep-asm.c: Regenerate.
2024-02-29 21:07:04 +10:30
Tatsuyuki Ishi
04d352509c RISC-V: Add assembly support for TLSDESC.
gas/
    * tc-riscv.c (percent_op_*): Add support for %tlsdesc_hi,
    %tlsdesc_load_lo, %tlsdesc_add_lo and %tlsdesc_call. percent_op_rtype
    renamed to percent_op_relax_only as this matcher is extended to handle
    jalr as well which is not R-type.
    (riscv_ip): Apply the percent_op_relax_only rename and update comment.
    (md_apply_fix): Add TLSDESC_* to relaxable list. Add TLSDESC_HI20 to
    TLS relocation check list.
    * testsuite/gas/riscv/tlsdesc.*: New test cases for TLSDESC relocation
    generation.
opcodes/
    * riscv-opc.c (riscv_opcodes): Add a new syntax for jalr with
    %tlsdesc_call annotations.
2024-02-29 15:02:51 +08:00
Matthieu Longo
d6a14e4138 aarch64: rename internals related to PAuth feature to use pauth in their naming for coherency
Hi,

Commits af1bd77 and 3f4ff08 introduced the Pointer Authentication feature with internal names that don't match the actual feature name pauth. The new feature PAuth_LR introduced in Armv9.5-A is an extension of the PAuth feature of Armv8.3-A. Using a different naming for it not based on the formerly "PAC" would create confusion.

Regression tested on aarch64-none-elf, and no regression found.

Ok for binutils-master? I don't have commit access so I need someone to commit on my behalf.

Regards,
Matthieu.
From 58b38358b2788939d81f2df7f5fb4c64a31ae06e Mon Sep 17 00:00:00 2001
From: Matthieu Longo <matthieu.longo@arm.com>
Date: Fri, 23 Feb 2024 11:30:40 +0000
Subject: [PATCH] aarch64: rename internals related to PAuth feature to use
 pauth in their naming for coherency

Commits af1bd77 and 3f4ff08 introduced the Pointer Authentication feature
with internal names that don't match the actual feature name pauth. The new
feature PAuth_LR introduced in Armv9.5-A is an extension of the PAuth feature
of Armv8.3-A. Using a different naming for it not based on the formerly "PAC"
would create confusion.
2024-02-27 12:46:15 +00:00
Jan Beulich
a40a04601f x86: also permit YMM/ZMM use in CFI directives
Next to code using %ymm<N> or %zmm<N> it is more natural to have .cfi_*
directives also reference those, not the corresponding %xmm<N>. Accept
their names as kind of aliases, i.e. resolving to the same numbers.

While extending the respective 64-bit testcase, also add %bnd<N> there
(should have happened right with 633789901c ["x86-64: Dwarf2 register
numbers for %bnd<N>"], sorry), requiring binutils/dwarf.c to be adjusted
accordingly as well.
2024-02-23 11:59:09 +01:00
Jan Beulich
2f630f60b5 x86/APX: INV{EPT,PCID,VPID} are WIG
While various other entries in version 003 of the spec aren't quite as
explicit (due to simply leaving the respective field blank), all three
have a clear IGNORED there. IOW they ought to be emitted with EVEX.W=0
by default (and respect -mevexwig=).
2024-02-23 11:58:15 +01:00
Paul Iannetta
9012a09f4f kvx: gas: missing aliases for $r14r15 in assembler.
Most registers from a register-pair suffixed by .lo and .hi suffixes.
This was not the case of $r14 and $r15 since they are defined by the
ABI: $r14 is the frame pointer, and $r15 is used to return aggregates
from functions.  We do not add aliases for $r12 (the stack pointer) and
$r13 (the tls register).

opcodes/ChangeLog:

	* kvx-opc.c: Regenerate.

gas/ChangeLog:

	* config/kvx-parse.h: Regenerate.
2024-02-20 12:07:57 +01:00
Paul Iannetta
9798722ef6 kvx: enable magic immediates for integer multiply-accumulate and CMOVE*
Affected instructions:
 - alu unit:
    cmovewp cmovehq
 - mau unit:
     maddwdp madduwdp maddsuwdp mma msbfwdp msbfuwdp
     msbfsuwdp mms mulwdp muluwdp mulsuwdp mm

opcodes/ChangeLog:

	* kvx-opc.c (struct kvxopc): Regenerate.

gas/ChangeLog:

	* config/kvx-parse.h: Regenerate.
2024-02-20 12:07:57 +01:00
Paul Iannetta
0593f8d6f7 kvx: gas: rename: or -> ior, xor -> eor
TCA instructions start with an X, this introduces ambiguities when it
comes to XOR (Is it the OR on the TCA or the XOR of the core?).  For this
reason, we rename OR to IOR and XOR to EOR.

OR and XOR variants are still valid on KV3-1 and KV3-2.  However, they
have been completely removed from KV4-1.

opcodes/ChangeLog:

	* kvx-opc.c: Regenerate.

include/ChangeLog:

	* opcode/kvx.h: Regenerate.

gas/ChangeLog:

	* config/kvx-parse.h: Regenerate.
	* testsuite/gas/kvx/kv3-1-insns-32.d: Regenerate.
	* testsuite/gas/kvx/kv3-1-insns-32.s: Regenerate.
	* testsuite/gas/kvx/kv3-1-insns-64.d: Regenerate.
	* testsuite/gas/kvx/kv3-1-insns-64.s: Regenerate.
	* testsuite/gas/kvx/kv3-2-insns-32.d: Regenerate.
	* testsuite/gas/kvx/kv3-2-insns-32.s: Regenerate.
	* testsuite/gas/kvx/kv3-2-insns-64.d: Regenerate.
	* testsuite/gas/kvx/kv3-2-insns-64.s: Regenerate.
	* testsuite/gas/kvx/kv4-1-insns-32.d: Regenerate.
	* testsuite/gas/kvx/kv4-1-insns-32.s: Regenerate.
	* testsuite/gas/kvx/kv4-1-insns-64.d: Regenerate.
	* testsuite/gas/kvx/kv4-1-insns-64.s: Regenerate.
2024-02-20 12:07:57 +01:00
Paul Iannetta
3c85dd404f kvx: gas: move the splat modifier to the immediate
The position of the splat modifier is now after the operand it
modifies and not attached directly to the opcode.

opcodes/ChangeLog:

	* kvx-opc.c: Regenerate.

include/ChangeLog:

	* opcode/kvx.h: Regenerate.

gas/ChangeLog:

	* config/kvx-parse.h: Regenerate.
	* testsuite/gas/kvx/kv3-1-insns-32.d: Regenerate.
	* testsuite/gas/kvx/kv3-1-insns-32.s: Regenerate.
	* testsuite/gas/kvx/kv3-1-insns-64.d: Regenerate.
	* testsuite/gas/kvx/kv3-1-insns-64.s: Regenerate.
	* testsuite/gas/kvx/kv3-2-insns-32.d: Regenerate.
	* testsuite/gas/kvx/kv3-2-insns-32.s: Regenerate.
	* testsuite/gas/kvx/kv3-2-insns-64.d: Regenerate.
	* testsuite/gas/kvx/kv3-2-insns-64.s: Regenerate.
	* testsuite/gas/kvx/kv4-1-insns-32.d: Regenerate.
	* testsuite/gas/kvx/kv4-1-insns-32.s: Regenerate.
	* testsuite/gas/kvx/kv4-1-insns-64.d: Regenerate.
	* testsuite/gas/kvx/kv4-1-insns-64.s: Regenerate.
2024-02-20 12:07:57 +01:00
Yury Khrustalev
1bc24c0dab aarch64: Add support for the id_aa64isar3_el1 system register
Hi,

[PATCH][Binutils] aarch64: Add support for the id_aa64isar3_el1 system register

AArch64 defines a read-only system register called id_aa64isar3_el1.
This patch also adds relevant tests.

Regression tested on the aarch64-none-elf and aarch64-none-linux-gnu targets
and no regressions was found.

Is this Ok for trunk? I do not have commit rights, if OK, can someone commit on my behalf?

Thanks,
Yury Khrustalev

From e42c835e8f2ee81150f498675f2faf108bbe79f8 Mon Sep 17 00:00:00 2001
From: Yury Khrustalev <yury.khrustalev@arm.com>
Date: Tue, 6 Feb 2024 11:05:39 +0000
Subject: [PATCH] [PATCH][Binutils] aarch64: Add support for the
 id_aa64isar3_el1 system register

AArch64 defines a read-only system register called id_aa64isar3_el1.
This patch also adds relevant tests.

Regression tested on the aarch64-none-elf and aarch64-none-linux-gnu targets
and no regressions was found.
2024-02-19 14:08:36 +00:00
Jan Beulich
c8054e730d x86/APX: drop stray IgnoreSize
While necessary on the legacy encodings, the EVEX ones don't need it.
Even more so when they're available for 64-bit mode only, when the
legacy encodings have the attribute only for correctly handling things
in 16-bit mode.
2024-02-16 10:20:08 +01:00
Jan Beulich
9405f24b8e x86: don't use VexWIG in SSE2AVX templates
Several years ago it was decided that SSE2AVX templates should not be
sensitive to -mvexwig= (upon my suggestion to consistently make all
sensitive as long as they don't require a specific setting of VEX.W).
Adjust the four that still are, switching to use of Vex128 at the same
time.
2024-02-16 10:19:11 +01:00
Jan Beulich
73f55087a4 x86: drop redundant Xmmword
While e20298da05 ("Remove redundant Byte, Word, Dword and Qword from
insn templates") did so for Byte/Word/Dword/Qword, the same kind of
redundancy was left in place for a few 128-bit SIMD operands.
2024-02-16 10:18:45 +01:00
Will Hawkins
7921285b6c objdump, as: add callx support for BPF CPU v1
Albeit not being a currently valid BPF instruction, callx is generated
by both clang and GCC when BPF programs are compiled unoptimized.
Until now, GCC would emit it only whe using the experimental
compiler-testing cpu version xbpf, whereas clang would emit it from
v1.  This patch makes GAS to accept callx also starting with cpu v1.

opcodes/ChangeLog

	* bpf-opc.c: Move callx into the v1 BPF CPU variant.

gas/ChangeLog

	* testsuite/gas/bpf/indcall-1-pseudoc.d: Do not select xbpf cpu
	version.
	* testsuite/gas/bpf/indcall-1.d: Likewise.
2024-02-15 15:11:44 +01:00
Yuriy Kolerov
c0852af056 arc: Put DBNZ instruction to a separate class
DBNZ instruction decrements its source register operand, and if
the result is non-zero it branches to the location defined by a signed
half-word displacement operand.

DBNZ instruction is in BRANCH class as other branch instrucitons
like B, Bcc, etc. However, DBNZ is the only branch instruction
that stores a branch offset in the second operand. Thus it must
be placed in a distinct class and treated differently.

For example, current logic of arc_insn_get_branch_target in GDB
assumes that a branch offset is always stored in the first operand
for BRANCH class and it's wrong for DBNZ.

include/ChangeLog:

2024-02-14  Yuriy Kolerov  <ykolerov@synopsys.com>

	* opcode/arc.h (enum insn_class_t): Add DBNZ class.

opcodes/ChangeLog:

2024-02-14  Yuriy Kolerov  <ykolerov@synopsys.com>

	* arc-tbl.h (dbnz): Use "DBNZ" class.
	* arc-dis.c (arc_opcode_to_insn_type): Handle "DBNZ" class.

gas/ChangeLog:

2024-02-14  Yuriy Kolerov  <ykolerov@synopsys.com>

	* config/tc-arc.c (is_br_jmp_insn_p): Add check against "DBNZ".
2024-02-14 11:36:52 +01:00
Peter Bergner
4199cf1e15 PowerPC: Add support for Power11 options
binutils/
	* doc/binutils.texi (PowerPC -M option): Mention power11 and pwr11.

gas/
	* config/tc-ppc.c: (md_show_usage): Mention -mpower11 and -mpwr11.
	* doc/c-ppc.texi: Likewise.

opcodes/
	* ppc-dis.c (ppc_opts): Add "power11" and "pwr11" entries.
	(powerpc_init_dialect): Default to "power11".
2024-02-09 10:52:23 -06:00
Jan Beulich
41e115853e x86/APX: with REX2 map 1 doesn't "chain" to maps 2 or 3
Don't wander into three_byte_table[] when REX2 is present.

While there also eliminate related confusion when accessing
dis386_twobyte[]: There's nothing 3-byte-ish involved there. Dropping
the odd variable gets things better in sync with 1-byte handling as
well.
2024-02-09 08:39:48 +01:00
Jan Beulich
ec3babb8c1 x86/APX: V{BROADCAST,EXTRACT,INSERT}{F,I}128 can also be expressed
Interestingly unlike VROUND{P,S}{S,D} and VPERM{F,I}128 they weren't
even present in the x86-64-apx-egpr-inval testcase, hence why I
overlooked that these can actually be encoded, (again) using suitable
AVX512 counterparts.

While there also "modernize" the adjacent AVX/AVX2 entries.
2024-02-09 08:39:20 +01:00
Jan Beulich
5a635f1f59 x86/APX: VROUND{P,S}{S,D} encodings require AVX512{F,VL}
In eea4357967 ("x86/APX: VROUND{P,S}{S,D} can generally be encoded") I
failed to add the AVX512* ISA dependency of the two new entries.
2024-02-09 08:38:52 +01:00
Jan Beulich
066673f6d5 x86: change type of Dwarf2 register numbers in register table
Already the %bnd<N> registers used numbers beyond 127, and eGPR ones are
all out of reach for "signed char", at least when CHAR_BITS=8. Switch to
"unsigned char", covering appropriately in places where the value
returned for "none" actually matters (in tc_x86_parse_to_dw2regnum()
this is actually achieved by altering how X_op is set).
2024-02-09 08:38:04 +01:00
Jose E. Marchesi
0c45feb159 bpf: there is no ldinddw nor ldabsdw instructions
There are no legacy ldind nor ldabs BPF instructions with BPF_SIZE_DW.
For some reason we were (incorrectly) supporting these.  This patch
updates the opcodes so the instructions get removed and modifies the
GAS manual and testsuite accordingly.

See discussion at
https://lore.kernel.org/bpf/110aad7a-f8a3-46ed-9fda-2f8ee54dcb89@linux.dev

Tested in bpf-uknonwn-none target, x86-64-linux-gnu host.

include/ChangeLog:

2024-01-29  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* opcode/bpf.h (enum bpf_insn_id): Remove BPF_INSN_LDINDDW and
	BPF_INSN_LDABSDW instructions.

opcodes/ChangeLog:

2024-01-29  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf-opc.c (bpf_opcodes): Remove BPF_INSN_LDINDDW and
	BPF_INSN_LDABSDW instructions.

gas/ChangeLog:

2024-01-29  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* doc/c-bpf.texi (BPF Instructions): There is no indirect 64-bit
	load instruction.
	(BPF Instructions): There is no absolute 64-bit load instruction.
	* testsuite/gas/bpf/mem.s: Update test accordingly.
	* testsuite/gas/bpf/mem-be-pseudoc.d: Likewise.
	* testsuite/gas/bpf/mem-be.d: Likewise.
	* testsuite/gas/bpf/mem-pseudoc.d: Likewise.
	* testsuite/gas/bpf/mem-pseudoc.s: Likewise.
	* testsuite/gas/bpf/mem.d: Likewise.
	* testsuite/gas/bpf/mem.s: Likewise.
2024-01-29 19:22:41 +01:00
Andrew Carlotti
0aac62aa32 aarch64: move SHA512 instructions to +sha3
SHA512 instructions were added to the architecture at the same time as SHA3
instructions, but later than the SHA1 and SHA256 instructions.  Furthermore,
implementations must support either both or neither of the SHA512 and SHA3
instruction sets.  However, SHA512 instructions were originally (and
incorrectly) added to Binutils under the +sha2 flag.

This patch moves SHA512 instructions under the +sha3 flag, which matches the
architecture constraints and existing GCC and LLVM behaviour.
2024-01-26 14:58:00 +00:00
Jan Beulich
c179ace029 x86/APX: TILE{RELEASE,ZERO} have no EVEX encodings
Re-using the entire VEX decode hierarchy for the respective major opcode
has led to those two also being decoded as-if valid. Follow the earlier
USE_X86_64_EVEX_{PFX,W}_TABLE approach to avoid this happening.
2024-01-26 10:34:48 +01:00
Jan Beulich
836f6ceb83 x86/APX: no need to have decode go through x86_64_table[]
As suggested during review already, all such entries have their first
slot as Bad_Opcode, so by adding two more enumerators we can avoid doing
that decode step altogether.
2024-01-26 10:34:24 +01:00
Jan Beulich
0ebcbb1bd0 x86/APX: optimize MOVBE
With identical source and destination it can be covered by the NDD-to-
legacy conversion logic as well, even if in this case the original insn
doesn't use an NDD encoding. The size savings are even better here, for
the replacement (BSWAP) not having a ModR/M byte.
2024-01-26 10:31:38 +01:00
mengqinggang
969f5c0e12 LoongArch: gas: Add support for s9 register
In LoongArch ABI, r22 register can be used as frame pointer or
static register(s9).

Link: https://github.com/loongson/la-abi-specs/blob/release/lapcs.adoc#general-purpose-registers
2024-01-26 16:49:43 +08:00
Andrew Carlotti
f895041bb9 aarch64: Eliminate unused variable warnings with -DNDEBUG 2024-01-24 12:14:59 +00:00
Nick Clifton
e97522312b Updated Serbian translations for th bfd, gold and opcodes directories 2024-01-22 17:26:36 +00:00
Mark Wielaard
5bc519bf0c opcodes: tic4x_disassemble swap xcalloc arguments
GCC 14 will detect when the size and count arguments of calloc are
swapped.

binutils-gdb/opcodes/tic4x-dis.c: In function ‘tic4x_disassemble’:
binutils-gdb/opcodes/tic4x-dis.c:710:32: error: ‘xcalloc’ sizes specified with ‘sizeof’ in the earlier argument and not in the later argument [-Werror=calloc-transposed-args]
  710 |       optab = xcalloc (sizeof (tic4x_inst_t *), (1 << TIC4X_HASH_SIZE));
      |                                ^~~~~~~~~~~~
binutils-gdb/opcodes/tic4x-dis.c:710:32: note: earlier argument should specify number of elements, later size of each element
binutils-gdb/opcodes/tic4x-dis.c:712:40: error: ‘xcalloc’ sizes specified with ‘sizeof’ in the earlier argument and not in the later argument [-Werror=calloc-transposed-args]
  712 |       optab_special = xcalloc (sizeof (tic4x_inst_t *), TIC4X_SPESOP_SIZE);
      |                                        ^~~~~~~~~~~~
binutils-gdb/opcodes/tic4x-dis.c:712:40: note: earlier argument should specify number of elements, later size of each element

opcodes/ChangeLog:

	* /tic4x-dis.c (tic4x_disassemble): Swap size and count xcalloc
	arguments.
2024-01-22 18:16:42 +01:00
Jan Beulich
633789901c x86-64: Dwarf2 register numbers for %bnd<N>
I don't see why we shouldn't record them when they have been allocated,
even if they're (bogusly) named as reserved in the ABI right now.
2024-01-19 10:19:15 +01:00
Jan Beulich
eea4357967 x86/APX: VROUND{P,S}{S,D} can generally be encoded
VRNDSCALE{P,S}{S,D} is the AVX512 generalization of these AVX insns. As
long as the immediate has the top 4 bits clear, they are equivalent to
the earlier VEX-encoded insns, and hence can be used to permit use of
eGPR-s in the memory operand. Since this is the normal way of using
these insns, also alter the resulting diagnostic to complain about the
immediate, not the eGPR use.
2024-01-19 10:18:32 +01:00
Jan Beulich
2519809009 x86/APX: be consistent with insn suffixes
When there's a suitably disambiguating register operand, suffixes are
generally omitted (unless in suffix-always mode). All NDD insns have a
suitable register operand, so they shouldn't have suffixes by default.
2024-01-19 10:17:44 +01:00
Jan Beulich
4945a0c46c x86: drop redundant EVex128 from PUSH2/POP2
EVexMap4 already covers that.
2024-01-19 10:16:28 +01:00
Jan Beulich
5190fa3828 x86: support APX forms of U{RD,WR}MSR
This was missed in 6177c84d5e ("Support APX GPR32 with extend evex
prefix").
2024-01-19 10:16:00 +01:00
Nick Clifton
0d656dfe5b Add note to translators not to translate z/Architecture 2024-01-18 11:25:48 +00:00
Nick Clifton
bfdd2ca621 Updated translations for various sub-directories 2024-01-18 11:23:48 +00:00
Nick Clifton
e775d3a9b7 Change version to 2.42.50 and regenerate files 2024-01-15 15:13:36 +00:00
Nick Clifton
299b91cd85 Add markers for 2.42 branch 2024-01-15 14:42:15 +00:00
Victor Do Nascimento
f1870e2fad aarch64: rcpc3: Regenerate aarch64-*-2.c files 2024-01-15 13:11:48 +00:00
Victor Do Nascimento
42fd649404 aarch64: rcpc3: Add FP load/store insns
Along with the relevant unit-tests, this adds the following rcpc3
instructions:

  STL1  { <Vt>.D }[<index>], [<Xn|SP>]
  LDAP1 { <Vt>.D }[<index>], [<Xn|SP>]

  LDAPUR <Bt>, [<Xn|SP>{, #<simm>}]
  LDAPUR <Ht>, [<Xn|SP>{, #<simm>}]
  LDAPUR <St>, [<Xn|SP>{, #<simm>}]
  LDAPUR <Dt>, [<Xn|SP>{, #<simm>}]
  LDAPUR <Qt>, [<Xn|SP>{, #<simm>}]

  STLUR <Bt>, [<Xn|SP>{, #<simm>}]
  STLUR <Ht>, [<Xn|SP>{, #<simm>}]
  STLUR <St>, [<Xn|SP>{, #<simm>}]
  STLUR <Dt>, [<Xn|SP>{, #<simm>}]
  STLUR <Qt>, [<Xn|SP>{, #<simm>}]

with `#<simm>' taking on a signed 8-bit integer value in the range
[-256,255] and `index' the values 0 or 1.

Co-authored-by: Srinath Parvathaneni <srinath.parvathaneni@arm.com>
2024-01-15 13:11:48 +00:00
Victor Do Nascimento
e771eaf8bb aarch64: rcpc3: Add integer load/store insns
Along with the relevant unit tests and updates to the existing
regression tests, this adds support for the following novel rcpc3
insns:

  LDIAPP <Wt1>, <Wt2>, [<Xn|SP>]
  LDIAPP <Wt1>, <Wt2>, [<Xn|SP>], #8
  LDIAPP <Xt1>, <Xt2>, [<Xn|SP>]
  LDIAPP <Xt1>, <Xt2>, [<Xn|SP>], #16

  STILP <Wt1>, <Wt2>, [<Xn|SP>]
  STILP <Wt1>, <Wt2>, [<Xn|SP>, #-8]!
  STILP <Xt1>, <Xt2>, [<Xn|SP>]
  STILP <Xt1>, <Xt2>, [<Xn|SP>, #-16]!

  LDAPR <Wt>, [<Xn|SP>], #4
  LDAPR <Xt>, [<Xn|SP>], #8

  STLR <Wt>, [<Xn|SP>, #-4]!
  STLR <Xt>, [<Xn|SP>, #-8]!
2024-01-15 13:11:48 +00:00
Victor Do Nascimento
b88fbd5213 aarch64: rcpc3: Define RCPC3_INSN macro
This patch adds the necessary macro for encoding FEAT_RCPC3-dependent
instructions in Binutils.
2024-01-15 13:11:48 +00:00