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Author SHA1 Message Date
Marcus Comstedt
f36ce378b4 RISC-V: Fix riscv gas/ld testsuites failures for big endian. 
Add riscv_choose_[ilp32|lp64]_emul, and use them to choose the correct
linker script rather than set elf[32|64]lriscv directly.

gas/
    * testsuite/gas/riscv/li32.d: Accept bigriscv in addition
    to littleriscv.
    * testsuite/gas/riscv/li64.d: Likewise.
    * testsuite/gas/riscv/lla32.d: Likewise.
    * testsuite/gas/riscv/lla64.d: Likewise.
    * testsuite/gas/riscv/march-ok-g2.d: Likewise.
    * testsuite/gas/riscv/march-ok-g2_p1.d: Likewise.
    * testsuite/gas/riscv/march-ok-g2p0.d: Likewise.
    * testsuite/gas/riscv/march-ok-i2p0.d: Likewise.
    * testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d: Likewise.
    * testsuite/gas/riscv/march-ok-nse-with-version.d: Likewise.
    * testsuite/gas/riscv/march-ok-two-nse.d: Likewise.

ld/
    * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Added
    riscv_choose_[ilp32|lp64]_emul to choose the correct linker script.
    * testsuite/ld-riscv-elf/attr-merge-arch-01.d: Call
    riscv_choose_[ilp32|lp64]_emul instead of hardcoding elf[32|64]lriscv.
    * testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
    * testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
    * testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d: Likewise.
    * testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d: Likewise.
    * testsuite/ld-riscv-elf/c-lui-2.d: Likewise.
    * testsuite/ld-riscv-elf/c-lui.d: Likewise.
    * testsuite/ld-riscv-elf/call-relax.d: Likewise.
    * testsuite/ld-riscv-elf/pcrel-lo-addend-2.d: Likewise.
    * testsuite/ld-riscv-elf/pcrel-lo-addend.d: Likewise.
    * testsuite/ld-riscv-elf/weakref32.d: Accept bigriscv in addition
    to littleriscv.
    * testsuite/ld-riscv-elf/weakref64.d: Likewise.
 2021-01-06 18:01:41 +08:00
Jim Wilson
9d1da81b26 RISC-V: Optimize lui and auipc relaxations for undefweak symbol. 
For the lui and auipc relaxations, since the symbol value of an undefined weak
symbol is always be zero, we can optimize the patterns into a single LI/MV/ADDI
instruction.

	bfd/
	* elfnn-riscv.c (riscv_pcgp_hi_reloc): Add new field undefined_weak.
	(riscv_record_pcgp_hi_reloc): New parameter undefined_weak.
	Set undefined_weak field from it.
	(relax_func_t): New parameter undefined_weak.
	(_bfd_riscv_relax_call): New ignored parameter undefined_weak.
	(_bfd_riscv_relax_tls_le): Likewise.
	(_bfd_riscv_relax_align): Likewise.
	(_bfd_riscv_relax_delete): Likewise.
	(_bfd_riscv_relax_lui): New parameter undefined_weak.  If true,
	allow relaxing.  For LO12* relocs, set rs1 to x0 when undefined_weak.
	(_bfd_riscv_relax_pc): New parameter undefined_weak.  For LO12* relocs,
	set undefined_weak from hi_reloc.  If true, allow relaxing.  For LO12*
	relocs, set rs1 to x0 when undefined_weak and change to non-pcrel
	reloc.
	(_bfd_riscv_relax_section): New local undefined_weak.  Set for
	undef weak relocs that can be relaxed.  Pass to relax_func call.

	ld/
	* testsuite/ld-riscv-elf/weakref32.s: Add relaxable undef weak code.
	* testsuite/ld-riscv-elf/weakref64.s: Likewise.
	* testsuite/ld-riscv-elf/weakref32.d: Updated.
	* testsuite/ld-riscv-elf/weakref64.d: Updated.
 2019-09-20 15:01:20 -07:00
Jim Wilson
cf7a5066b9 RISC-V: Handle out-of-range calls to undefined weak. 
bfd/
	PR ld/23244
	* elfnn-riscv.c (riscv_elf_relocate_section) <R_RISCV_CALL>: Check
	for and handle an undefined weak with no PLT.

	ld/
	* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Run new weak ref tests.
	* testsuite/ld-riscv-elf/weakref.ld: New.
	* testsuite/ld-riscv-elf/weakref32.d: New.
	* testsuite/ld-riscv-elf/weakref32.s: New.
	* testsuite/ld-riscv-elf/weakref64.d: New.
	* testsuite/ld-riscv-elf/weakref64.s: New.
 2018-06-03 15:42:29 -07:00