Only the xcoff and pe extensions were enabled. Build the lot, and fix
some more printf format problems when the host is 32-bit.
* configure.ac (od_vectors): Set up for --enable-targets=all.
* configure: Regenerate.
* od-elf32_avr.c (elf32_avr_dump_mem_usage): Correct format
specifier vs. arg mismatch.
(elf32_avr_dump_avr_prop): Likewise.
This makes sure copy_archive exits with ibfd and obfd closed. Error
paths didn't do that, leading to memory leaks. None of this matters
very much.
* objcopy.c (copy_archive): bfd_close ibfd and obfd on error
return paths. Remove braces around "list" free.
(copy_file): Don't close invalid file descriptor.
bfd/
* coff-rs6000.c (add_range): Revise comment, noting possible fail.
(_bfd_xcoff_openr_next_archived_file): Start with clean ranges.
binutils/
* bfdtest1.c: Enhance to catch errors on second scan.
For example, objcopy --set-section-flags .data=alloc,large will add
SHF_X86_64_LARGE to the .data section. Omitting "large" will drop the
SHF_X86_64_LARGE flag.
The bfd_section flag is named generically, SEC_ELF_LARGE, in case other
processors want to follow SHF_X86_64_LARGE. SEC_ELF_LARGE has the same
value as SEC_TIC54X_BLOCK used by coff.
bfd/
* section.c: Define SEC_ELF_LARGE.
* bfd-in2.h: Regenerate.
* elf64-x86-64.c (elf_x86_64_section_flags, elf_x86_64_fake_sections,
elf_x86_64_copy_private_section_data): New.
binutils/
* NEWS: Mention the new feature for objcopy.
* doc/binutils.texi: Mention "large".
* objcopy.c (parse_flags): Parse "large".
(check_new_section_flags): Error if "large" is used with a
non-x86-64 ELF target.
* testsuite/binutils-all/x86-64/large-sections.d: New.
* testsuite/binutils-all/x86-64/large-sections.s: New.
* testsuite/binutils-all/x86-64/large-sections-i386.d: New.
* testsuite/binutils-all/x86-64/large-sections-2.d: New.
* testsuite/binutils-all/x86-64/large-sections-2-x32.d: New.
The ARC HS5x and ARC HS6x processors are based on the new ARCv3 ISA
that implements a full range of 32-bit and 64-bit instructions. These
processors feature a high-speed 10-stage, dual-issue pipeline that
offers increased utilization of functional units with a limited
increase in power and area. The HS5x processors feature a 32-bit
pipeline that can execute all ARCv3 32-bit instructions, while the
HS6x processors feature a full 64-bit pipeline and register file that
can execute both 32-bit and 64-bit instructions. In addition, the ARC
HS6x supports 64-bit virtual and 52-bit physical address spaces to
enable direct addressing of current and future large memories, as well
as 128-bit loads and stores for efficient data movement.
This readelf patch updates/adds Synopsys ARCv3 machine name fileds and
supported relocations.
Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
This commit adds the recently added support of the RISC-V vector crypto
extensions to the NEWS file.
binutils/ChangeLog:
* NEWS: Announce new RISC-V vector crypto extensions.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
We picked up support for a few new extensions over the last weeks
(this may need further updating prior to the next release), list them
in the NEWS file.
binutils/ChangeLog:
* binutils/NEWS: announce suuport for the new RISC-V
extensions (Zicond, Zfa, XVentanaCondOps).
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Discard non-alloc sections when section headers are stripped.
bfd/
PR ld/25617
* elf.c (_bfd_elf_assign_file_positions_for_non_load): Skip
non-load sections without section header.
(_bfd_elf_write_object_contents): Don't set the sh_name field
without section header. Write out the .shstrtab section only
if its sh_offset field isn't -1.
binutils/
PR ld/25617
* objcopy.c (is_strip_section_1): Remove non-alloc sections for
--strip-section-headers.
ld/
PR ld/25617
* ldlang.c (lang_discard_section_p): Discard non-alloc sections
if we are stripping section headers.
I see these warnings from time to time, when configuring a build with --enable-pgo-build=lto, I haven't yet found out why I see these sometime, and why not. E.g. https://gcc.gnu.org/PR109241. Just ignore these when they appear in test cases. lto-wrapper: warning: using serial compilation of N LTRANS jobs
The Allegrex CPU was created by Sony Interactive Entertainment to power
their portable console, the PlayStation Portable.
The pspdev organization maintains all sorts of tools to create software
for said device including documentation.
Signed-off-by: David Guillen Fandos <david@davidgf.net>
Commit 89c70cd358 apparently results in a bogus "value may be used
uninitialized" warning with some combination of compiler and
optimisation options.
* readelf.c (target_specific_reloc_handling): Init value.
Test on:
mips64-linux-gnuabi64
mips64el-linux-gnuabi64
mipsisa64-linux-gnuabi64
mipsisa64el-linux-gnuabi64
mipsisa64r2-linux-gnuabi64
mipsisa64r2el-linux-gnuabi64
mipsisa64r6-linux-gnuabi64
mipsisa64r6el-linux-gnuabi64
Introduce
run_dump_test_o32l
run_dump_test_n32l
run_dump_test_n64l
Which use `-march=from-abi` for pre-R6 testcases,
like micromips/mips16e etc.
For cases doesn't use run_dump_test_*, we use
-mips32r2 for micromips32
-mips1 for mips16-32
-march=from-abi for testcases to o32/n32/n64 both/all.
Replace `addi` with `addiu` for some cases for both r6 and pre-R6.
Introduce some new testcases for r6 with FPXX/FP64.
Introduce new testcase: comdat-reloc-r6.
Skip `default` in mips_arch_list_matching if triple is mipsisa*, due to:
1)it will cannot match mipsr6@*.d: since mips32rN/mips64rN
will always be used, it won't be a problem.
2)some test think -march=mips64rN will alway true for mipsisa64rN,
which is not true now.
This patch fix testsuite for all r6-default gnu triples:
mipsisa32r6-linux-gnu
mipsisa32r6el-linux-gnu
mips-img-linux-gnu
mipsel-img-linux-gnu
mipsisa64r6-linux-gnu
mipsisa64r6el-linux-gnu
This fixes two buffer overflows found by fuzzers.
* readelf.c (target_specific_reloc_handling): Sanity check
loongarch reloc symbol index. Don't apply reloc after errors.
Reduce translation work of "invalid symbol index" error message.
* od-pe.c (targ_info): New array.
(get_target_specific_info): New function.
(decode_machine_number): Retire. Use get_target_specific_info instead.
(is_pe_object_magic): Likewise.
(dump_pe_file_header): Display more information.
Rework layout to be similar to that from 'objdump -p'.
Add code to handle larger than normnal AOUT headers.
arm-pe looks to be a very old PE implementation, incompatible with
current arm-wince-pe. arm-pe has different relocations and uses
ARMMAGIC which has this comment: "I just made this up". Well, OK, I
don't know the history but it was probably before Microsoft "just made
up" their constants for ARM windows CE.
This patch supports objdump -P for arm-pe, and another magic constant
that may appear in object files. (I don't think binutils generates
files using ARMV7PEMAGIC aka IMAGE_FILE_MACHINE_ARMNT.)
* od-pe.c (is_pe_object_magic): Handle IMAGE_FILE_MACHINE_ARMNT
and ARMMAGIC.
* od-pe.c: New file: Dumps fields in PE format headers.
* configure.ac (od_vectors): Add objdump_private_desc_pe for PE format targets. (od_files): Add od-pe for PE format targets.
* configure: Regenerate.
* Makefile.am (CFILES): Add od-pe.c (EXTRA_objdump_SOURCE): Likewise.
* Makefile.in: Generate.
* NEWS: Mention the new feature.
* doc/binutils.texi: Document the new support.
* objdump.c (wide_output): Change from local to global.
* objdump.h (wide_output): Prototype. (objdump_private_desc_pe): Prototype.
* testsuite/binutils-all/objdump.exp: Add a test of the new feature.
Revert value of DT_ENCODING to as it was before commit a7fd118627, and
adjust readelf.
include/
* elf/common.h (DT_ENCODING): Set back to 32.
binutils/
* readelf.c (struct filedata): Don't size dynamic_info array
using DT_ENCODING.
96d6e190e9
There are some known limitations for now,
* Do not shrink the length of the uleb128 value, even if the value is reduced
after relaxations. Also reports error if the length grows up.
* The R_RISCV_SET_ULEB128 needs to be paired with and be placed before the
R_RISCV_SUB_ULEB128.
bfd/
* bfd-in2.h: Regenerated.
* elfnn-riscv.c (perform_relocation): Perform R_RISCV_SUB_ULEB128 and
R_RISCV_SET_ULEB128 relocations. Do not shrink the length of the
uleb128 value, and report error if the length grows up. Called the
generic functions, _bfd_read_unsigned_leb128 and _bfd_write_unsigned_leb128,
to encode the uleb128 into the section contents.
(riscv_elf_relocate_section): Make sure that the R_RISCV_SET_ULEB128
must be paired with and be placed before the R_RISCV_SUB_ULEB128.
* elfxx-riscv.c (howto_table): Added R_RISCV_SUB_ULEB128 and
R_RISCV_SET_ULEB128.
(riscv_reloc_map): Likewise.
(riscv_elf_ignore_reloc): New function.
* libbfd.h: Regenerated.
* reloc.c (BFD_RELOC_RISCV_SET_ULEB128, BFD_RELOC_RISCV_SUB_ULEB128):
New relocations to support .uleb128 subtraction.
gas/
* config/tc-riscv.c (md_apply_fix): Added BFD_RELOC_RISCV_SET_ULEB128
and BFD_RELOC_RISCV_SUB_ULEB128.
(s_riscv_leb128): Updated to allow uleb128 subtraction.
(riscv_insert_uleb128_fixes): New function, scan uleb128 subtraction
expressions and insert fixups for them.
(riscv_md_finish): Called riscv_insert_uleb128_fixes for all sections.
include/
* elf/riscv.h ((R_RISCV_SET_ULEB128, (R_RISCV_SUB_ULEB128): Defined.
ld/
* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
* testsuite/ld-riscv-elf/uleb128*: New testcase for uleb128 subtraction.
binutils/
* testsuite/binutils-all/nm.exp: Updated since RISCV supports .uleb128.
