Section alignment for coff-go32 is inconsistent - The '.text' and
'.data' sections are 16-byte aligned, but named sections '.text.*' and
'.data.*' are only 4-byte aligned. '.gnu.linkonce.r.*' is aligned to
16 bytes, yet '.rodata' and '.rodata.*' are aligned to 4 bytes. For
'.bss' all input sections are only aligned to 4 bytes.
This primarily can cause trouble when using SSE instructions, which
require their memory operands to be aligned to 16-byte boundaries.
This patch solves the issue simply by setting the section alignment
to 16 bytes, for all code and data sections referenced in the default
linker script.
* coff-go32.c (COFF_SECTION_ALIGNMENT_ENTRIES): Use partial
name match for .text, .data. Add entries for .const, .rodata,
.bss, .gnu.linkonce.b.
Commit b69c9d41e8 edited bfd/Makefile.in rather than using automake,
which meant a typo in Makefile.am was not discovered and other
differences in Makefile.in are seen with a proper regeneration. One
difference was lack of an empty line between the pe-aarch64igen.c rule
and the following $(BFD32_LIBS) etc. dependency rule, in the
regenerated file. Not that it matters for proper "make" behaviour,
but it's nicer with a line between those rules. Moving the rule
earlier seems to cure the missing empty line.
* Makefile.am (BFD64_BACKENDS): Correct typo.
(BFD_H_DEPS, LOCAL_H_DEPS): Move earlier. Move rule using these
deps earlier too.
* Makefile.in: Regenerate.
* po/BLD-POTFILES.in: Regenerate.
* po/SRC-POTFILES.in: Regenerate.
This adds support for efi-*-aarch64 by virtue of adding a new PEI target
pei-aarch64-little. This is not a full target and only exists to support EFI
at this time.
This means that this target does not support relocation processing and is mostly
a container format. This format has been added to elf based aarch64 targets
such that efi images can be made natively on Linux.
However this target is not valid for use with gas but only with objcopy.
With these changes the resulting file is recognized as an efi image by
third party tools:
> pecli info hello.efi
Metadata
================================================================================
MD5: 598c32a778b0f0deebe977fef8578c4e
SHA1: 4580121edd5cb4dc40f51b28f171fd15250df84c
SHA256: 3154bd7cf42433d1c957f6bf55a17ad8c57ed41b29df2d485703349fd6ff1d5c
Imphash:
Size: 47561 bytes
Type: PE32+ executable (EFI application) (stripped to external PDB), for MS Windows
Compile Time: 1970-01-01 00:00:00 (UTC - 0x0 )
Entry point: 0x2000 (section .text)
Sections
================================================================================
Name RWX VirtSize VirtAddr RawAddr RawSize Entropy md5
.text R-X 0x5bb0 0x2000 0x400 0x5c00 6.39 551fbc264256a3f387de8a891500ae0d
.reloc R-- 0xc 0x8000 0x6000 0x200 0.02 0c45f6d812d079821c1d54c09ab89e1d
.data RW- 0x1d88 0x9000 0x6200 0x1e00 4.18 5d1137c09f01289dc62bf754f7290db3
.dynamic RW- 0xf0 0xb000 0x8000 0x200 0.34 5c94ed3206f05a277e6f04fbf131f131
.rela R-- 0xe58 0xc000 0x8200 0x1000 1.87 8b5c6bc30f3acb7ca7bf2e6789d68519
.dynsym R-- 0x138 0xd000 0x9200 0x200 0.96 bdcf5101da51aadc663ca8859f88138c
Imports
================================================================================
Any magic number is based on the Microsoft PE specification [1].
[1] https://docs.microsoft.com/en-us/windows/win32/debug/pe-format
bfd/ChangeLog:
2021-10-21 Tamar Christina <tamar.christina@arm.com>
PR binutils/26206
* .gitignore (pe-aarch64igen.c): New.
* Makefile.am (pei-aarch64.lo, pe-aarch64igen.lo, pei-aarch64.c,
pe-aarch64igen.c): Add support.
* Makefile.in: Likewise.
* bfd.c (bfd_get_sign_extend_vma): Add pei-aarch64-little.
* coff-aarch64.c: New file.
* coffcode.h (coff_set_arch_mach_hook, coff_set_flags,
coff_write_object_contents) Add aarch64 (aarch64_pei_vec) support.
* config.bfd: Likewise.
* configure: Likewise.
* configure.ac: Likewise.
* libpei.h (GET_OPTHDR_IMAGE_BASE, PUT_OPTHDR_IMAGE_BASE,
GET_OPTHDR_SIZE_OF_STACK_RESERVE, PUT_OPTHDR_SIZE_OF_STACK_RESERVE,
GET_OPTHDR_SIZE_OF_STACK_COMMIT, PUT_OPTHDR_SIZE_OF_STACK_COMMIT,
GET_OPTHDR_SIZE_OF_HEAP_RESERVE, PUT_OPTHDR_SIZE_OF_HEAP_RESERVE,
GET_OPTHDR_SIZE_OF_HEAP_COMMIT, PUT_OPTHDR_SIZE_OF_HEAP_COMMIT,
GET_PDATA_ENTRY, _bfd_peAArch64_bfd_copy_private_bfd_data_common,
_bfd_peAArch64_bfd_copy_private_section_data,
_bfd_peAArch64_get_symbol_info, _bfd_peAArch64_only_swap_filehdr_out,
_bfd_peAArch64_print_private_bfd_data_common,
_bfd_peAArch64i_final_link_postscript,
_bfd_peAArch64i_only_swap_filehdr_out, _bfd_peAArch64i_swap_aouthdr_in,
_bfd_peAArch64i_swap_aouthdr_out, _bfd_peAArch64i_swap_aux_in,
_bfd_peAArch64i_swap_aux_out, _bfd_peAArch64i_swap_lineno_in,
_bfd_peAArch64i_swap_lineno_out, _bfd_peAArch64i_swap_scnhdr_out,
_bfd_peAArch64i_swap_sym_in, _bfd_peAArch64i_swap_sym_out,
_bfd_peAArch64i_swap_debugdir_in, _bfd_peAArch64i_swap_debugdir_out,
_bfd_peAArch64i_write_codeview_record,
_bfd_peAArch64i_slurp_codeview_record,
_bfd_peAArch64_print_ce_compressed_pdata): New.
* peXXigen.c (_bfd_XXi_swap_aouthdr_in, _bfd_XXi_swap_aouthdr_out,
pe_print_pdata, _bfd_XX_print_private_bfd_data_common,
_bfd_XX_bfd_copy_private_section_data, _bfd_XXi_final_link_postscript):
Support COFF_WITH_peAArch64,
* pei-aarch64.c: New file.
* peicode.h (coff_swap_scnhdr_in, pe_ILF_build_a_bfd, pe_ILF_object_p):
Support COFF_WITH_peAArch64.
(jtab): Add dummy entry that traps.
* targets.c (aarch64_pei_vec): New.
binutils/ChangeLog:
2021-10-21 Tamar Christina <tamar.christina@arm.com>
PR binutils/26206
* NEWS: Add new support.
* objcopy.c (convert_efi_target): Add efi-*-aarch64 support.
* testsuite/binutils-all/aarch64/pei-aarch64-little.d: New test.
* testsuite/binutils-all/aarch64/pei-aarch64-little.s: New test.
include/ChangeLog:
2021-10-21 Tamar Christina <tamar.christina@arm.com>
PR binutils/26206
* coff/aarch64.h: New file.
* coff/pe.h (IMAGE_FILE_MACHINE_ARM64): New.
If we always use the .option arch to call the riscv_update_subset, then
it is almost impossible that the input string will be NULL. Therefore,
just remove the redundant NULL pointer check in the riscv_update_subset.
bfd/
* elfxx-riscv.c (riscv_update_subset): Removed the redundant NULL
pointer check.
The architecture parser in riscv_update_subset shouldn't check (or access)
the pointer space which doesn't exist.
bfd/
pr 28610
* elfxx-riscv.c (riscv_update_subset): The architecture parser
shouldn't access the pointer space which doesn't exist.
This comment was long time ago associated to the function
"xcoff_build_ldsyms" which have since been replaced by
"xcoff_build_ldsym".
* xcofflink.c: Remove wrong comment.
https://github.com/riscv/riscv-asm-manual/pull/67
Format:
.option arch, +<extension><version>, ...
.option arch, -<extension>
.option arch, =<ISA string>
The new direcitve is used to enable/disable extensions for the specific
code region. For example,
.attribute arch, "rv64ic" # arch = rv64i2p0_c2p0
.option push
.option arch, +d2p0, -c # arch = rv64i2p0_f2p0_d2p0, f is added implied
.option arch, =rv32gc # arch = rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0
.option pop # arch = rv64i2p0_c2p0
Note that,
1. ".option rvc/norvc" have the same behavior as ".option arch +c/-c".
2. ".option arch -i" is illegal, since we cannot remove base i extension.
3. If arch=rv64i2p0, then ".option arch, +i3p0" will update the i's version
from 2.0 to 3.0.
4. If arch=rv64i3p0, then ".option arch, +i" will update the i's version
from 2.0 to the default one according to the chosen isa spec.
bfd/
* elfxx-riscv.c (riscv_add_subset): If the subset is already added,
and the new versions are not RISCV_UNKNOWN_VERSION, then update the
versions to the subset list.
(riscv_copy_subset): New function. Copy the subset from list.
(riscv_copy_subset_list): New function. Return the new copyed list.
(riscv_update_subset): Updated to make .option arch directives workable.
* elfxx-riscv.h: Updated.
gas/
* config/tc-riscv.c (riscv_subsets): Defined as a pointer.
(riscv_rps_as): Init the subset_list to NULL, we will set it later
once riscv_opts_stack is created or updated.
(struct riscv_option_stack, riscv_opts_stack): Moved forward.
(riscv_set_arch): Updated.
(s_riscv_option): Support new .option arch directive, to add, remove
or update subsets for the specific code region.
(riscv_write_out_attrs): Updated.
* doc/c-riscv.texi: Added document for new .option arch directive.
* testsuite/gas/riscv/option-arch-01a.d: New testcase.
* testsuite/gas/riscv/option-arch-01b.d: Likewise.
* testsuite/gas/riscv/option-arch-01.s: Likewise..
* testsuite/gas/riscv/option-arch-02.d: Likewise.
* testsuite/gas/riscv/option-arch-02.s: Likewise.
* testsuite/gas/riscv/option-arch-fail.d: Likewise.
* testsuite/gas/riscv/option-arch-fail.l: Likewise.
* testsuite/gas/riscv/option-arch-fail.s: Likewise.
This is the original discussion,
https://github.com/riscv/riscv-elf-psabi-doc/pull/190
And here is the glibc part,
https://sourceware.org/pipermail/libc-alpha/2021-August/129931.html
For binutils part, we need to support a new direcitve: .variant_cc.
The function symbol marked by .variant_cc means it need to be resolved
directly without resolver for dynamic linker. We also add a new dynamic
entry, STO_RISCV_VARIANT_CC, to indicate there are symbols with the
special attribute in the dynamic symbol table of the object.
I heard that llvm already have supported this in their mainline, so
I think it's time to commit this.
bfd/
* elfnn-riscv.c (riscv_elf_link_hash_table): Added variant_cc
flag. It is used to check if relocations for variant CC symbols
may be present.
(allocate_dynrelocs): If the symbol has STO_RISCV_VARIANT_CC
flag, then raise the variant_cc flag of riscv_elf_link_hash_table.
(riscv_elf_size_dynamic_sections): Added dynamic entry for
variant_cc.
(riscv_elf_merge_symbol_attribute): New function, used to merge
non-visibility st_other attributes, including STO_RISCV_VARIANT_CC.
binutils/
* readelf.c (get_riscv_dynamic_type): New function.
(get_dynamic_type): Called get_riscv_dynamic_type for riscv targets.
(get_riscv_symbol_other): New function.
(get_symbol_other): Called get_riscv_symbol_other for riscv targets.
gas/
* config/tc-riscv.c (s_variant_cc): Marked symbol that it follows a
variant CC convention.
(riscv_elf_copy_symbol_attributes): Same as elf_copy_symbol_attributes,
but without copying st_other. If a function symbol has special st_other
value set via directives, then attaching an IFUNC resolver to that symbol
should not override the st_other setting.
(riscv_pseudo_table): Support variant_cc diretive.
* config/tc-riscv.h (OBJ_COPY_SYMBOL_ATTRIBUTES): Defined.
* testsuite/gas/riscv/variant_cc-set.d: New testcase.
* testsuite/gas/riscv/variant_cc-set.s: Likewise.
* testsuite/gas/riscv/variant_cc.d: Likewise.
* testsuite/gas/riscv/variant_cc.s: Likewise.
include/
* elf/riscv.h (DT_RISCV_VARIANT_CC): Defined to (DT_LOPROC + 1).
(STO_RISCV_VARIANT_CC): Defined to 0x80.
ld/
* testsuite/ld-riscv-elf/variant_cc-1.s: New testcase.
* testsuite/ld-riscv-elf/variant_cc-2.s: Likewise.
* testsuite/ld-riscv-elf/variant_cc-now.d: Likewise.
* testsuite/ld-riscv-elf/variant_cc-r.d: Likewise.
* testsuite/ld-riscv-elf/variant_cc-shared.d: Likewise.
* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
Reuse float instructions in INSN_CLASS_F/D/Q, use riscv_subset_supports to
verify if z*inx enabled and use gpr instead of fpr when z*inx is enable.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Added support for
z*inx extension.
gas/ChangeLog:
* config/tc-riscv.c (riscv_ip): Added register choice for z*inx.
include/ChangeLog:
* opcode/riscv.h (enum riscv_insn_class): Reused INSN_CLASS_* for z*inx.
opcodes/ChangeLog:
* riscv-dis.c (riscv_disassemble_insn): Added disassemble check for
z*inx.
* riscv-opc.c: Reused INSN_CLASS_* for z*inx.
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Minimal support for zfinx, zdinx, zqinx. Like f/d/q, the zqinx
imply zdinx and zdinx imply zfinx, where zfinx are not compatible
with f/d/q.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_implicit_subsets): Added implicit rules
for z*inx extensions.
(riscv_supported_std_z_ext): Added entries for z*inx.
(riscv_parse_check_conflicts): Added conflict check for z*inx.
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
PR 28452
bfd * elf.c (assign_file_positions_for_non_load_sections): Replace
assertion with a warning message.
ld * ldgram.y: Add support for PT_GNU_RELRO and PT_GNU_PROPERTY.
* ldgram.c: Regenerate.
2021-11-17 Jim Wilson <jimw@sifive.com>
Kito Cheng <kito.cheng@sifive.com>
Nelson Chu <nelson.chu@sifive.com>
This patch is porting from the following riscv github,
https://github.com/riscv/riscv-binutils-gdb/tree/rvv-1.0.x
And here is the vector spec,
https://github.com/riscv/riscv-v-spec
bfd/
* elfxx-riscv.c (riscv_implicit_subsets): Added imply rules
of v, zve and zvl extensions.
(riscv_supported_std_ext): Updated verison of v to 1.0.
(riscv_supported_std_z_ext): Added zve and zvl extensions.
(riscv_parse_check_conflicts): The zvl extensions need to
enable either v or zve extension.
(riscv_multi_subset_supports): Check the subset list to know
if the INSN_CLASS_V and INSN_CLASS_ZVEF instructions are supported.
gas/
* config/tc-riscv.c (enum riscv_csr_class): Added CSR_CLASS_V.
(enum reg_class): Added RCLASS_VECR and RCLASS_VECM.
(validate_riscv_insn): Check whether the rvv operands are valid.
(md_begin): Initialize register hash for rvv registers.
(macro_build): Added rvv operands when expanding rvv pseudoes.
(vector_macro): Expand rvv macros into one or more instructions.
(macro): Likewise.
(my_getVsetvliExpression): Similar to my_getVsetvliExpression,
but used for parsing vsetvli operands.
(riscv_ip): Parse and encode rvv operands. Besides, The rvv loads
and stores with EEW 64 cannot be used when zve32x is enabled.
* testsuite/gas/riscv/priv-reg-fail-version-1p10.d: Updated -march
to rv32ifv_zkr.
* testsuite/gas/riscv/priv-reg-fail-version-1p11.d: Likewise.
* testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d: Likewise.
* testsuite/gas/riscv/priv-reg.s: Added rvv csr testcases.
* testsuite/gas/riscv/priv-reg-version-1p10.d: Likewise.
* testsuite/gas/riscv/priv-reg-version-1p11.d: Likewise.
* testsuite/gas/riscv/priv-reg-version-1p9p1.d: Likewise.
* testsuite/gas/riscv/march-imply-v.d: New testcase.
* testsuite/gas/riscv/vector-insns-fail-zve32xf.d: Likewise.
* testsuite/gas/riscv/vector-insns-fail-zve32xf.l: Likewise.
* testsuite/gas/riscv/vector-insns-fail-zvl.d: Likewise.
* testsuite/gas/riscv/vector-insns-fail-zvl.l: Likewise.
* testsuite/gas/riscv/vector-insns-vmsgtvx.d: Likewise.
* testsuite/gas/riscv/vector-insns-vmsgtvx.s: Likewise.
* testsuite/gas/riscv/vector-insns-zero-imm.d: Likewise.
* testsuite/gas/riscv/vector-insns-zero-imm.s: Likewise.
* testsuite/gas/riscv/vector-insns.d: Likewise.
* testsuite/gas/riscv/vector-insns.s: Likewise.
include/
* opcode/riscv-opc.h: Defined mask/match encodings and csrs for rvv.
* opcode/riscv.h: Defined rvv immediate encodings and fields.
(enum riscv_insn_class): Added INSN_CLASS_V and INSN_CLASS_ZVEF.
(INSN_V_EEW64): Defined.
(M_VMSGE, M_VMSGEU): Added for the rvv pseudoes.
opcodes/
* riscv-dis.c (print_insn_args): Dump the rvv operands.
* riscv-opc.c (riscv_vecr_names_numeric): Defined rvv registers.
(riscv_vecm_names_numeric): Likewise.
(riscv_vsew): Likewise.
(riscv_vlmul): Likewise.
(riscv_vta): Likewise.
(riscv_vma): Likewise.
(match_vs1_eq_vs2): Added for rvv Vu operand.
(match_vd_eq_vs1_eq_vs2): Added for rvv Vv operand.
(riscv_opcodes): Added rvv v1.0 instructions.
Add instructions in k-ext, some instruction in zbkb, zbkc is reuse from
zbb,zbc, we just change the class attribute to make them both support.
The 'aes64ks1i' and 'aes64ks2' instructions are present in both the Zknd
and Zkne extensions on rv64. Add new operand letter 'y' to present 'bs'
symbol and 'Y' to present 'rnum' symbolc for zkn instructions. Also add
a new Entropy Source CSR define 'seed' located at address 0x015.
bfd/
* elfxx-riscv.c (riscv_multi_subset_supports): Added support for
crypto extension.
gas/
*config/tc-riscv.c (enum riscv_csr_class): Added CSR_CLASS_ZKR.
(riscv_csr_address): Checked for CSR_CLASS_ZKR.
(validate_riscv_insn): Added y and Y for bs and rnum operands.
(riscv_ip): Handle y and Y operands.
include/
* opcode/riscv-opc.h: Added encodings of crypto instructions.
Also defined new csr seed, which address is 0x15.
* opcode/riscv.h: Defined OP_* and INSN_CLASS_* for crypto.
opcodes/
* riscv-dis.c (print_insn_args): Recognized new y and Y operands.
* riscv-opc.c (riscv_opcodes): Added crypto instructions.
Minimal support of scalar crypto extension, add "k" in the
riscv_supported_std_ext, to make the order check right with
"zk" behind "zb".
bfd/
* elfxx-riscv.c (riscv_implicit_subsets): Added implicit
rules for zk* extensions.
(riscv_supported_std_ext): Added entry for k.
(riscv_supported_std_z_ext): Added entries for zk*.
Commit e86fc4a5bc ("PR 28447: implement multiple parameters for .file
on XCOFF") introduces C_FILE entries which can store additional
information.
However, some modifications are needed by them but not by the original
C_FILE entries, usually representing the filename.
This patch ensures that filename entries are kept as is, in order to
protect targets not supporting the additional entries.
* coffgen.c (coff_write_symbol): Protect filename entries
(coff_write_symbols): Likewise.
(coff_print_symbol): Likewise.
R_PPC64_REL24_P9NOTOC is a variant of R_PPC64_REL24_NOTOC for use on
@notoc cals from non-power10 code in the rare case that using such a
construct is useful. R_PPC64_REL24_P9NOTOC will be emitted by gas
rather than R_PPC64_REL24_NOTOC when @notoc is used in a branch
instruction if power10 instructions are not enabled at that point.
The new relocation tells the linker to not use power10 instructions on
any stub emitted for that branch, unless overridden by
--power10-stubs=yes.
The current linker heuristic of only generating power10 instructions
for stubs if power10-only relocations are detected, continues to be
used.
include/
* elf/ppc64.h (R_PPC64_REL24_P9NOTOC): Define.
bfd/
* reloc.c (BFD_RELOC_PPC64_REL24_P9NOTOC): Define.
* elf64-ppc.c (ppc64_elf_howto_raw): Add entry for new reloc.
(ppc64_elf_reloc_type_lookup): Handle it.
(enum ppc_stub_type): Delete.
(enum ppc_stub_main_type, ppc_stub_sub_type): New.
(struct ppc_stub_type): New.
(struct ppc_stub_hash_entry): Use the above new type.
(struct ppc_link_hash_table): Update stub_count.
(is_branch_reloc, ppc64_elf_check_relocs),
(toc_adjusting_stub_needed): Handle new reloc.
(stub_hash_newfunc, select_alt_stub, ppc_merge_stub),
(ppc_type_of_stub, plt_stub_size, build_plt_stub),
(build_tls_get_addr_head, build_tls_get_addr_tail),
(ppc_build_one_stub, ppc_size_one_stub, ppc64_elf_size_stubs),
(ppc64_elf_build_stubs, ppc64_elf_relocate_section): Handle new
reloc. Modify stub handling to suit new scheme.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
gas/
* config/tc-ppc.c (ppc_elf_suffix): When power10 is not enabled
return BFD_RELOC_PPC64_REL24_P9NOTOC for @notoc.
(fixup_size, ppc_force_relocation, ppc_fix_adjustable): Handle
BFD_RELOC_PPC64_REL24_P9NOTOC.
ld/
* testsuite/ld-powerpc/callstub-2.s: Add .machine power10.
For now we should always generate the elf architecture attribute both for
elf and linux toolchains, so that we could dump the objects correctly
according to the generated architecture string. This patch resolves the
problem that we probably dump an object with c.nop instructions, but
in fact the c extension isn't allowed. Consider the following case,
nelson@LAPTOP-QFSGI1F2:~/test$ cat temp.s
.option norvc
.option norelax
.text
add a0, a0, a0
.byte 0x1
.balign 16
nelson@LAPTOP-QFSGI1F2:~/test$ ~/binutils-dev/build-elf32-upstream/build-install/bin/riscv32-unknown-elf-as temp.s -o temp.o
nelson@LAPTOP-QFSGI1F2:~/test$ ~/binutils-dev/build-elf32-upstream/build-install/bin/riscv32-unknown-elf-objdump -d temp.o
temp.o: file format elf32-littleriscv
Disassembly of section .text:
00000000 <.text>:
0: 00a50533 add a0,a0,a0
4: 01 .byte 0x01
5: 00 .byte 0x00
6: 0001 nop
8: 00000013 nop
c: 00000013 nop
nelson@LAPTOP-QFSGI1F2:~/test$ ~/binutils-dev/build-elf32-upstream/build-install/bin/riscv32-unknown-elf-readelf -A temp.o
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0"
The c.nop at address 0x6 is generated for alignment, but since the rvc isn't
allowed for this object, dump it as a c.nop instruction looks wrong. After
applying this patch, I get the following result,
nelson@LAPTOP-QFSGI1F2:~/test$ ~/binutils-dev/build-elf32-upstream/build-install/bin/riscv32-unknown-elf-objdump -d temp.o
temp.o: file format elf32-littleriscv
Disassembly of section .text:
00000000 <.text>:
0: 00a50533 add a0,a0,a0
4: 01 .byte 0x01
5: 00 .byte 0x00
6: 0001 .2byte 0x1
8: 00000013 nop
c: 00000013 nop
For the current objdump, we dump data to .byte/.short/.word/.dword, and
dump the unknown or unsupported instructions to .2byte/.4byte/.8byte, which
respectively are 2, 4 and 8 bytes instructions. Therefore, we shouldn't
dump the 0x0001 as a c.nop instruction in the above case, we should dump
it to .2byte 0x1 as a unknown instruction, since the rvc is disabled.
However, consider that some people may use the new objdump to dump the old
objects, which don't have any elf attributes. We usually set the default
architecture string to rv64g by bfd/elfxx-riscv.c:riscv_set_default_arch.
But this will cause rvc instructions to be unrecognized. Therefore, we
set the default architecture string to rv64gc for disassembler, to keep
the previous behavior.
This patch pass the riscv-gnu-toolchain gcc/binutils regressions for
rv32emc-elf, rv32gc-linux, rv32i-elf, rv64gc-elf and rv64gc-linux
toolchains. Also, tested by --enable-targets=all and can build
riscv-gdb successfully.
bfd/
* elfnn-riscv.c (riscv_merge_arch_attr_info): Tidy the
codes for riscv_parse_subset_t setting.
* elfxx-riscv.c (riscv_get_default_ext_version): Updated.
(riscv_subset_supports): Moved from gas/config/tc-riscv.c.
(riscv_multi_subset_supports): Likewise.
* elfxx-riscv.h: Added extern for riscv_subset_supports and
riscv_multi_subset_supports.
gas/
* config/tc-riscv.c (riscv_subset_supports): Moved to
bfd/elfxx-riscv.c.
(riscv_multi_subset_supports): Likewise.
(riscv_rps_as): Defined for architectrue parser.
(riscv_set_arch): Updated.
(riscv_set_abi_by_arch): Likewise.
(riscv_csr_address): Likewise.
(reg_lookup_internal): Likewise.
(riscv_ip): Likewise.
(s_riscv_option): Updated.
* testsuite/gas/riscv/mapping-04b.d: Updated.
* testsuite/gas/riscv/mapping-norelax-03b.d: Likewise.
* testsuite/gas/riscv/mapping-norelax-04b.d: Likewise.
opcodes/
* riscv-dis.c: Include elfxx-riscv.h since we need the
architecture parser. Also removed the cpu-riscv.h, it
is already included in elfxx-riscv.h.
(default_isa_spec): Defined since the parser need this
to set the default architecture string.
(xlen): Moved out from riscv_disassemble_insn as a global
variable, it is more convenient to initialize riscv_rps_dis.
(riscv_subsets): Defined to recoed the supported
extensions.
(riscv_rps_dis): Defined for architectrue parser.
(riscv_disassemble_insn): Call riscv_multi_subset_supports
to make sure if the instructions are valid or not.
(print_insn_riscv): Initialize the riscv_subsets by parsing
the elf architectrue attribute. Otherwise, set the default
architectrue string to rv64gc.
This patch is adding support for Cortex-A710 CPU in Arm.
bfd/
* cpu-arm.c (processors): Add cortex-a710.
gas/
* NEWS: Update docs.
* config/tc-arm.c (arm_cpus): Add cortex-a710 to -mcpu.
* doc/c-arm.texi: Update docs.
* testsuite/gas/arm/cpu-cortex-a710.d: New test.
This one was logically wrong too. If file_ptr was 64 bits, then -1U
is extended to 0x00000000ffffffff, probably not what was intended
here.
* mach-o.c (FILE_ALIGN): Correct expression.
