Fix commit e407c74b5b ("Support for MIPS R5900 (Sony Playstation 2)"),
<https://sourceware.org/ml/binutils/2012-12/msg00240.html>, and add the
handling of E_MIPS_MACH_5900, correctly showing `5900' among `Flags:' in
the output of `-h' rather than `unknown CPU'.
binutils/
* readelf.c (get_machine_flags) <E_MIPS_MACH_5900>: New case.
gas/
* testsuite/gas/mips/elf_mach_5900.d: New test.
* testsuite/gas/mips/mips.exp: Run it.
If a .stabs directive was used before another .set directive in a MIPS
source file, s_mips_stab would call mips_mark_labels without having
initialized the mips_opts structure yet. Fix this by calling
file_mips_check_options which will initialize mips_opts if necessary.
gas/
PR gas/21762
* config/tc-mips.c (s_mips_stab): Insert call to
file_mips_check_options.
* testsuite/gas/mips/micromips@stabs-symbol-type.d: New test.
* testsuite/gas/mips/mips.exp: Run the new tests.
* testsuite/gas/mips/mips16@stabs-symbol-type.d: New test.
* testsuite/gas/mips/stabs-symbol-type.d: New test.
* testsuite/gas/mips/stabs-symbol-type.s: New test source.
Since the NOTRACK prefix is no longer required to be the last prefix
before the REX prefix, restriction on the NOTRACK prefix position is
removed from assembler as well as disassembler. Assembler encodes the
NOTRACK prefix the same way as the DS segment register, which places
it before other prefixes. Disassembler displays prefixes in the order
they appear.
gas/
* config/tc-i386.c (NOTRACK_PREFIX): Removed.
(REX_PREFIX): Updated.
(MAX_PREFIXES): Likewise.
(parse_insn): Remove restriction on NOTRACK prefix position.
* testsuite/gas/i386/notrack.s: Add tests with NOTRACK prefix
before other prefixes.
* testsuite/gas/i386/x86-64-notrack.s: Likewise.
* testsuite/gas/i386/notrackbad.s: Remove tests with NOTRACK
prefix before other prefixes.
* testsuite/gas/i386/x86-64-notrackbad.s: Likewise.
* testsuite/gas/i386/notrack-intel.d: Updated.
* testsuite/gas/i386/notrack.d: Likewise.
* testsuite/gas/i386/notrackbad.l: Likewise.
* testsuite/gas/i386/x86-64-notrack-intel.d: Likewise.
* testsuite/gas/i386/x86-64-notrack.d: Likewise.
* testsuite/gas/i386/x86-64-notrackbad.l: Likewise.
opcodes/
* i386-dis.c (last_active_prefix): Removed.
(ckprefix): Don't set last_active_prefix.
(NOTRACK_Fixup): Don't check last_active_prefix.
Fix a bug in commit a6ebf6169a ("MIPS: Convert cross-mode BAL to
JALX") and in BFD linker relaxation correct the microMIPS interpretation
of the branch offset, which is supposed to be shifted by 1 bit, rather
than 2 as in the regular MIPS case.
bfd/
* elfxx-mips.c (mips_elf_perform_relocation): Correct microMIPS
branch offset interpretation.
gas/
* testsuite/gas/mips/branch-addend-micromips.d: New test.
* testsuite/gas/mips/branch-addend-micromips-n32.d: New test.
* testsuite/gas/mips/branch-addend-micromips-n64.d: New test.
* testsuite/gas/mips/branch-addend-micromips.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
ld/
* testsuite/ld-mips-elf/bal-jalx-addend-micromips.d: New test.
* testsuite/ld-mips-elf/bal-jalx-addend-micromips-n32.d: New
test.
* testsuite/ld-mips-elf/bal-jalx-addend-micromips-n64.d: New
test.
* testsuite/ld-mips-elf/bal-jalx-local-micromips.d: New test.
* testsuite/ld-mips-elf/bal-jalx-local-micromips-n32.d: New
test.
* testsuite/ld-mips-elf/bal-jalx-local-micromips-n64.d: New
test.
* testsuite/ld-mips-elf/bal-jalx-pic-micromips.d: New test.
* testsuite/ld-mips-elf/bal-jalx-pic-micromips-n32.d: New test.
* testsuite/ld-mips-elf/bal-jalx-pic-micromips-n64.d: New test.
* testsuite/ld-mips-elf/bal-jalx-pic-ignore-micromips.d: New
test.
* testsuite/ld-mips-elf/bal-jalx-pic-ignore-micromips-n32.d: New
test.
* testsuite/ld-mips-elf/bal-jalx-pic-ignore-micromips-n64.d: New
test.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
Fix a bug in commit 8b10b0b3e1 ("MIPS: Add options to control branch
ISA checks") and with the `-mignore-branch-isa' command-line option also
lift a GAS check for invalid MIPS16 branches between ISA modes, which is
made separately from regular MIPS and microMIPS checks.
gas/
* config/tc-mips.c (md_convert_frag): Respect
`mips_ignore_branch_isa'.
* testsuite/gas/mips/branch-local-5.d: New test.
* testsuite/gas/mips/branch-local-n32-5.d: New test.
* testsuite/gas/mips/branch-local-n64-5.d: New test.
* testsuite/gas/mips/branch-local-6.d: New test.
* testsuite/gas/mips/branch-local-n32-6.d: New test.
* testsuite/gas/mips/branch-local-n64-6.d: New test.
* testsuite/gas/mips/branch-local-7.d: New test.
* testsuite/gas/mips/branch-local-n32-7.d: New test.
* testsuite/gas/mips/branch-local-n64-7.d: New test.
* testsuite/gas/mips/branch-local-ignore-5.d: New test.
* testsuite/gas/mips/branch-local-ignore-n32-5.d: New test.
* testsuite/gas/mips/branch-local-ignore-n64-5.d: New test.
* testsuite/gas/mips/branch-local-ignore-6.d: New test.
* testsuite/gas/mips/branch-local-ignore-n32-6.d: New test.
* testsuite/gas/mips/branch-local-ignore-n64-6.d: New test.
* testsuite/gas/mips/branch-local-5.l: New stderr output.
* testsuite/gas/mips/branch-local-6.l: New stderr output.
* testsuite/gas/mips/branch-local-5.s: New test source.
* testsuite/gas/mips/branch-local-6.s: New test source.
* testsuite/gas/mips/branch-local-7.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
We got a report from the linux-arm-kernel folks about getting spurious
warnings when building the kernel with binutils 2.29. See
https://www.spinics.net/lists/arm-kernel/msg599929.html
which boils down to this testcase.
$> cat /tmp/tst.s
lr .req x30
/tmp/tst.s: Assembler messages:
/tmp/tst.s:1: Warning: ignoring attempt to redefine built-in register 'lr'
Instead let's treat this as a proper alias at startup time thus
avoiding the problem and treating these as proper aliases
rather than new registers. This means that attempts to redefine
the alias with the same "name" will provoke no warning and attempts
to redefine the alias to something else will provoke the above mentioned
warning.
Tested make check-gas and no regressions.
Ok to apply to trunk (and backport to 2.29 branch)?
Regards
Ramana
We can't create alias of common symbol. Local alias of common symbol has
been disallowed. But global alias of common symbol is disallowed when the
common symbol is seen first and silently dropped otherwise. This patch
disallows alias of common symbol in all cases.
gas/
PR gas/21667
* read.c (pseudo_set): Update error message for alias of common
symbol.
* write.c (write_object_file): Disallow both local and global
aliases of common symbol.
* testsuite/gas/elf/common5a.d: New file.
* testsuite/gas/elf/common5a.l: Likewise.
* testsuite/gas/elf/common5a.s: Likewise.
* testsuite/gas/elf/common5b.d: Likewise.
* testsuite/gas/elf/common5b.l: Likewise.
* testsuite/gas/elf/common5b.s: Likewise.
* testsuite/gas/elf/common5c.d: Likewise.
* testsuite/gas/elf/common5c.s: Likewise.
* testsuite/gas/elf/common5d.d: Likewise.
* testsuite/gas/elf/common5d.s: Likewise.
* testsuite/gas/elf/elf.exp: Run common5a, common5b, common5c
and common5d.
According to ARMv8-A architecture manual, REG_SP is allowed in CRC32
instructions in Thumb mode. It is REG_PC that will cause unpredictable
behaviours on both ARM and Thumb.
This patch removes the incorrect warning on Thumb mode.
Meanwhile the disassembler is updated to use format "<bitfield>R" instead of
"<bitfield>S". "<bitfield>S" is not used elsewhere. so I have deleted related
code from the disassembler.
gas/
* config/tc-arm.c (do_crc32_1): Remove warning on REG_SP for thumb_mode.
* testsuite/gas/arm/crc32-armv8-a-bad.d: Update exepcted result.
* testsuite/gas/arm/crc32-armv8-r-bad.d: Likewise.
* testsuite/gas/arm/crc32-armv8-a.d: Likewise.
* testsuite/gas/arm/crc32-armv8-r.d: Likewise.
* testsuite/gas/arm/crc32-armv8-ar-bad.s: Update test case.
* testsuite/gas/arm/crc32-armv8-ar.s: Likewise.
* testsuite/gas/arm/crc32-bad.l: Update expected error message.
opcode/
* arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
register operands in CRC instructions.
(print_insn_thumb32): Remove "<bitfield>S" support. Updated the
comments.
The following relocation types were added to GCC/binutils:
ARC_JLI_SECTOFF is a relocation type in Metaware that is now used by
GCC as well to adjust the index of function calls to functions with
attribute jli_call_always.
bfd/
2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
John Eric Martin <John.Martin@emmicro-us.com>
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* elf32-arc.c (JLI): Define.
* reloc.c: Add JLI relocations.
gas/
2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/jli-1.d: New file.
* testsuite/gas/arc/jli-1.s: Likewise.
* testsuite/gas/arc/taux.d: Update for jli_base.
include/
2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
John Eric Martin <John.Martin@emmicro-us.com>
* elf/arc-reloc.def: Add JLI relocs howto.
* opcode/arc-func.h (replace_jli): New function.
ld/
2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
John Eric Martin <John.Martin@emmicro-us.com>
* emulparams/arcelf.sh (JLI_START_TABLE): Define.
* scripttempl/elfarc.sc: Handle jlitab section.
* scripttempl/elfarcv2.sc: Likewise.
* testsuite/ld-arc/arc.exp: Add JLI test.
* testsuite/ld-arc/jli-script.ld: New file.
* testsuite/ld-arc/jli-simple.dd: Likewise.
* testsuite/ld-arc/jli-simple.rd: Likewise.
* testsuite/ld-arc/jli-simple.s: Likewise.
* testsuite/ld/testsuite/ld-arc/jli-overflow.s: Likewise.
* testsuite/ld/testsuite/ld-arc/jli-overflow.d: Likewise.
* testsuite/ld/testsuite/ld-arc/jli-overflow.err: Likewise.
opcode/
2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
John Eric Martin <John.Martin@emmicro-us.com>
* arc-opc.c (UIMM10_6_S_JLIOFF): Define.
(UIMM3_23): Adjust accordingly.
* arc-regs.h: Add/correct jli_base register.
* arc-tbl.h (jli_s): Likewise.
The instructions are not documented in the Intel SDM but are documented
in the AMD APM as an alias to the group 2, ModRM.reg == 4 variant.
Both AMD and Intel CPUs execute the C[0-1] and D[0-3] instructions as
expected, i.e., like the /4 aliases:
#include <stdio.h>
int main(void)
{
int a = 2;
printf ("a before: %d\n", a);
asm volatile(".byte 0xd0,0xf0" /* SHL %al */
: "+a" (a));
printf("a after : %d\n", a);
return 0;
}
$ ./a.out
a before: 2
a after : 4
This patch adds support mvfr2 control registers for armv8-a as
this was missed from the original port to armv8-a (documented
at G6.2.109 in (Issue B.a) of the ARM-ARM. This was discovered
by an internal user of the GNU toolchain.
I'd like to backport this to the binutils 2.28 and binutils 2.29
release branch if possible (with suitable testing and basically
checking removing the armv8-r parts).
Tristan - are you ok with the backports ?
Applied to trunk.
regards Ramana
2017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* gas/config/tc-arm.c (arm_regs): Add MVFR2.
(do_vmrs): Constraint for MVFR2 and armv8.
(do_vmsr): Likewise.
* gas/testsuite/gas/arm/armv8-a+fp.d: Update.
* gas/testsuite/gas/arm/armv8-ar+fp.s: Likewise.
* gas/testsuite/gas/arm/armv8-r+fp.d: Likewise.
* gas/testsuite/gas/arm/vfp-bad.s: Likewise.
* gas/testsuite/gas/arm/vfp-bad.l: Likewise.
* opcodes/arm-dis.c: Support MVFR2 in disassembly
with vmrs and vmsr.
Use frag symbols with a non-zero offset directly in `fix_new_exp' calls
made in PIC branch relaxation. There is no need here to make a helper
symbol to hold the result of a `symbol+offset' calculation requested as
only branches to local symbols are relaxed and in this case the LO16
part of the PIC address load sequence will have the offset accounted for
in calculation against the local GOT entry retrieved as the GOT16 high
part. Consequently actual code produed is identical whether a helper
symbol is used or the original `symbol+offset' expression used directly.
Verify that this is indeed the case with GAS and LD tests.
gas/
* config/tc-mips.c (md_convert_frag): Don't make a helper
expression symbol for `fix_new_exp' called with a non-zero
offset.
* testsuite/gas/mips/relax-offset.d: New test.
* testsuite/gas/mips/mips1@relax-offset.d: New test.
* testsuite/gas/mips/r3000@relax-offset.d: New test.
* testsuite/gas/mips/r3900@relax-offset.d: New test.
* testsuite/gas/mips/micromips@relax-offset.d: New test.
* testsuite/gas/mips/relax-offset.l: New stderr output.
* testsuite/gas/mips/relax-offset.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
ld/
* testsuite/ld-mips-elf/relax-offset.dd: New test.
* testsuite/ld-mips-elf/relax-offset.gd: New test.
* testsuite/ld-mips-elf/relax-offset-umips.dd: New test.
* testsuite/ld-mips-elf/relax-offset-umips.gd: New test.
* testsuite/ld-mips-elf/relax-offset.ld: New test linker script.
* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
(prune_warnings): New temporary procedure.
PR gas/21683
include * opcode/avr.h (AVR_INSN): Add one for __gcc_isr.
gas * doc/c-avr.texi (AVR Options) <-mgcc-isr>: Document it.
(AVR Pseudo Instructions): New node.
* config/tc-avr.h (md_pre_output_hook): Define to avr_pre_output_hook.
(md_undefined_symbol): Define to avr_undefined_symbol.
(avr_pre_output_hook, avr_undefined_symbol): New protos.
* config/tc-avr.c (struc-symbol.h): Include it.
(ISR_CHUNK_Done, ISR_CHUNK_Prologue, ISR_CHUNK_Epilogue): New enums.
(avr_isr, avr_gccisr_opcode)
(avr_no_sreg_hash, avr_no_sreg): New static variables.
(avr_opt_s) <have_gccisr>: Add field.
(avr_opt): Add initializer for have_gccisr.
(enum options) <OPTION_HAVE_GCCISR>: Add enum.
(md_longopts) <"mgcc-isr">: Add entry.
(md_show_usage): Document -mgcc-isr.
(md_parse_option) [OPTION_HAVE_GCCISR]: Handle it.
(md_undefined_symbol): Remove.
(avr_undefined_symbol, avr_pre_output_hook): New fuctions.
(md_begin) <avr_no_sreg_hash, avr_gccisr_opcode>: Initialize them.
(avr_operand) <pregno>: Add argument and set *pregno if function
is called for a register constraint.
[N]: Handle constraint.
(avr_operands) <avr_operand>: Pass 5th parameter to calls.
[avr_opt.have_gccisr]: Call avr_update_gccisr. Call
avr_gccisr_operands instead of avr_operands.
(avr_update_gccisr, avr_emit_insn, avr_patch_gccisr_frag)
(avr_gccisr_operands, avr_check_gccisr_done): New static functions.
* testsuite/gas/avr/gccisr-01.d: New test.
* testsuite/gas/avr/gccisr-01.s: New test.
* testsuite/gas/avr/gccisr-02.d: New test.
* testsuite/gas/avr/gccisr-02.s: New test.
* testsuite/gas/avr/gccisr-03.d: New test.
* testsuite/gas/avr/gccisr-03.s: New test.
Add support for the base and Virtualization ASE microMIPS instructions
as per the architecture specifications[1][2][3][4].
Most of this change by Andrew Bennett.
[1] "MIPS Architecture for Programmers Volume II-B: The microMIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00582,
Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit
Instructions", p. 340
[2] "microMIPS32 Architecture for Programmers Volume IV-i:
Virtualization Module of the microMIPS32 Architecture", MIPS
Technologies, Inc., Document Number: MD00848, Revision 1.06,
December 10, 2013, Section 6.1 "Overview", pp. 133, 136
[3] "MIPS Architecture for Programmers Volume II-B: The microMIPS64
Instruction Set", MIPS Technologies, Inc., Document Number: MD00594,
Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit
Instructions", pp. 415, 444
[4] "microMIPS64 Architecture for Programmers Volume IV-i:
Virtualization Module of the microMIPS64 Architecture", MIPS
Technologies, Inc., Document Number: MD00849, Revision 1.06,
December 10, 2013, Section 6.1 "Overview", pp. 134-135, 139-140
binutils/
* NEWS: Mention microMIPS XPA support.
opcodes/
* micromips-opc.c (XPA, XPAVZ): New macros.
(micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
"mthgc0".
gas/
* config/tc-mips.c (mips_ases): Add microMIPS XPA support.
* testsuite/gas/mips/micromips@xpa.d: New test.
* testsuite/gas/mips/mips.exp: Run the new test. Enable
`xpa-virt-err' test for `micromips'.
Add base microMIPS Release 5 ISA support and the ERETNC instruction in
particular, as per the architecture specifications[1][2].
Most of this change by Andrew Bennett.
References:
[1] "MIPS Architecture for Programmers Volume II-B: The microMIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00582,
Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit
Instructions", pp. 266-267
[2] "MIPS Architecture for Programmers Volume II-B: The microMIPS64
Instruction Set", MIPS Technologies, Inc., Document Number: MD00594,
Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit
Instructions", pp. 326-327
binutils/
* NEWS: Mention microMIPS Release 5 ISA support.
opcodes/
* micromips-opc.c (I36): New macro.
(micromips_opcodes): Add "eretnc".
gas/
* testsuite/gas/mips/micromips@r5.d: New test.
* testsuite/gas/mips/mips.exp: Run the new test.
Correct a commit 7d64c587c1 ("Add support for the MIPS eXtended
Physical Address (XPA) ASE.") bug, causing XPA base and Virtualization
ASE instructions to be wrongly always enabled with the selection of the
MIPS32r2 or higher ISA.
For example this source assembles successfully as shown below:
$ cat xpa.s
mfhc0 $2, $1
$ as -32 -mips32 -o xpa.o xpa.s
xpa.s: Assembler messages:
xpa.s:1: Error: opcode not supported on this processor: mips32 (mips32) `mfhc0 $2,$1'
$ as -32 -mips32r2 -o xpa.o xpa.s
$ objdump -d xpa.o
xpa.o: file format elf32-tradbigmips
Disassembly of section .text:
00000000 <.text>:
0: 40420800 mfhc0 v0,c0_random
...
$
To address this issue remove the I33 (INSN_ISA32R2) marking from all XPA
instructions in the opcode table. Additionally, for XPA Virtualization
ASE instructions implement an XPAVZ (ASE_XPA_VIRT) combination ASE flag
and use it in place of IVIRT|XPA (ASE_VIRT|ASE_XPA).
Now the same source is correctly rejected unless the `-mxpa' option is
also used:
$ as -32 -mips32r2 -o xpa.o xpa.s
xpa.s: Assembler messages:
xpa.s:1: Error: opcode not supported on this processor: mips32r2 (mips32r2) `mfhc0 $2,$1'
$ as -32 -mips32r2 -mxpa -o xpa.o xpa.s
$
Add test cases for XPA base and XPA Virtualization ASE instructions.
Parts of this change by Andrew Bennett.
include/
* opcode/mips.h (ASE_XPA_VIRT): New macro.
opcodes/
* mips-dis.c (mips_calculate_combination_ases): Handle the
ASE_XPA_VIRT flag.
(parse_mips_ase_option): New function.
(parse_mips_dis_option): Factor out ASE option handling to the
new function. Call `mips_calculate_combination_ases'.
* mips-opc.c (XPAVZ): New macro.
(mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
"mfhgc0", "mthc0" and "mthgc0".
gas/
* config/tc-mips.c (mips_set_ase): Handle the ASE_XPA_VIRT flag.
* testsuite/gas/mips/xpa.d: Remove `xpa' from `-M' in `objdump'
flags. Add `-mvirt' to `as' flags.
* testsuite/gas/mips/xpa-err.d: New test.
* testsuite/gas/mips/xpa-virt-err.d: New test.
* testsuite/gas/mips/xpa-err.l: New stderr output.
* testsuite/gas/mips/xpa-virt-err.l: New stderr output.
* testsuite/gas/mips/xpa-err.s: New test source.
* testsuite/gas/mips/xpa-virt-err.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
binutils/
* testsuite/binutils-all/mips/mips-xpa-virt-1.d: New test.
* testsuite/binutils-all/mips/mips-xpa-virt-2.d: New test.
* testsuite/binutils-all/mips/mips-xpa-virt-3.d: New test.
* testsuite/binutils-all/mips/mips-xpa-virt-4.d: New test.
* testsuite/binutils-all/mips/mips-xpa-virt.s: New test source.
* testsuite/binutils-all/mips/mips.exp: Run the new tests.
Correct a commit 25499ac7ee ("MIPS16e2: Add MIPS16e2 ASE support")
disassembler bug with the handling of the ASE_MIPS16E2_MT combination
ASE flag, where the calculation uses MIPS ABI Flags directly rather than
calculated internal ASE flags. Consequently code does not correctly set
the ASE_MIPS16E2_MT flag when the MIPS16e2 ASE flag and the MT ASE flag
come from different sources, i.e. one from the BFD chosen and the other
one from MIPS ABI Flags.
Fix this by using internal ASE_MT and ASE_MIPS16E2 flags in a separate
subsequent step, factored out to a dedicated function for use with
future combination ASE flags. Adjust the `mips16e2@mips16e2-mt-sub.d'
test case accordingly, where the MT flag comes from the BFD selected for
the disassembler and the MIPS16e2 flag comes from the ELF binary itself.
opcodes/
* mips-dis.c (mips_calculate_combination_ases): New function.
(mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
calculation to the new function.
(set_default_mips_dis_options): Call the new function.
gas/
* testsuite/gas/mips/mips16e2@mips16e2-mt-sub.d: Adjust for the
ASE_MIPS16E2_MT flag disassembler fix.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e2-mt-sub.d:
Likewise.
Correct a commit 25499ac7ee ("MIPS16e2: Add MIPS16e2 ASE support") GAS
bug with the handling of the ASE_MIPS16E2_MT combination ASE flag, which
is not correctly calculated as `.set nomips16e2' and `.set nomt'
pseudo-ops are processed. This leads to code like:
$ cat foo.s
.set nomt
evpe
.align 4, 0
$ cat bar.s
.set nomips16e2
dvpe
.align 4, 0
$
to successfully assemble where it should not:
$ as -32 -mips32r3 -mmt -mips16 -mmips16e2 -o foo.o foo.s
$ as -32 -mips32r3 -mmt -mips16 -mmips16e2 -o bar.o bar.s
$ objdump -m mips:16 -d foo.o
foo.o: file format elf32-tradbigmips
Disassembly of section .text:
00000000 <.text>:
0: f027 6700 evpe
...
bar.o: file format elf32-tradbigmips
Disassembly of section .text:
00000000 <.text>:
0: f026 6700 dvpe
...
$
This happens because ASE_MIPS16E2_MT once set in `mips_set_ase' is never
cleared. Fix the problem by clearing it there before it is calculated
based on the ASE_MT and ASE_MIPS16E2 flags, making assembly fail as
expected:
$ as -32 -mips32r3 -mmt -mips16 -mmips16e2 -o foo.o foo.s
foo.s: Assembler messages:
foo.s:2: Error: opcode not supported on this processor: mips32r3 (mips32r3) `evpe'
$ as -32 -mips32r3 -mmt -mips16 -mmips16e2 -o bar.o bar.s
bar.s: Assembler messages:
bar.s:2: Error: opcode not supported on this processor: mips32r3 (mips32r3) `dvpe'
$
gas/
* config/tc-mips.c (mips_set_ase): Clear the ASE_MIPS16E2_MT
flag before recalculating.
* testsuite/gas/mips/mips16e2-mt-err.d: New test.
* testsuite/gas/mips/mips16e2-mt-err.l: New stderr output.
* testsuite/gas/mips/mips16e2-mt-err.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new test.
This patch add assembler and disassembler support for new Dot Product
Extension.
The support can be enabled through the new "+dotprod" extension.
include/
* opcode/arm.h (FPU_NEON_EXT_DOTPROD): New macro.
(FPU_ARCH_DOTPROD_NEON_VFP_ARMV8): New macro.
gas/
* config/tc-arm.c (fpu_neon_ext_dotprod): New variable.
(neon_scalar_for_mul): Improve comments.
(do_neon_dotproduct): New function to encode Dot Product instructions.
(do_neon_dotproduct_s): Wrapper function for signed Dot Product
instructions.
(do_neon_dotproduct_u): Wrapper function for unsigned Dot Product
instructions.
(insns): New entries for vsdot and vudot.
(arm_extensions): New entry for "dotprod".
* doc/c-arm.texi: Document new "dotprod" extension.
* testsuite/gas/arm/dotprod.s: New test source.
* testsuite/gas/arm/dotprod-illegal.s: New test source.
* testsuite/gas/arm/dotprod.d: New test.
* testsuite/gas/arm/dotprod-thumb2.d: New test.
* testsuite/gas/arm/dotprod-illegal.d: New test.
* testsuite/gas/arm/dotprod-legacy-arch.d: New test.
* testsuite/gas/arm/dotprod-illegal.l: New error file.
* testsuite/gas/arm/dotprod-legacy-arch.l: New error file.
opcodes/
* arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
Add GAS tests to verify Imagination interAptiv MR2 instruction assembly,
disassembly and ELF object file flags.
Add LD tests to verify Imagination interAptiv MR2 ELF object file
link-time compatibility and flag merging/propagation. Use the framework
enhancement added with commit 7575e6a752 ("MIPS/LD/testsuite:
mips-elf-flags: Add MIPS ABI Flags handling").
gas/
* testsuite/gas/mips/elf_mach_interaptiv-mr2.d: New test.
* testsuite/gas/mips/save-err.d: New test.
* testsuite/gas/mips/save-sub.d: New test.
* testsuite/gas/mips/interaptiv-mr2@save.d: New test.
* testsuite/gas/mips/mips1@save-sub.d: New test.
* testsuite/gas/mips/mips2@save-sub.d: New test.
* testsuite/gas/mips/mips3@save-sub.d: New test.
* testsuite/gas/mips/mips4@save-sub.d: New test.
* testsuite/gas/mips/mips5@save-sub.d: New test.
* testsuite/gas/mips/mips32@save-sub.d: New test.
* testsuite/gas/mips/mips64@save-sub.d: New test.
* testsuite/gas/mips/mips16@save-sub.d: New test.
* testsuite/gas/mips/mips16e@save-sub.d: New test.
* testsuite/gas/mips/r3000@save-sub.d: New test.
* testsuite/gas/mips/r3900@save-sub.d: New test.
* testsuite/gas/mips/r4000@save-sub.d: New test.
* testsuite/gas/mips/vr5400@save-sub.d: New test.
* testsuite/gas/mips/interaptiv-mr2@save-sub.d: New test.
* testsuite/gas/mips/sb1@save-sub.d: New test.
* testsuite/gas/mips/octeon2@save-sub.d: New test.
* testsuite/gas/mips/octeon3@save-sub.d: New test.
* testsuite/gas/mips/xlr@save-sub.d: New test.
* testsuite/gas/mips/r5900@save-sub.d: New test.
* testsuite/gas/mips/mips16e2-copy.d: New test.
* testsuite/gas/mips/mips16e2-copy-err.d: New test.
* testsuite/gas/mips/save.d: Remove `MIPS16e' from the `name'
option. Adjust for trailing padding change.
* testsuite/gas/mips/mips16e2-copy-err.l: New stderr output.
* testsuite/gas/mips/save-sub.s: New test source.
* testsuite/gas/mips/mips16e2-copy.s: New test source.
* testsuite/gas/mips/mips16e2-copy-err.s: New test source.
* testsuite/gas/mips/save.s: Update description, change trailing
padding and remove trailing white space.
* testsuite/gas/mips/mips.exp: Expand `save' and `save-err'
tests across the regular MIPS interAptiv MR2 architecture. Run
the new tests.
ld/
* testsuite/ld-mips-elf/mips-elf-flags.exp: Add interAptiv MR2
tests.
Define a new regular MIPS and MIPS16 interAptiv MR2 test architecture
and adjust existing tests now run against these architectures
accordingly.
This change causes new test failures:
FAIL: MIPS jal-svr4pic (interaptiv-mr2)
FAIL: MIPS jal-svr4pic noreorder (interaptiv-mr2)
with the `mips-sgi-irix5' and `mips-sgi-irix6' targets, which are
consistent with the remaining architecture results for these cases, that
do not take into account the lack of R_MIPS_JALR relocations produced by
GAS for these targets. As a preexisting issue these failures are not
addressed with this change.
gas/
* testsuite/gas/mips/mips.exp (interaptiv-mr2): New architecture.
(mips16e2-interaptiv-mr2): Likewise.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro.d: New
test.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro-t.d:
New test.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro-e.d:
New test.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-insn-t.d:
New test.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-insn-e.d:
New test.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e-64.d: New
test.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-sub.d: New
test.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e-sub.d: New
test.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e-64-sub.d:
New test.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e2-mt-sub.d:
New test.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-asmacro.d:
New test.
* testsuite/gas/mips/interaptiv-mr2@mcu.d: New test.
* testsuite/gas/mips/interaptiv-mr2@isa-override-1.d: New test.
* testsuite/gas/mips/interaptiv-mr2@isa-override-2.d: New test.
* testsuite/gas/mips/attr-gnu-4-5.d: Ignore any number of ASE
flag lines present rather than just one.
* testsuite/gas/mips/attr-gnu-4-6.d: Likewise.
* testsuite/gas/mips/attr-gnu-4-7.d: Likewise.
* testsuite/gas/mips/attr-none-o32-fp64-nooddspreg.d: Likewise.
* testsuite/gas/mips/attr-none-o32-fp64.d: Likewise.
* testsuite/gas/mips/attr-none-o32-fpxx.d: Likewise.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro.l: New
stderr output.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro-t.l:
New stderr output.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-macro-e.l:
New stderr output.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-insn-t.l:
New stderr output.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-insn-e.l:
New stderr output.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16-sub.l: New
stderr output.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e-sub.l: New
stderr output.
* testsuite/gas/mips/mips16e2-interaptiv-mr2@mips16e-64-sub.l:
New stderr output.
* testsuite/gas/mips/interaptiv-mr2@isa-override-1.l: New stderr
output.
* testsuite/gas/mips/interaptiv-mr2@isa-override-2.l: New stderr
output.
The .symver directive on common symbol creates a new common symbol,
which shouldn't be allowed, similar to alias on common symbol:
$ cat y.S
.comm bar,8,8
.set bar1,bar
$ as -o y.o y.S
y.S: Assembler messages:
y.S:2: Error: `bar1' can't be equated to common symbol 'bar'
$
PR gas/21661
* config/obj-elf.c (obj_elf_symver): Don't allow .symver with
common symbol.
(elf_frob_symbol): Likewise.
* testsuite/gas/elf/elf.exp: Run pr21661.
* testsuite/gas/elf/pr21661.d: New file.
* testsuite/gas/elf/pr21661.s: Likewise.
ARC cpus do not accept any jump or instructions with long immediate
into the delay slots.
gas/
2017-06-07 Claudiu Zissulescu <claziss@synopsys.com>
* /config/tc-arc.c (is_br_jmp_insn_p): Update macro with known
instructions to be accounted as jumps.
(assemble_insn): Check for limms into the delay slots. Emit an
error if so.
* testsuite/gas/arc/asm-errors-3.d: New file.
* testsuite/gas/arc/asm-errors-3.err: Likewise.
* testsuite/gas/arc/asm-errors-3.s: Likewise.
=== Context ===
This patch is part of a patch series to add support for ARMv8-R
architecture. Its purpose is to add support for ARMv8-R in GAS:
instructions, build attributes and readelf.
=== Patch description ===
Although some differences exist for system registers, from GAS point of
view ARMv8-R supports the same instructions as ARMv8-A Aarch32 state
and a subset of its extensions. This patch therefore introduce a new
feature bit to distinguish the availability of the pan, ras and rdma
extensions between ARMv8-A and ARMv8-R and allow crypto, fp and simd
extensions to be used by ARMv8-R.
Most of the changes are then in the testsuite to (i) rename source files
and error output to be shared between ARMv8-A and ARMv8-R, (ii) rename
files with expected output for ARMv8-A build attributes and (iii) add
new files with expected output for ARMv8-R build attributes.
2017-06-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
binutils/
* readelf.c (arm_attr_tag_CPU_arch): Fill value for ARMv8-R.
gas/
* NEWS: Mention support for ARMv8-R architecture.
* config/tc-arm.c (arm_archs): Add entry for ARMv8-R.
(arm_extensions): Restrict pan, ras and rdma extension to
ARMv8-A and make crypto, fp and simd extensions available to
ARMv8-R.
(cpu_arch_ver): Add entry for ARMv8-R.
(aeabi_set_public_attributes): Update gas_assert for Tag_DIV_use
logic.
* testsuite/gas/arm/armv8-a+fp.s: Rename into ...
* testsuite/gas/arm/armv8-ar+fp.s: This. Remove .arch directive.
* testsuite/gas/arm/armv8-a+fp.d: Specify source to assemble and
architecture to assemble for.
* testsuite/gas/arm/armv8-r+fp.d: New.
* testsuite/gas/arm/armv8-a+simd.s: Rename into ...
* testsuite/gas/arm/armv8-ar+simd.s: This. Remove .arch directive.
* testsuite/gas/arm/armv8-a+simd.d: Specify source to assemble and
architecture to assemble for.
* testsuite/gas/arm/armv8-r+simd.d: New.
* testsuite/gas/arm/armv8-a-bad.s: Rename into ...
* testsuite/gas/arm/armv8-ar-bad.s: This. Remove .arch directive.
* testsuite/gas/arm/armv8-a-bad.l: Rename into ...
* testsuite/gas/arm/armv8-ar-bad.l: This. Decrement line number by 1.
* testsuite/gas/arm/armv8-a-bad.d: Specify source to assemble,
architecture to assemble for and adjust error output file.
* testsuite/gas/arm/armv8-r-bad.d: New.
* testsuite/gas/arm/armv8-a-barrier.s: Rename into ...
* testsuite/gas/arm/armv8-ar-barrier.s: This.
* testsuite/gas/arm/armv8-a-barrier-arm.d: Adjust source.
* testsuite/gas/arm/armv8-a-barrier-thumb.d: Likewise.
* testsuite/gas/arm/armv8-r-barrier-arm.d: New.
* testsuite/gas/arm/armv8-r-barrier-thumb.d: New.
* testsuite/gas/arm/armv8-a-it-bad.s: Rename into ...
* testsuite/gas/arm/armv8-ar-it-bad.s: This. Remove .arch directive.
* testsuite/gas/arm/armv8-a-it-bad.l: Rename into ...
* testsuite/gas/arm/armv8-ar-it-bad.l: This. Decrement line number
by 1.
* testsuite/gas/arm/armv8-a-it-bad.d: Specify source to assemble,
architecture to assemble for and adjust error output file.
* testsuite/gas/arm/armv8-r-it-bad.d: New.
* testsuite/gas/arm/armv8-a.s: Rename into ...
* testsuite/gas/arm/armv8-ar.s: This. Remove .arch directive.
* testsuite/gas/arm/armv8-a.d: Specify source to assemble and
architecture to assemble for.
* testsuite/gas/arm/armv8-r.d: New.
* testsuite/gas/arm/attr-march-armv8-r+crypto.d: New.
* testsuite/gas/arm/attr-march-armv8-r+fp.d: New.
* testsuite/gas/arm/attr-march-armv8-r+simd.d: New.
* testsuite/gas/arm/attr-march-armv8-r.d: New.
* testsuite/gas/arm/crc32.s: Rename into ...
* testsuite/gas/arm/crc32-armv8-ar.s: This.
* testsuite/gas/arm/crc32.d: Rename into ...
* testsuite/gas/arm/crc32-armv8-a.d: This. Specify source to assemble.
* testsuite/gas/arm/crc32-armv8-r.d: New.
* testsuite/gas/arm/crc32-bad.s: Rename into ...
* testsuite/gas/arm/crc32-armv8-ar-bad.s: This.
* testsuite/gas/arm/crc32-bad.d: Rename into ...
* testsuite/gas/arm/crc32-armv8-a-bad.d: This. Specify source to
assemble.
* testsuite/gas/arm/crc32-armv8-r-bad.d: New.
* testsuite/gas/arm/mask_1.s: Rename into ...
* testsuite/gas/arm/mask_1-armv8-ar.s: This.
* testsuite/gas/arm/mask_1.d: Rename into ...
* testsuite/gas/arm/mask_1-armv8-a.d: This. Specify source to
assemble.
* testsuite/gas/arm/mask_1-armv8-r.d: new.
include/
* elf/arm.h (TAG_CPU_ARCH_V8R): New macro.
* opcode/arm.h (ARM_EXT2_V8A): New macro.
(ARM_AEXT2_V8A): Rename into ...
(ARM_AEXT2_V8AR): This.
(ARM_AEXT2_V8A): New macro.
(ARM_AEXT_V8R): New macro.
(ARM_AEXT2_V8R): New macro.
(ARM_ARCH_V8R): New macro.
=== Context ===
This patch is part of a patch series to add support for ARMv8-R
architecture. Its purpose is to rework the Tag_CPU_arch build attribute
value selection to (i) match architecture or CPU if specified by user
without any need for hack and (ii) match an architecture with all the
features used if in autodetection mode or return an error.
=== Motivation ===
Currently, Tag_CPU_arch build attribute value selection assumes that an
architecture is always a superset of architectures released earlier. As
such, the logic is to browse architectures in chronological order of
release and selecting the Tag_CPU_arch value of the last one to
contribute a feature used[1]/requested[2] not contributed by earlier
architectures.
[1] in case of autodetection mode
[2] otherwise, ie. in case of -mcpu/-march or associated directives
This logic fails the two objectives mentionned in the Context section.
First, due to the assumption it does an architecture can be selected
while not having all the features used/requested which fails the second
objective. Second, not doing an exact match when an architecture or CPU
is selected by the user means the wrong value is chosen when a later
architecture provides a subset of the feature bits of an earlier
architecture. This is the case for the implementation of ARMv8-R (see
later patch).
An added benefit of this patch is that it is possible to easily generate
more consistent build attribute by setting the feature bits from the
architecture matched in aeabi_set_public_attributes in autodetection
mode. This is better done as a separate patch because lots of testcase'
expected results must then be updated accordingly.
=== Patch description ===
The patch changes the main logic for Tag_CPU_arch and
Tag_CPU_arch_profile
values selection to:
- look for an exact match in case an architecture or CPU was specified
on the command line or in a directive
- select the first released architecture that provides a superset of the
feature used in the autodetection case
- select the most featureful architecture in case of -march=all
The array cpu_arch_ver is updated to include all architectures in order
to make the first point work.
Note that when looking for an exact match, the architecture with
selected extension is tried first and then only the architecture. This
is because some architectures are exactly equivalent to an earlier
architecture with its extensions selected. ARMv6S-M (= ARMv6-M + OS
extension) and ARMv6KZ (ARMv6K + security extension) are two such
examples.
Other adjustments are also necessary in aeabi_set_public_attributes to
make this change work.
1) The logic to set Tag_ARM_ISA_use and Tag_THUMB_ISA_use must check the
absence of feature bit used/requested to decide whether to give the
default value for empty files (see EABI attribute defaults test). It was
previously checking that arch == 0 which would only happen if no feature
bit could be matched by any architecture, ie there is no feature bit to
match.
2) A fallback to a superset match must exist when no_cpu_selected ()
returns true. This is because aeabi_set_public_attributes is called
again after relaxation and at this point selected_cpu is set from the
previous execution of that function. There is therefore no way to check
whether the user specified an architecture or CPU.
3) Tag_CPU_arch lines are removed from expected output when the
detected architecture should be pre-ARMv4, since 0 is the Tag_CPU_arch
value for pre-ARMv4 architectures and default value for an absent entry
is 0.
2017-06-21 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (fpu_any): Defined from FPU_ANY.
(cpu_arch_ver): Add all architectures and sort by release date.
(have_ext_for_needed_feat_p): New.
(get_aeabi_cpu_arch_from_fset): New.
(aeabi_set_public_attributes): Call above function to determine
Tag_CPU_arch and Tag_CPU_arch_profile values. Adapt Tag_ARM_ISA_use
and Tag_THUMB_ISA_use selection logic to check absence of feature bit
accordingly.
* testsuite/gas/arm/attr-march-armv1.d: Fix expected Tag_CPU_arch build
attribute value.
* testsuite/gas/arm/attr-march-armv2.d: Likewise.
* testsuite/gas/arm/attr-march-armv2a.d: Likewise.
* testsuite/gas/arm/attr-march-armv2s.d: Likewise.
* testsuite/gas/arm/attr-march-armv3.d: Likewise.
* testsuite/gas/arm/attr-march-armv3m.d: Likewise.
* testsuite/gas/arm/pr12198-2.d: Likewise.
include/
* opcode/arm.h (FPU_ANY): New macro.
Update x86 assembler and disassembler for CET v2.0:
https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf
1. incsspd and incsspq are changed to take a register opeand with a
different opcode.
2. setssbsy is changed to take no opeand with a different opcode.
gas/
* testsuite/gas/i386/cet-intel.d: Updated.
* testsuite/gas/i386/cet.d: Likewise.
* testsuite/gas/i386/x86-64-cet-intel.d: Likewise.
* testsuite/gas/i386/x86-64-cet.d: Likewise.
* testsuite/gas/i386/cet.s: Update incsspd and setssbsy tests.
* testsuite/gas/i386/x86-64-cet.s: Likewise.
opcodes/
* i386-dis.c (RM_0FAE_REG_5): Removed.
(PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
(PREFIX_MOD_3_0F01_REG_5_RM_0): New.
(PREFIX_MOD_3_0FAE_REG_5): Likewise.
(prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
PREFIX_MOD_3_0F01_REG_5_RM_0.
(prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
PREFIX_MOD_3_0FAE_REG_5.
(mod_table): Update MOD_0FAE_REG_5.
(rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
* i386-opc.tbl: Update incsspd, incsspq and setssbsy.
* i386-tbl.h: Regenerated.
=== Context ===
This patch is part of a patch series to add support for ARMv8-R
architecture. Its purpose is to allow ARMv7 to be selected in automatic
architecture selection in presence of Thumb division instructions.
=== Motivation ===
any-idiv.d and automatic-sdiv.d testcases in GAS testsuite expect
autodetection code to select ARMv7 in presence of Thumb integer
division. However, the definition of ARM_AEXT_V7 and thus ARM_ARCH_V7 do
not contain these instructions and the idiv extension is only available
for ARMv7-A and ARMv7-R. Therefore, under the stricter automatic
detection code proposed in the subsequent patch of the series ARMv7 is
refused if a Thumb division instruction is present.
=== Patch description ===
This patch adds a new "idiv" extension after the existing one that is
available to all ARMv7 targets. This new entry is ignored by all current
code parsing arm_extensions such that it would be unavailable on the
command-line and remain a purely internal hack, easily removed in favor
of a better solution later. This is considered though by the subsequent
patch reworking automatic detection of build attributes such that ARMv7
is allowed to match in present of Thumb division instructions. For good
measure, comments are added in all instances of code browsing
arm_extensions to mention the expected behavior in case of duplicate
entries as well as a new testcase.
2017-06-20 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (arm_extensions): New duplicate idiv entry to enable
Thumb division for ARMv7 architecture.
(arm_parse_extension): Document expected behavior for duplicate
entries.
(s_arm_arch_extension): Likewise.
* testsuite/gas/arm/forbid-armv7-idiv-ext.d: New test.
* testsuite/gas/arm/forbid-armv7-idiv-ext.l: New expected output for
above test.
* config/tc-aarch64.c (reg_entry_reg_names): Add IP0,
IP1, FP, and LR as register aliases of register 16, 17, 29
and 30 respectively.
* testsuite/gas/aarch64/diagnostic.l: Remove diagnostic
prohibiting register 'lr' which is now an alias.
* testsuite/gas/aarch64/diagnostic.s: Remove instruction
utilizing register 'lr' which is now an alias.
For Thumb mode, since ARMv8-A, REG_SP is allowed in most of the places in
Rd/Rt/Rt2 etc while it was disallowed before ARMv8-A, and was rejected through
the "reject_bad_reg" macro and several scattered checks.
This patch only rejects REG_SP in "reject_bad_reg" and several related places
for legacy architectures before ARMv8-A. I have checked those affected instructions
, all of them qualify such relaxations.
Testcases adjusted accordingly.
* ld-sp-warn.d was written without .arch and without -march options passed.
By default it assumes all architectures, so I deleted the REG_SP warning
on ldrsb as it's supported on ARMv8-A. There are actually quite a few
seperate tests on other architectures, for example ld-sp-warn-v7.l etc.,
so there the test for ldrsb on legacy architectures are still covered.
* sp-pc-validations-bad-t has been extended to armv8-a.
* strex-bad-t.d restricted on armv7-a.
* Some new tests for REG_SP used as Rd/Rt etc added in sp-usage-thumb2-relax*.
gas/
* config/tc-arm.c (reject_bad_reg): Allow REG_SP on ARMv8-A.
(parse_operands): Allow REG_SP for OP_oRRnpcsp and OP_RRnpcsp on
ARMv8-A.
(do_co_reg): Allow REG_SP for Rd on ARMv8-A.
(do_t_add_sub): Likewise.
(do_t_mov_cmp): Likewise.
(do_t_tb): Likewise.
* testsuite/gas/arm/ld-sp-warn.l: Delete the warning on REG_SP as Rt for
ldrsb.
* testsuite/gas/arm/sp-pc-validations-bad-t-v8a.d: New test.
* testsuite/gas/arm/sp-pc-validations-bad-t-v8a.l: New test.
* testsuite/gas/arm/sp-pc-validations-bad-t.d: Specifies -march=armv7-a.
* testsuite/gas/arm/sp-pc-validations-bad-t.s: Remove ".arch armv7-a".
* testsuite/gas/arm/sp-usage-thumb2-relax-on-v7.d: New test.
* testsuite/gas/arm/sp-usage-thumb2-relax-on-v7.l: New test.
* testsuite/gas/arm/sp-usage-thumb2-relax-on-v8.d: New test.
* testsuite/gas/arm/sp-usage-thumb2-relax.s: New test.
* testsuite/gas/arm/strex-bad-t.d: Specifies -march=armv7-a.
