With "name" a char*, the length at name[0] might be negative, escaping
buffer limit checks.
* vms-alpha.c (evax_bfd_print_dst): Make name an unsigned char*.
(evax_bfd_print_emh): Likewise.
In the process of fixing a buffer overflow in commit fe69d4fcf0,
I managed to introduce a fairly obvious NULL pointer dereference..
* peXXigen.c (_bfd_XX_bfd_copy_private_bfd_data_common): Don't
segfault on not finding section. Wrap overlong lines.
Add support for the AMDGCN architecture to BFD.
This is the bare minimum to get
$ ./configure --target=amdgcn-hsa-amdhsa --disable-gas
$ make all-binutils
working later in this series.
The specific AMDGCN models added here are a bit arbitrary, based on
what we intend to initially support in GDB. This list will need to be
updated in the future anyway. The complete up-to-date list of existing
AMDGPU models can be found here:
https://llvm.org/docs/AMDGPUUsage.html#processors
The ELF format for this architecture is documented here:
https://llvm.org/docs/AMDGPUUsage.html#elf-code-object
The flags for the "HSA" OS ABI are properly versioned and documented on
that page. But the NONE, PAL and MESA3D OS ABIs are not well documented
nor versioned. Taking a peek at the LLVM source code, we see that they
encode their flags the same way as HSA v3. For example, for PAL:
c8b614cd74/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp (L601)
So at least, we know that all AMDGPU objects (of which AMDGCN objects
are a subset of) at the time of writing encode the specific GPU model in
the EF_AMDGPU_MACH field of e_flags.
bfd/ChangeLog:
* Makefile.am (ALL_MACHINES, ALL_MACHINES_CFILES):
Add cpu-amdgcn.c.
(BFD64_BACKENDS): Add elf64-amdgcn.lo.
(BFD64_BACKENDS_CFILES): Add elf64-amdgcn.c.
* Makefile.in: Re-generate.
* cpu-amdgcn.c: New.
* elf64-amdgcn.c: New.
* archures.c (bfd_architecture): Add bfd_arch_amdgcn and related
mach defines.
(bfd_amdgcn_arch): New.
(bfd_archures_list): Add bfd_amdgcn_arch.
* bfd-in2.h: Re-generate.
* config.bfd: Handle amdgcn* target.
* configure.ac: Handle amdgcn_elf64_le_vec.
* configure: Re-generate.
* elf-bfd.h (elf_target_id): Add AMDGCN_ELF_DATA.
* targets.c (amdgcn_elf64_le_vec): New.
(_bfd_target_vector): Add amdgcn_elf64_le_vec.
include/ChangeLog:
* elf/amdgpu.h: New.
* elf/common.h (ELFOSABI_AMDGPU_HSA): Add.
Change-Id: I969f7b14960797e88891c308749a6e341eece5b2
Section addresses can change between ppc64_elf_size_stubs and
ppc64_elf_build_stubs due to .eh_frame editing. The idea of stashing
r_offset final addresses calculated in ppc64_elf_size_stubs for use by
ppc64_elf_build_stubs was never a good idea. Instead, we need to keep
section/offset pairs.
* elf64-ppc.c (struct ppc_link_hash_table): Delete relr_addr.
Add relr section/offset array.
(append_relr_off): Rewrite. Update all callers.
(sort_relr): New function.
(ppc64_elf_size_stubs): Adjust to suit new relative reloc stash.
(ppc64_elf_build_stubs): Likewise.
PR 28848
PR 28859
* elf32-arm.c (elf32_arm_merge_eabi_attributes): If the first
input bfd has a Tag_ABI_HardFP_use set to 3 but does not also have
TAG_FP_arch set then reset the TAG_ABI_HardFP_use.
Since commit e601909a32 ("RISC-V: Support
to parse the multi-letter prefix in the architecture string.") changed
so that all prefixed extensions are parsed in single
riscv_parse_prefixed_ext call, a "while" loop on riscv_parse_subset
is no longer required.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_parse_subset): Remove unnecessary loop.
Currently we report errors as "unrecognized opcode `fence.i'" when the
opcode isn't part of the selected extensions.
This patch expands that error message to include the missing extension
information. For example, now the error message would be "unrecognized
opcode `fence.i', extension `zifencei' required".
If the opcode is not a part of any extension, the error message reverts
to "unrecognized opcode `<op statement>'".
Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
bfd/
pr 28733
* elfxx-riscv.c (riscv_multi_subset_supports_ext): New function,
used to return the extension string for each INSN_CLASS_*.
* elfxx-riscv.h: Added extern riscv_multi_subset_supports_ext.
gas/
pr 28733
* config/tc-riscv.c (struct riscv_ip_error): New structure,
contains information about errors that occur within the riscv_ip.
(riscv_ip): Use struct riscv_ip_error to report more detailed errors.
* testsuite/gas/riscv/c-fld-fsd-fail.l: Updated.
* testsuite/gas/riscv/march-imply-i2p1-01.: Likewise.
Using dummy entry in riscv_supported_std_ext cause confusing and wrongly
support `b` and `k` extensions.
bfd/
* elfxx-riscv.c (riscv_supported_std_ext): Drop unsupported
extensions.
(riscv_ext_canonical_order): New.
(riscv_init_ext_order): Use riscv_ext_canonical_order rather
than riscv_supported_std_ext to compute canonical order.
V2 Changes:
- Use `*ext` rather than `*ext != NULL` for checking is reach end of
string.
"DO NOT EDIT!" says the comment at the top of bfd-in2.h. Move the new
type field where it belongs.
PR ld/28841
* section.c (struct bfd_section): Add type. Formatting.
(BFD_FAKE_SECTION): Formatting.
* bfd-in2.h: Regenerate.
