RISC-V Psabi pr196,
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/196
bfd/
* elfxx-riscv.c (riscv_release_subset_list): Free arch_str if needed.
(riscv_copy_subset_list): Copy arch_str as well.
* elfxx-riscv.h (riscv_subset_list_t): Store arch_str for each subset list.
gas/
* config/tc-riscv.c (riscv_reset_subsets_list_arch_str): Update the
architecture string in the subset_list.
(riscv_set_arch): Call riscv_reset_subsets_list_arch_str after parsing new
architecture string.
(s_riscv_option): Likewise.
(need_arch_map_symbol): New boolean, used to indicate if .option
directives do affect instructions.
(make_mapping_symbol): New boolean parameter reset_seg_arch_str. Need to
generate $x+arch for MAP_INSN, and then store it into tc_segment_info_data
if reset_seg_arch_str is true.
(riscv_mapping_state): Decide if we need to add $x+arch for MAP_INSN. For
now, only add $x+arch if the architecture strings in subset list and segment
are different. Besides, always add $x+arch at the start of section, and do
not add $x+arch for code alignment, since rvc for alignment can be judged
from addend of R_RISCV_ALIGN.
(riscv_remove_mapping_symbol): If current and previous mapping symbol have
same value, then remove the current $x only if the previous is $x+arch;
Otherwise, always remove previous.
(riscv_add_odd_padding_symbol): Updated.
(riscv_check_mapping_symbols): Don't need to add any $x+arch if
need_arch_map_symbol is false, so changed them to $x.
(riscv_frag_align_code): Updated since riscv_mapping_state is changed.
(riscv_init_frag): Likewise.
(s_riscv_insn): Likewise.
(riscv_elf_final_processing): Call riscv_release_subset_list to release
subset_list of riscv_rps_as, rather than only release arch_str in the
riscv_write_out_attrs.
(riscv_write_out_attrs): No need to call riscv_arch_str, just get arch_str
from subset_list of riscv_rps_as.
* config/tc-riscv.h (riscv_segment_info_type): Record current $x+arch mapping
symbol of each segment.
* testsuite/gas/riscv/mapping-0*: Merged and replaced by mapping.s.
* testsuite/gas/riscv/mapping.s: New testcase, to test most of the cases in
one file.
* testsuite/gas/riscv/mapping-symbols.d: Likewise.
* testsuite/gas/riscv/mapping-dis.d: Likewise.
* testsuite/gas/riscv/mapping-non-arch.s: New testcase for the case that
does need any $x+arch.
* testsuite/gas/riscv/mapping-non-arch.d: Likewise.
* testsuite/gas/riscv/option-arch-01a.d: Updated.
opcodes/
* riscv-dis.c (riscv_disassemble_insn): Set riscv_fpr_names back to
riscv_fpr_names_abi or riscv_fpr_names_numeric when zfinx is disabled
for some specfic code region.
(riscv_get_map_state): Recognized mapping symbols $x+arch, and then reset
the architecture string once the ISA is different.
The lack thereof did caused gas to issue "internal: unreachable
INSN_CLASS_*" errors when trying to assemble respective insns without
the feature(s) enabled via e.g. ".option arch, ...". Of course a proper
hint towards the missing extension then wasn't given either.
'H', 'Smstateen', 'Sscofpmf' and 'Sstc' are four privileged extensions with
their CSR definitions and 'Smepmp' is a privileged extension with additional
CSR bits.
Volume II: Privileged Architecture of the RISC-V ISA Manual states that the
privileged architecture requires the 'Zicsr' extension. However, current
GNU Binutils has no direct way whether the program has dependency to the
privileged architecture itself.
As a workaround, we should add implications from privileged extensions that
either add new CSRs, extend existing CSRs or depends on using CSRs.
This commit adds such implications for existing privileged extensions that
satisfy this condition.
gas/ChangeLog:
* testsuite/gas/riscv/march-imply-h.d: New test, at least for 'H'.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_implicit_subsets): Add 'Zicsr'
implicications for privileged extensions 'H', 'Smstateen',
'Sscofpmf', 'Sstc' and 'Smepmp'.
Currently, GNU Binutils does not support following privileged extensions:
- 'Smepmp'
- 'Svnapot'
- 'Svpbmt'
as they do not provide new CSRs or new instructions ('Smepmp' extends the
privileged architecture CSRs but does not define the CSR itself). However,
adding them might be useful as we no longer have to "filter" ISA strings
just for toolchains (if full ISA string is given by a vendor, we can
straightly use it).
And there's a fact that supports this theory: there's already an
(unprivileged) extension which does not provide CSRs or instructions (but
only an architectural guarantee): 'Zkt' (constant timing guarantee for
certain subset of RISC-V instructions).
This simple commit simply adds three privileged extensions listed above.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_supported_std_s_ext): Add 'Smepmp',
'Svnapot' and 'Svpbmt' extensions.
This patch adds support for the Zawrs ISA extension
("wrs.nto" and "wrs.sto" instructions).
The specification can be found here:
https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XTheadMemPair extension, a collection of T-Head specific
two-GP-register memory operations.
The 'th' prefix and the "XTheadMemPair" extension are documented in a PR
for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XTheadMemIdx extension, a collection of T-Head specific
GPR memory access instructions.
The 'th' prefix and the "XTheadMemIdx" extension are documented in a PR
for the RISC-V toolchain conventions ([1]).
In total XTheadCmo introduces the following 44 instructions
(BU,HU,WU only for loads (zero-extend instead of sign-extend)):
* {L,S}{D,W,WU,H,HU,B,BU}{IA,IB} rd, rs1, imm5, imm2
* {L,S}R{D,W,WU,H,HU,B,BU} rd, rs1, rs2, imm2
* {L,S}UR{D,W,WU,H,HU,B,BU} rd, rs1, rs2, imm2
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XTheadFMemIdx extension, a collection of
T-Head-specific floating-point memory access instructions.
The 'th' prefix and the "XTheadFMemIdx" extension are documented
in a PR for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XTheadMac extension, a collection of
T-Head-specific multiply-accumulate instructions.
The 'th' prefix and the "XTheadMac" extension are documented
in a PR for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XTheadCondMov extension, a collection of
T-Head-specific conditional move instructions.
The 'th' prefix and the "XTheadCondMov" extension are documented
in a PR for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XThead{Ba,Bb,Bs} extensions, a collection of
T-Head-specific bitmanipulation instructions.
The 'th' prefix and the "XThead{Ba,Bb,Bs}" extension are documented
in a PR for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XTheadSync extension, a collection of
T-Head-specific multi-processor synchronization instructions.
The 'th' prefix and the "XTheadSync" extension are documented in a PR
for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XTheadCmo extension, a collection of T-Head specific
cache management operations.
The 'th' prefix and the "XTheadCmo" extension are documented in a PR
for the RISC-V toolchain conventions ([1]).
In total XTheadCmo introduces the following 21 instructions:
* DCACHE.{C,CI,I}ALL
* DCACHE.{C,CI,I}{PA,VA,SW} rs1
* DCACHE.C{PAL1,VAL1} rs1
* ICACHE.I{ALL,ALLS}
* ICACHE.I{PA,VA} rs1
* L2CACHE.{C,CI,I}ALL
Contrary to Zicbom, the XTheadCmo instructions don't have a constant
displacement, therefore we have a different syntax for the arguments.
To clarify this is intended behaviour, there is a set of negative test
for Zicbom-style arguments in x-thead-cmo-fail.s.
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
v2:
- Add missing DECLARE_INSN() list
- Fix ordering
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
This patch introduces changes that allow the integration of vendor ISA
extensions:
* Define a list of vendor extensions (riscv_supported_vendor_x_ext)
where vendor extensions can be added
* Introduce a section with a table in the documentation where vendor
extensions can be added
To add a vendor extension that consists of instructions only,
the following things need to be done:
* Add the extension to the riscv_supported_vendor_x_ext list
* Add lookup entry in riscv_multi_subset_supports
* Documenting the extension in c-riscv.texti
* Add test cases for all instructions
* Add MATCH*/MASK* constants and DECLARE_INSN() for all instructions
* Add new instruction class to enum riscv_insn_class
* Define the instructions in riscv_opcodes
* Additional changes if necessary (depending on the instructions)
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
This patch support ZTSO extension. It will turn on the tso flag for elf_flags
once we have enabled Ztso extension. This is intended to implement v0.1 of
the proposed specification which can be found in Chapter 25 of,
https://github.com/riscv/riscv-isa-manual/releases/download/draft-20220723-10eea63/riscv-spec.pdf.
bfd\ChangeLog:
* elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Set TSO flag.
* elfxx-riscv.c: Add Ztso's arch.
binutils\ChangeLog:
* readelf.c (get_machine_flags): Set TSO flag.
gas\ChangeLog:
* config/tc-riscv.c (riscv_set_tso): Ditto.
(riscv_set_arch): Ditto.
* testsuite/gas/riscv/ztso.d: New test.
include\ChangeLog:
* elf/riscv.h (EF_RISCV_TSO): Ditto.
Three-part patch set from Tsukasa OI to support zmmul in assembler.
The 'Zmmul' is a RISC-V extension consisting of only multiply instructions
(a subset of 'M' which has multiply and divide instructions).
bfd/
* elfxx-riscv.c (riscv_implicit_subsets): Add 'Zmmul' implied by 'M'.
(riscv_supported_std_z_ext): Add 'Zmmul' extension.
(riscv_multi_subset_supports): Add handling for new instruction class.
gas/
* testsuite/gas/riscv/attribute-09.d: Updated implicit 'Zmmul' by 'M'.
* testsuite/gas/riscv/option-arch-02.d: Likewise.
* testsuite/gas/riscv/m-ext.s: New test.
* testsuite/gas/riscv/m-ext-32.d: New test (RV32).
* testsuite/gas/riscv/m-ext-64.d: New test (RV64).
* testsuite/gas/riscv/zmmul-32.d: New expected output.
* testsuite/gas/riscv/zmmul-64.d: Likewise.
* testsuite/gas/riscv/m-ext-fail-xlen-32.d: New test (failure
by using RV64-only instructions in RV32).
* testsuite/gas/riscv/m-ext-fail-xlen-32.l: Likewise.
* testsuite/gas/riscv/m-ext-fail-zmmul-32.d: New failure test
(RV32 + Zmmul but with no M).
* testsuite/gas/riscv/m-ext-fail-zmmul-32.l: Likewise.
* testsuite/gas/riscv/m-ext-fail-zmmul-64.d: New failure test
(RV64 + Zmmul but with no M).
* testsuite/gas/riscv/m-ext-fail-zmmul-64.l: Likewise.
* testsuite/gas/riscv/m-ext-fail-noarch-64.d: New failure test
(no Zmmul or M).
* testsuite/gas/riscv/m-ext-fail-noarch-64.l: Likewise.
include/
* opcode/riscv.h (enum riscv_insn_class): Added INSN_CLASS_ZMMUL.
ld/
* testsuite/ld-riscv-elf/attr-merge-arch-01.d: We don't care zmmul in
these testcases, so just replaced m by a.
* testsuite/ld-riscv-elf/attr-merge-arch-01a.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-01b.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-02a.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-03a.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-user-ext-01.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i2p1_a2p0.s: Renamed.
* testsuite/ld-riscv-elf/attr-merge-user-ext-rv32i2p1_a2p1.s: Renamed.
opcodes/
* riscv-opc.c (riscv_opcodes): Updated multiply instructions to zmmul.
They were legacy relocation types copied from other ports. The related
-fvtable-gc was removed from GCC in 2003.
The associated assembler directives (.vtable_inherit and .vtable_entry)
have never been supported by the RISC-V port. Remove related ld code.
Link: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/323
This commit adds Zfhmin and Zhinxmin extensions (subsets of Zfh and
Zhinx extensions, respectively). In the process supporting Zfhmin and
Zhinxmin extension, this commit also changes how instructions are
categorized considering Zfhmin, Zhinx and Zhinxmin extensions.
Detailed changes,
* From INSN_CLASS_ZFH to INSN_CLASS_ZFHMIN:
flh, fsh, fmv.x.h and fmv.h.x.
* From INSN_CLASS_ZFH to INSN_CLASS_ZFH_OR_ZHINX:
fmv.h.
* From INSN_CLASS_ZFH_OR_ZHINX to INSN_CLASS_ZFH_OR_ZHINX:
fneg.h, fabs.h, fsgnj.h, fsgnjn.h, fsgnjx.h,
fadd.h, fsub.h, fmul.h, fdiv.h, fsqrt.h, fmin.h, fmax.h,
fmadd.h, fnmadd.h, fmsub.h, fnmsub.h,
fcvt.w.h, fcvt.wu.h, fcvt.h.w, fcvt.h.wu,
fcvt.l.h, fcvt.lu.h, fcvt.h.l, fcvt.h.lu,
feq.h, flt.h, fle.h, fgt.h, fge.h,
fclass.h.
* From INSN_CLASS_ZFH_OR_ZHINX to INSN_CLASS_ZFHMIN_OR_ZHINXMIN:
fcvt.s.h and fcvt.h.s.
* From INSN_CLASS_D_AND_ZFH_INX to INSN_CLASS_ZFHMIN_AND_D:
fcvt.d.h and fcvt.h.d.
* From INSN_CLASS_Q_AND_ZFH_INX to INSN_CLASS_ZFHMIN_AND_Q:
fcvt.q.h and fcvt.h.q.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_implicit_subsets): Change implicit
subsets. Zfh->Zicsr is not needed and Zfh->F is replaced with
Zfh->Zfhmin and Zfhmin->F. Zhinx->Zicsr is not needed and
Zhinx->Zfinx is replaced with Zhinx->Zhinxmin and
Zhinxmin->Zfinx.
(riscv_supported_std_z_ext): Added zfhmin and zhinxmin.
(riscv_multi_subset_supports): Rewrite handling for new
instruction classes.
(riscv_multi_subset_supports_ext): Updated.
(riscv_parse_check_conflicts): Change error message to include
zfh and zfhmin extensions.
gas/ChangeLog:
* testsuite/gas/riscv/zfhmin-d-insn-class-fail.s: New complex
error handling test.
* testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.d: Likewise.
* testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.l: Likewise.
* testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.d: Likewise.
* testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.l: Likewise.
* testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.d: Likewise.
* testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.l: Likewise.
* testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.d: Likewise.
* testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.l: Likewise.
* testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.d: Likewise.
* testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.l: Likewise.
* testsuite/gas/riscv/zhinx.d: Renamed from fp-zhinx-insns.d
and refactored.
* testsuite/gas/riscv/zhinx.s: Likewise.
include/ChangeLog:
* opcode/riscv.h (enum riscv_insn_class): Removed INSN_CLASS_ZFH,
INSN_CLASS_D_AND_ZFH_INX and INSN_CLASS_Q_AND_ZFH_INX. Added
INSN_CLASS_ZFHMIN, INSN_CLASS_ZFHMIN_OR_ZHINXMIN,
INSN_CLASS_ZFHMIN_AND_D and INSN_CLASS_ZFHMIN_AND_Q.
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcodes): Change instruction classes for
Zfh and Zfhmin instructions. Fix `fcvt.h.lu' instruction
(two operand variant) mask.
This commit fixes how instructions are masked on Zhinx+Z{d,q}inx.
fcvt.h.d and fcvt.d.h require ((D&&Zfh)||(Zdinx&&Zhinx)) and
fcvt.h.q and fcvt.q.h require ((Q&&Zfh)||(Zqinx&&Zhinx)).
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Fix feature gate
on INSN_CLASS_{D,Q}_AND_ZFH_INX.
(riscv_multi_subset_supports_ext): Fix feature gate diagnostics
on INSN_CLASS_{D,Q}_AND_ZFH_INX.
gas/ChangeLog:
* testsuite/gas/riscv/fp-zhinx-insns.d: Add Zqinx to -march
for proper testing.
Because ratified Zihintpause extension has a version number of 2.0
(not 1.0), we should update the number.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_supported_std_z_ext): Update version
number of Zihintpause extension.
This patch has been pending for almost a year... However, I noticed that
llvm can already re-order the extensions, even if they are out of orders.
Not really sure if they can also re-order the single letter extensions,
but at least we can do this for the multi-letter extensions in binutils.
bfd/
* elfxx-riscv.c (riscv_parse_prefixed_ext): Removed the code which are
used to check the prefixed extension orders.
gas/
* testsuite/gas/riscv/march-fail-order-x-z.d: Removed since we will help
tp reorder the prefixed extensions for now.
* testsuite/gas/riscv/march-fail-order-x-z.l: Likewise.
* testsuite/gas/riscv/march-fail-order-x.d: Likewise.
* testsuite/gas/riscv/march-fail-order-x.l: Likewise.
* testsuite/gas/riscv/march-fail-order-z.d: Likewise.
* testsuite/gas/riscv/march-fail-order-z.l: Likewise.
According to the picture 28.1 in the current ISA spec, h is no larger the
multi-letter extension, it is a single extension after v. Therefore, this
patch fix the implementation, and use the single h to control hypervisor
CSRs and instructions, which we promised to do before.
bfd/
* elfxx-riscv.c (riscv_supported_std_ext): Added h with version 1.0 after v.
(riscv_supported_std_h_ext): Removed.
(riscv_all_supported_ext): Updated since riscv_supported_std_h_ext is removed.
(riscv_prefix_ext_class): Removed RV_ISA_CLASS_H.
(parse_config): Updated since riscv_prefix_ext_class is removed.
(riscv_recognized_prefixed_ext): Likewise.
(riscv_get_default_ext_version): Likewise.
(riscv_multi_subset_supports): Handle INSN_CLASS_H for hypervisor instructions.
(riscv_multi_subset_supports_ext): Likewise.
gas/
* config/tc-riscv.c (riscv_csr_class): Added CSR_CLASS_H and CSR_CLASS_H_32 for
hypervisor CSRs.
(riscv_csr_address): Likewise.
* testsuite/gas/riscv/csr-version-1p10.d: Updated since hypervisor CSRs are
controlled by single h extension for now.
* testsuite/gas/riscv/csr-version-1p10.l: Likewise.
* testsuite/gas/riscv/csr-version-1p11.d: Likewise.
* testsuite/gas/riscv/csr-version-1p11.l: Likewise.
* testsuite/gas/riscv/csr-version-1p12.d: Likewise.
* testsuite/gas/riscv/csr-version-1p12.l: Likewise.
* testsuite/gas/riscv/csr-version-1p9p1.d: Likewise.
* testsuite/gas/riscv/csr-version-1p9p1.l: Likewise.
* testsuite/gas/riscv/h-ext-32.d: Added h to architecture string.
* testsuite/gas/riscv/h-ext-64.d: Likewise.
* testsuite/gas/riscv/march-fail-single-prefix-h: Removed since h is no
longer multi-letter extension.
* testsuite/gas/riscv/march-fail-unknown-h.d: Likewise.
include/
* opcode/riscv-opc.h: Control hypervisor CSRs by h extension, rather than
the privileged spec verisons.
* opcode/riscv.h (riscv_insn_class): Added INSN_CLASS_H.
opcodes/
* riscv-opc.c (riscv_opcodes): Control hypervisor instructions by h extension.
This commit adds 'H' to canonical extension ordering based on current
consensus (not officially ratified as a new ISA specification manual
but discussion for software compatibility is made).
bfd/ChangeLog
* elfxx-riscv.c (riscv_ext_canonical_order): Add 'H' for
canonical extension ordering based on current consensus.
Some strings returned by the riscv_multi_subset_supports_ext function
contain not just extension names but words like "and" and "or".
This commit wraps such strings with the gettext macro (_) for
internationalization in the future.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports_ext): Wrap some
strings with the gettext macro to prepare future i18n.
The "HOWTO size encoding" patch put 1 as the HOWTO size arg for
numerous howtos that are unused, describe dynamic relocs, are markers,
or otherwise are special purpose reloc howtos that don't care about
the size. The idea was to ensure no howto changed by inspecting
object files. Revert those changes, making them zero size.
* coff-alpha.c: Give special purpose reloc howtos a size of zero.
* coff-mcore.c, * elf-hppa.h, * elf-m10300.c, * elf32-arm.c,
* elf32-csky.c, * elf32-m32c.c, * elf32-m68k.c, * elf32-mep.c,
* elf32-mips.c, * elf32-ppc.c, * elf32-rx.c, * elf32-s390.c,
* elf32-spu.c, * elf32-tic6x.c, * elf32-tilepro.c, *elf32-vax.c,
* elf32-xtensa.c, * elf64-alpha.c, * elf64-mips.c,
* elf64-mmix.c, * elf64-ppc.c, * elf64-s390.c, * elfn32-mips.c,
* elfxx-loongarch.c, * elfxx-riscv.c, * elfxx-sparc.c,
* elfxx-tilegx.c, * som.c, * vms-alpha.c: Likewise.
The zhinx extension is a sub-extension in zfinx, corresponding to
zfh extension but use GPRs instead of FPRs.
This patch expanded the zfh insn class define, since zfh and zhinx
use the same opcodes, thanks for Nelson's works.
changelog in V2: Add missing classes of 'zfh' and 'zhinx' in
"riscv_multi_subset_supports_ext".
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): New extensions.
(riscv_multi_subset_supports_ext): New extensions.
gas/ChangeLog:
* testsuite/gas/riscv/fp-zhinx-insns.d: New test.
* testsuite/gas/riscv/fp-zhinx-insns.s: New test.
include/ChangeLog:
* opcode/riscv.h (enum riscv_insn_class): New INSN classes.
opcodes/ChangeLog:
* riscv-opc.c: Modify INSN_CLASS.
This commit makes RV32 + 'Q' extension (version 2.2 or later) not
conflicting since this combination is no longer prohibited by the
specification.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_parse_check_conflicts): Remove conflict
detection that prohibits RV32Q on 'Q' version 2.2 or later.
gas/ChangeLog:
* testsuite/gas/riscv/march-fail-rv32iq.d: Removed.
* testsuite/gas/riscv/march-fail-rv32iq.l: Likewise.
* testsuite/gas/riscv/march-fail-rv32iq2p0.d: New test
showing RV32IQ fails on 'Q' extension version 2.0.
* testsuite/gas/riscv/march-fail-rv32iq2p0.l: Likewise.
* testsuite/gas/riscv/march-fail-rv32iq2.d: Likewise.
* testsuite/gas/riscv/march-fail-rv32iq-isa-2p2.d: New test
showing RV32IQ fails on ISA specification version 2.2.
* testsuite/gas/riscv/march-ok-rv32iq2p2.d: New test
showing RV32IQ succesds on 'Q' extension version 2.2.
* testsuite/gas/riscv/march-ok-rv32iq-isa-20190608.d: New test
showing RV32IQ succesds on ISA specification 20190608.
This commit fixes canonical extension order to follow the RISC-V ISA
Manual draft-20210402-1271737 or later.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_recognized_prefixed_ext): Fix "K" extension
prefix to be placed before "J".
Since commit e601909a32 ("RISC-V: Support
to parse the multi-letter prefix in the architecture string.") changed
so that all prefixed extensions are parsed in single
riscv_parse_prefixed_ext call, a "while" loop on riscv_parse_subset
is no longer required.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_parse_subset): Remove unnecessary loop.
Currently we report errors as "unrecognized opcode `fence.i'" when the
opcode isn't part of the selected extensions.
This patch expands that error message to include the missing extension
information. For example, now the error message would be "unrecognized
opcode `fence.i', extension `zifencei' required".
If the opcode is not a part of any extension, the error message reverts
to "unrecognized opcode `<op statement>'".
Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
bfd/
pr 28733
* elfxx-riscv.c (riscv_multi_subset_supports_ext): New function,
used to return the extension string for each INSN_CLASS_*.
* elfxx-riscv.h: Added extern riscv_multi_subset_supports_ext.
gas/
pr 28733
* config/tc-riscv.c (struct riscv_ip_error): New structure,
contains information about errors that occur within the riscv_ip.
(riscv_ip): Use struct riscv_ip_error to report more detailed errors.
* testsuite/gas/riscv/c-fld-fsd-fail.l: Updated.
* testsuite/gas/riscv/march-imply-i2p1-01.: Likewise.
Using dummy entry in riscv_supported_std_ext cause confusing and wrongly
support `b` and `k` extensions.
bfd/
* elfxx-riscv.c (riscv_supported_std_ext): Drop unsupported
extensions.
(riscv_ext_canonical_order): New.
(riscv_init_ext_order): Use riscv_ext_canonical_order rather
than riscv_supported_std_ext to compute canonical order.
V2 Changes:
- Use `*ext` rather than `*ext != NULL` for checking is reach end of
string.
Update the default ISA spec from 2.2 to 20191213 will change the default
version of i from 2.0 to 2.1. Since zicsr and zifencei are separated
from i 2.1, users need to add them in the architecture string if they need
fence.i and csr instructions. Besides, we also allow old ISA spec can
recognize zicsr and zifencei, but we won't output them since they are
already included in the i extension when i's version is less than 2.1.
bfd/
* elfxx-riscv.c (riscv_parse_add_subset): Allow old ISA spec can
recognize zicsr and zifencei.
gas/
* config/tc-riscv.c (DEFAULT_RISCV_ISA_SPEC): Updated to 20191213.
* testsuite/gas/riscv/csr-version-1p10.d: Added zicsr to -march since
the default version of i is 2.1.
* testsuite/gas/riscv/csr-version-1p11.d: Likewise.
* testsuite/gas/riscv/csr-version-1p12.d: Likewise.
* testsuite/gas/riscv/csr-version-1p9p1.d: Likewise.
* testsuite/gas/riscv/option-arch-03.d: Updated i's version to 2.1.
* testsuite/gas/riscv/option-arch-03.s: Likewise.
ld/
* testsuite/ld-riscv-elf/call-relax.d: Added zicsr to -march since
the default version of i is 2.1.
* testsuite/ld-riscv-elf/attr-merge-arch-01.d: Updated i's version to 2.1.
* testsuite/ld-riscv-elf/attr-merge-arch-01a.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-01b.: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-02a.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-02b.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-03a.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-03b.s: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d: Added zifencei
into Tag_RISCV_arch since it is added implied when i's version is
larger than 2.1.
The result of running etc/update-copyright.py --this-year, fixing all
the files whose mode is changed by the script, plus a build with
--enable-maintainer-mode --enable-cgen-maint=yes, then checking
out */po/*.pot which we don't update frequently.
The copy of cgen was with commit d1dd5fcc38ead reverted as that commit
breaks building of bfp opcodes files.
According to the privileged spec, there are five new instructions for
svinval extension. Two of them (HINVAL.VVMA and HINVAL.GVMA) need to
enable the hypervisor extension. But there is no implementation of
hypervisor extension in mainline for now, so let's consider the related
issues later.
31..25 24..20 19..15 14..12 11...7 6..2 1..0
sinval.vma 0001011 rs2 rs1 000 00000 11100 11
sfence.w.inval 0001100 00000 00000 000 00000 11100 11
sfence.inval.ir 0001100 00001 00000 000 00000 11100 11
hinval.vvma 0010011 rs2 rs1 000 00000 11100 11
hinval.gvma 0110011 rs2 rs1 000 00000 11100 11
This patch is cherry-picked from the riscv integration branch since the
svinval extension is frozen for now. Besides, we fix the funct7 encodings
of hinval.vvma and hinval.gvma, from 0x0011011 and 0x0111011 to 0x0010011
and 0x0110011.
bfd/
* elfxx-riscv.c (riscv_supported_std_s_ext): Added svinval.
(riscv_multi_subset_supports): Handle INSN_CLASS_SVINVAL.
gas/
* testsuite/gas/riscv/svinval.d: New testcase.
* testsuite/gas/riscv/svinval.s: Likewise.
include/
* opcode/riscv-opc.h: Added encodings for svinval.
* opcode/riscv.h (enum riscv_insn_class): Added INSN_CLASS_SVINVAL.
opcodes/
* riscv-opc.c (riscv_opcodes): Added svinval instructions.
* To be consistent with -march option, removed the "=" operator when
user want to reset the whole architecture string. So the formats are,
.option arch, +<extension><version>, ...
.option arch, -<extension>
.option arch, <ISA string>
* Don't allow to add or remove the base extensions in the .option arch
directive. Instead, users should reset the whole architecture string
while they want to change the base extension.
* The operator "+" won't update the version of extension, if the
extension is already in the subset list.
bfd/
* elfxx-riscv.c (riscv_add_subset): Don't update the version
if the extension is already in the subset list.
(riscv_update_subset): To be consistent with -march option,
removed the "=" operator when user want to reset the whole
architecture string. Besides, Don't allow to add or remove
the base extensions in the .option arch directive.
gas/
* testsuite/gas/riscv/option-arch-01.s: Updated since we cannot
add or remove the base extensions in the .option arch directive.
* testsuite/gas/riscv/option-arch-02.s: Likewise.
* testsuite/gas/riscv/option-arch-fail.l: Likewise.
* testsuite/gas/riscv/option-arch-fail.s: Likewise.
* testsuite/gas/riscv/option-arch-01a.d: Set -misa-spec=2.2.
* testsuite/gas/riscv/option-arch-01b.d: Likewise.
* testsuite/gas/riscv/option-arch-02.d: Updated since the .option
arch, + won't change the version of extension, if the extension is
already in the subset list.
* testsuite/gas/riscv/option-arch-03.s: Removed the "=" operator
when resetting the whole architecture string.
If we always use the .option arch to call the riscv_update_subset, then
it is almost impossible that the input string will be NULL. Therefore,
just remove the redundant NULL pointer check in the riscv_update_subset.
bfd/
* elfxx-riscv.c (riscv_update_subset): Removed the redundant NULL
pointer check.
The architecture parser in riscv_update_subset shouldn't check (or access)
the pointer space which doesn't exist.
bfd/
pr 28610
* elfxx-riscv.c (riscv_update_subset): The architecture parser
shouldn't access the pointer space which doesn't exist.
https://github.com/riscv/riscv-asm-manual/pull/67
Format:
.option arch, +<extension><version>, ...
.option arch, -<extension>
.option arch, =<ISA string>
The new direcitve is used to enable/disable extensions for the specific
code region. For example,
.attribute arch, "rv64ic" # arch = rv64i2p0_c2p0
.option push
.option arch, +d2p0, -c # arch = rv64i2p0_f2p0_d2p0, f is added implied
.option arch, =rv32gc # arch = rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0
.option pop # arch = rv64i2p0_c2p0
Note that,
1. ".option rvc/norvc" have the same behavior as ".option arch +c/-c".
2. ".option arch -i" is illegal, since we cannot remove base i extension.
3. If arch=rv64i2p0, then ".option arch, +i3p0" will update the i's version
from 2.0 to 3.0.
4. If arch=rv64i3p0, then ".option arch, +i" will update the i's version
from 2.0 to the default one according to the chosen isa spec.
bfd/
* elfxx-riscv.c (riscv_add_subset): If the subset is already added,
and the new versions are not RISCV_UNKNOWN_VERSION, then update the
versions to the subset list.
(riscv_copy_subset): New function. Copy the subset from list.
(riscv_copy_subset_list): New function. Return the new copyed list.
(riscv_update_subset): Updated to make .option arch directives workable.
* elfxx-riscv.h: Updated.
gas/
* config/tc-riscv.c (riscv_subsets): Defined as a pointer.
(riscv_rps_as): Init the subset_list to NULL, we will set it later
once riscv_opts_stack is created or updated.
(struct riscv_option_stack, riscv_opts_stack): Moved forward.
(riscv_set_arch): Updated.
(s_riscv_option): Support new .option arch directive, to add, remove
or update subsets for the specific code region.
(riscv_write_out_attrs): Updated.
* doc/c-riscv.texi: Added document for new .option arch directive.
* testsuite/gas/riscv/option-arch-01a.d: New testcase.
* testsuite/gas/riscv/option-arch-01b.d: Likewise.
* testsuite/gas/riscv/option-arch-01.s: Likewise..
* testsuite/gas/riscv/option-arch-02.d: Likewise.
* testsuite/gas/riscv/option-arch-02.s: Likewise.
* testsuite/gas/riscv/option-arch-fail.d: Likewise.
* testsuite/gas/riscv/option-arch-fail.l: Likewise.
* testsuite/gas/riscv/option-arch-fail.s: Likewise.
Reuse float instructions in INSN_CLASS_F/D/Q, use riscv_subset_supports to
verify if z*inx enabled and use gpr instead of fpr when z*inx is enable.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Added support for
z*inx extension.
gas/ChangeLog:
* config/tc-riscv.c (riscv_ip): Added register choice for z*inx.
include/ChangeLog:
* opcode/riscv.h (enum riscv_insn_class): Reused INSN_CLASS_* for z*inx.
opcodes/ChangeLog:
* riscv-dis.c (riscv_disassemble_insn): Added disassemble check for
z*inx.
* riscv-opc.c: Reused INSN_CLASS_* for z*inx.
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Minimal support for zfinx, zdinx, zqinx. Like f/d/q, the zqinx
imply zdinx and zdinx imply zfinx, where zfinx are not compatible
with f/d/q.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_implicit_subsets): Added implicit rules
for z*inx extensions.
(riscv_supported_std_z_ext): Added entries for z*inx.
(riscv_parse_check_conflicts): Added conflict check for z*inx.
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
