Commit graph

327 commits

Author SHA1 Message Date
Richard Earnshaw
7917156599 arm: remove disassembly support for the FPA co-processor
Remove the FPA support from the disassembler.  This entails a couple
of testsuite fixes where we were (probably incorrectly) disassembling
a generic co-processor instruction using the legacy FPA opcodes.
2024-06-05 17:45:45 +01:00
Richard Earnshaw
ad5da6e6d8 arm: opcodes: remove Maverick disassembly.
Remove the patterns to match Maverick co-processor instructions from
the disassembly tables.

This required fixing a couple of tests in the assembler testsuite
where we, probably incorrectly, disassembled generic co-processor
instructions as a Maverick instruction (it particularly made no sense
to do this for Armv6t2 in Thumb state).
2024-05-14 10:56:58 +01:00
Claudio Bantaloukas
3e562e4be8 arm: Fix MVE vmla encoding 2024-04-23 17:59:57 +01:00
Alex Coplan
cd714ac07c arm: Fix disassembly of MVE vq[r]shr[u]n
This patch fixes the disassembly of vq[r]shr[u]n insns so that the
shift immediate is properly decoded.  See the description of the
previous patch for an example of the incorrect disassembly.

As part of this patch we also fix the mve-vqrshrn.d test which was
testing for the incorrect disassembly of the immediates.  The
disassembly now matches the assembled instructions in that test.

Finally we add an mve-vqshrn test which tests the non-rounding variants
of those insns, whose encoding we fixed with the previous patch in this
series.
2024-04-09 10:09:25 +01:00
Alex Coplan
f9d6cf2e9f arm: Refactor condition for print_mve_shift_n
This is intended to have no functional change, but refactors the
condition guarding the call to print_mve_shift_n in arm-dis.c ahead of a
later patch which adds additional insns to the set of those whose
shift immediate is disassembled using print_mve_shift_n.
2024-04-09 10:09:25 +01:00
Alan Modra
fd67aa1129 Update year range in copyright notice of binutils files
Adds two new external authors to etc/update-copyright.py to cover
bfd/ax_tls.m4, and adds gprofng to dirs handled automatically, then
updates copyright messages as follows:

1) Update cgen/utils.scm emitted copyrights.
2) Run "etc/update-copyright.py --this-year" with an extra external
   author I haven't committed, 'Kalray SA.', to cover gas testsuite
   files (which should have their copyright message removed).
3) Build with --enable-maintainer-mode --enable-cgen-maint=yes.
4) Check out */po/*.pot which we don't update frequently.
2024-01-04 22:58:12 +10:30
Andrew Burgess
4fc808ae2a opcodes/arm: adjust whitespace in cpsie instruction
While I was working on the disassembler styling for ARM I noticed that
the whitespace in the cpsie instruction was inconsistent with most of
the other ARM disassembly output, the disassembly for cpsie looks like
this:

  cpsie   if,#10

notice there's no space before the '#10' immediate, most other ARM
instructions have a space before each operand.

This commit updates the disassembler to add the missing space, and
updates the tests I found that tested this instruction.
2023-04-03 12:11:32 +01:00
Nick Clifton
7718604518 Fix an illegal memory access when disassebling a corrupt ARM file.
PR 30230
  * arm-dis.c (get_sym_code_type): Check for non-ELF symbols.
2023-03-15 11:44:56 +00:00
Alan Modra
d87bef3a7b Update year range in copyright notice of binutils files
The newer update-copyright.py fixes file encoding too, removing cr/lf
on binutils/bfdtest2.c and ld/testsuite/ld-cygwin/exe-export.exp, and
embedded cr in binutils/testsuite/binutils-all/ar.exp string match.
2023-01-01 21:50:11 +10:30
Luis Machado
76a95facf1 [opcodes/arm] Fix potential null pointer dereferences
PR tdep/29598

  As pointed out in the bug ticket, we have a couple potential null pointer
  dereferencing situations. Harden those.

  Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=29598
2022-11-10 01:12:17 +00:00
Andrew Burgess
d8521074fe opcodes/arm: silence compiler warning about uninitialized variable use
After this commit:

  commit 6576bffe6c
  Date:   Thu Jul 7 13:43:45 2022 +0100

      opcodes/arm: add disassembler styling for arm

Some people were seeing their builds failing with complaints about a
possible uninitialized variable usage.  I previously fixed an instance
of this issue in this commit:

  commit 2df82cd4b4
  Date:   Tue Nov 1 10:36:59 2022 +0000

      opcodes/arm: silence compiler warning about uninitialized variable use

which did fix the build problems that the sourceware buildbot was
hitting, however, an additional instance of the same problem was
brought to my attention, and that is fixed in this commit.

Where commit 2df82cd4b4 fixed the uninitialized variable problem in
print_mve_unpredictable, this commit fixes the same problem in
print_mve_undefined.

As with the previous commit, I don't believe we could really ever get
an uninitialized variable usage, based on the current usage of the
function, so I have just initialized the reason variable to "??".
2022-11-04 10:46:59 +00:00
Andrew Burgess
4575eafb45 opcodes/arm: don't pass non-string literal to printf like function
The earlier commit:

  commit 6576bffe6c
  Date:   Thu Jul 7 13:43:45 2022 +0100

      opcodes/arm: add disassembler styling for arm

introduced two places where a register name was passed as the format
string to the disassembler's fprintf_styled_func callback.  This will
cause a warning from some compilers, like this:

  ../../binutils-gdb/opcodes/arm-dis.c: In function ‘print_mve_vld_str_addr’:
  ../../binutils-gdb/opcodes/arm-dis.c:6005:3: error: format not a string literal and no format arguments [-Werror=format-security]
   6005 |   func (stream, dis_style_register, arm_regnames[gpr]);
        |   ^~~~

This commit fixes these by using "%s" as the format string.
2022-11-01 11:07:33 +00:00
Andrew Burgess
2df82cd4b4 opcodes/arm: silence compiler warning about uninitialized variable use
The earlier commit:

  commit 6576bffe6c
  Date:   Thu Jul 7 13:43:45 2022 +0100

      opcodes/arm: add disassembler styling for arm

was causing a compiler warning about a possible uninitialized variable
usage within opcodes/arm-dis.c.

The problem is in print_mve_unpredictable, and relates to the reason
variable, which is set by a switch table.

Currently the switch table does cover every valid value, though there
is no default case.  The variable switched on is passed in as an
argument to the print_mve_unpredictable function.

Looking at how print_mve_unpredictable is used, there is only one use,
the second argument is the one that is used for the switch table,
looking at how this argument is set, I don't believe it is possible
for this argument to take an invalid value.

So, I think the compiler warning is a false positive.  As such, my
proposed solution is to initialize the reason variable to the string
"??", this will silence the warning, and the "??" string should never
end up being printed.
2022-11-01 10:50:50 +00:00
Andrew Burgess
6576bffe6c opcodes/arm: add disassembler styling for arm
This commit adds disassembler styling for the ARM architecture.

The ARM disassembler is driven by several instruction tables,
e.g. cde_opcodes, coprocessor_opcodes, neon_opcodes, etc

The type for elements in each table can vary, but they all have one
thing in common, a 'const char *assembler' field.  This field
contains a string that describes the assembler syntax of the
instruction.

Embedded within that assembler syntax are various escape characters,
prefixed with a '%'.  Here's an example of a very simple instruction
from the arm_opcodes table:

  "pld\t%a"

The '%a' indicates a particular type of operand, the function
print_insn_arm processes the arm_opcodes table, and includes a switch
statement that handles the '%a' operand, and takes care of printing
the correct value for that instruction operand.

It is worth noting that there are many print_* functions, each
function handles a single *_opcodes table, and includes its own switch
statement for operand handling.  As a result, every *_opcodes table
uses a different mapping for the operand escape sequences.  This means
that '%a' might print an address for one *_opcodes table, but in a
different *_opcodes table '%a' might print a register operand.

Notice as well that in our example above, the instruction mnemonic
'pld' is embedded within the assembler string.  Some instructions also
include comments within the assembler string, for example, also from
the arm_opcodes table:

  "nop\t\t\t@ (mov r0, r0)"

here, everything after the '@' is a comment that is displayed at the
end of the instruction disassembly.

The next complexity is that the meaning of some escape sequences is
not necessarily fixed.  Consider these two examples from arm_opcodes:

  "ldrex%c\tr%12-15d, [%16-19R]"
  "setpan\t#%9-9d"

Here, the '%d' escape is used with a bitfield modifier, '%12-15d' in
the first instruction, and '%9-9d' in the second instruction, but,
both of these are the '%d' escape.

However, in the first instruction, the '%d' is used to print a
register number, notice the 'r' immediately before the '%d'.  In the
second instruction the '%d' is used to print an immediate, notice the
'#' just before the '%d'.

We have two problems here, first, the '%d' needs to know if it should
use register style or immediate style, and secondly, the 'r' and '#'
characters also need to be styled appropriately.

The final thing we must consider is that some escape codes result in
more than just a single operand being printed, for example, the '%q'
operand as used in arm_opcodes ends up calling arm_decode_shift, which
can print a register name, a shift type, and a shift amount, this
could end up using register, sub-mnemonic, and immediate styles, as
well as the text style for things like ',' between the different
parts.

I propose a three layer approach to adding styling:

(1) Basic state machine:

    When we start printing an instruction we should maintain the idea
    of a 'base_style'.  Every character from the assembler string will
    be printed using the base_style.

   The base_style will start as mnemonic, as each instruction starts
   with an instruction mnemonic.  When we encounter the first '\t'
   character, the base_style will change to text.  When we encounter
   the first '@' the base_style will change to comment_start.

   This simple state machine ensures that for simple instructions the
   basic parts, except for the operands themselves, will be printed in
   the correct style.

(2) Simple operand styling:

    For operands that only have a single meaning, or which expand to
    multiple parts, all of which have a consistent meaning, then I
    will simply update the operand printing code to print the operand
    with the correct style.  This will cover a large number of the
    operands, and is the most consistent with how styling has been
    added to previous architectures.

(3) New styling syntax in assembler strings:

    For cases like the '%d' that I describe above, I propose adding a
    new extension to the assembler syntax.  This extension will allow
    me to temporarily change the base_style.  Operands like '%d', will
    then print using the base_style rather than using a fixed style.

    Here are the two examples from above that use '%d', updated with
    the new syntax extension:

      "ldrex%c\t%{R:r%12-15d%}, [%16-19R]"
      "setpan\t%{I:#%9-9d%}"

    The syntax has the general form '%{X:....%}' where the 'X'
    character changes to indicate a different style.  In the first
    instruction I use '%{R:...%}' to change base_style to the register
    style, and in the second '%{I:...%}' changes base_style to
    immediate style.

    Notice that the 'r' and '#' characters are included within the new
    style group, this ensures that these characters are printed with
    the correct style rather than as text.

    The function decode_base_style maps from character to style.  I've
    included a character for each style for completeness, though only
    a small number of styles are currently used.

I have updated arm-dis.c to the above scheme, and checked all of the
tests in gas/testsuite/gas/arm/, and the styling looks reasonable.

There are no regressions on the ARM gas/binutils/ld tests that I can
see, so I don't believe I've changed the output layout at all.  There
were two binutils tests for which I needed to force the disassembler
styling off.

I can't guarantee that I've not missed some untested corners of the
disassembler, or that I might have just missed some incorrectly styled
output when reviewing the test results, but I don't believe I've
introduced any changes that could break the disassembler - the worst
should be some aspect is not styled correctly.
2022-11-01 09:32:13 +00:00
Andrew Burgess
8cb6e17571 opcodes/arm: use '@' consistently for the comment character
Looking at the ARM disassembler output, every comment seems to start
with a ';' character, so I assumed this was the correct character to
start an assembler comment.

I then spotted a couple of places where there was no ';', but instead,
just a '@' character.  I thought that this was a case of a missing
';', and proposed a patch to add the missing ';' characters.

Turns out I was wrong, '@' is actually the ARM assembler comment
character, while ';' is the statement separator.  Thus this:

    nop    ;@ comment

is two statements, the first is the 'nop' instruction, while the
second contains no instructions, just the '@ comment' comment text.

This:

    nop    @ comment

is a single 'nop' instruction followed by a comment.  And finally,
this:

    nop    ; comment

is two statements, the first contains the 'nop' instruction, while the
second contains the instruction 'comment', which obviously isn't
actually an instruction at all.

Why this matters is that, in the next commit, I would like to add
libopcodes syntax styling support for ARM.

The question then is how should the disassembler style the three cases
above?

As '@' is the actual comment start character then clearly the '@' and
anything after it can be styled as a comment.  But what about ';' in
the second example?  Style as text?  Style as a comment?

And the third example is even harder, what about the 'comment' text?
Style as an instruction mnemonic?  Style as text?  Style as a comment?

I think the only sensible answer is to move the disassembler to use
'@' consistently as its comment character, and remove all the uses of
';'.

Then, in the next commit, it's obvious what to do.

There's obviously a *lot* of tests that get updated by this commit,
the only actual code changes are in opcodes/arm-dis.c.
2022-11-01 09:32:13 +00:00
Alan Modra
4eeb001305 PR29626, Segfault when disassembling ARM code
PR 29626
	* arm-dis.c (mapping_symbol_for_insn): Return false on zero
	symtab_size.  Delete later symtab_size test.
2022-09-30 10:33:27 +09:30
Alan Modra
f15ba945a4 ubsan: arm-dis.c index out of bounds
We are way off in the weeds with this one, and will be printing
<UNPREDICTABLE> for S > 10.

	* arm-dis.c (print_insn_cde): Wrap 'T' value.
2022-09-14 10:19:56 +09:30
Alan Modra
a2c5833233 Update year range in copyright notice of binutils files
The result of running etc/update-copyright.py --this-year, fixing all
the files whose mode is changed by the script, plus a build with
--enable-maintainer-mode --enable-cgen-maint=yes, then checking
out */po/*.pot which we don't update frequently.

The copy of cgen was with commit d1dd5fcc38ead reverted as that commit
breaks building of bfp opcodes files.
2022-01-02 12:04:28 +10:30
Przemyslaw Wirkus
3197e593d8 arm: add armv9-a architecture to -march
Update also include:
	+ New value of Tag_CPU_arch EABI attribute (22) is added.
	+ Updated missing Tag_CPU_arch EABI attributes.
	+ Updated how we combine archs 'v4t_plus_v6_m' as this mechanism
	  have to handle new Armv9 as well.

Regression tested on `arm-none-eabi` cross Binutils and no issues.

bfd/

	* archures.c: Define bfd_mach_arm_9.
	* bfd-in2.h (bfd_mach_arm_9): Define bfd_mach_arm_9.
	* cpu-arm.c: Add 'armv9-a' option to -march.
	* elf32-arm.c (using_thumb2_bl): Update assert check.
	(arch_has_arm_nop): Add TAG_CPU_ARCH_V9.
	(bfd_arm_get_mach_from_attributes): Add case for TAG_CPU_ARCH_V9.
	Update assert.
	(tag_cpu_arch_combine): Updated table.
	(v9): New table..

binutils/

	* readelf.c (arm_attr_tag_CPU_arch): Update with

elfcpp/

	* arm.h: Update TAG_CPU_ARCH_ enums with correct values.

gas/

	* NEWS: Update docs.
	* config/tc-arm.c (get_aeabi_cpu_arch_from_fset): Return Armv9-a
	for -amarch=all.
	(aeabi_set_public_attributes): Update assert.
	* doc/c-arm.texi: Update docs.
	* testsuite/gas/arm/armv9-a_arch.d: New test.
	* testsuite/gas/arm/attr-march-all.d: Update test with v9.

include/

	* elf/arm.h Update TAG_CPU_ARCH_ defines with correct values.
	* opcode/arm.h (ARM_EXT3_V9A): New macro.
	(ARM_ARCH_NONE): Updated with arm_feature_set.core size.
	(FPU_NONE): Updated.
	(ARM_ANY): Updated.
	(ARM_ARCH_UNKNOWN): New macro.
	(ARM_FEATURE_LOW): Updated.
	(ARM_FEATURE_CORE): Updated.
	(ARM_FEATURE_CORE_LOW): Updated.
	(ARM_FEATURE_CORE_HIGH): Updated.
	(ARM_FEATURE_COPROC): Updated.
	(ARM_FEATURE): Updated.
	(ARM_FEATURE_ALL): New macro.

opcodes/

	* arm-dis.c (select_arm_features): Support bfd_mach_arm_9.
	Also Update bfd_mach_arm_unknown to use new macro ARM_ARCH_UNKNOWN.
2021-11-01 10:51:03 +00:00
Alan Modra
459cde81fb ubsan: arm: undefined shift
left shift of 2 by 31 places cannot be represented in type 'int'

	* arm-dis.c (print_insn_thumb16): Avoid undefined behaviour.
2021-10-28 07:40:49 +10:30
Tom de Vries
cad152f221 [gdb/tdep] Reset force_thumb in parse_arm_disassembler_options
With a gdb build with --enable-targets=all, we have 2 arch-specific failures
in selftest print_one_insn:
...
$ gdb -q -batch a.out -ex "maint selftest print_one_insn" 2>&1 \
  | grep "Self test failed: arch "
Self test failed: arch armv8.1-m.main: self-test failed at \
  disasm-selftests.c:165
Self test failed: arch arm_any: self-test failed at disasm-selftests.c:165
$
...

During the first failed test, force_thumb is set to true, and remains so until
and during the second test, which causes the second failure.

Fix this by resetting force_thumb to false in parse_arm_disassembler_options,
such that we get just one failure:
...
$ gdb -q -batch a.out -ex "maint selftest print_one_insn" 2>&1 \
  | grep "Self test failed: arch "
Self test failed: arch armv8.1-m.main: self-test failed at \
  disasm-selftests.c:165
$
...

Tested on x86_64-linux.
2021-09-13 20:16:36 +02:00
Andrea Corallo
5c43020d83 PATCH [9/10] arm: add 'pacg' instruction for Armv8.1-M pacbti extension
gas/
2021-06-11  Andrea Corallo  <andrea.corallo@arm.com>

	* config/tc-arm.c (T16_32_TAB): Add '_pacg'.
	(do_t_pacbti_pacg): New function.
	(insns): Define 'pacg' insn.
	* testsuite/gas/arm/armv8_1-m-pacbti.d: Add 'pacg' test.
	* testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise.

opcodes/
2021-06-11  Andrea Corallo  <andrea.corallo@arm.com>

	* arm-dis.c (thumb32_opcodes): Add 'pacg'.
2021-07-26 14:18:24 +02:00
Andrea Corallo
be05908c0c PATCH [8/10] arm: add 'autg' instruction for Armv8.1-M pacbti extension
gas/
2021-06-11  Andrea Corallo  <andrea.corallo@arm.com>

	* config/tc-arm.c (T16_32_TAB): Add '_autg'.
	(insns): Define 'autg' insn.
	* testsuite/gas/arm/armv8_1-m-pacbti.d: Add autg test.
	* testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise.

opcodes/
2021-06-11  Andrea Corallo  <andrea.corallo@arm.com>

	* arm-dis.c (thumb32_opcodes): Add 'autg'.
2021-07-26 14:18:24 +02:00
Andrea Corallo
e07352fa4f PATCH [7/10] arm: add 'bxaut' instruction for Armv8.1-M pacbti extension
gas/
2021-06-11  Andrea Corallo  <andrea.corallo@arm.com>

	* config/tc-arm.c (T16_32_TAB): Add '_bxaut'.
	(do_t_pacbti_nonop): New function.
	(insns): Define 'bxaut' insn.
	* testsuite/gas/arm/armv8_1-m-pacbti.d: Add 'bxaut' test.
	* testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise.

opcodes/
2021-06-11  Andrea Corallo  <andrea.corallo@arm.com>

	* arm-dis.c (thumb32_opcodes): Add 'bxaut'.
2021-07-26 14:18:24 +02:00
Andrea Corallo
ce537a7db7 PATCH [4/10] arm: add 'pac' instruction for Armv8.1-M pacbti extension
gas/
2021-06-11  Andrea Corallo  <andrea.corallo@arm.com>

	* config/tc-arm.c (T16_32_TAB): Add '_pac'.
	(insns): Add 'pac' insn.
	* testsuite/gas/arm/armv8_1-m-pacbti-bad.l: Add pac tests.
	* testsuite/gas/arm/armv8_1-m-pacbti-bad.s: Likewise.
	* testsuite/gas/arm/armv8_1-m-pacbti.d: Likewise.
	* testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise.

opcodes/
2021-06-11  Andrea Corallo  <andrea.corallo@arm.com>

	* arm-dis.c (thumb32_opcodes): Add 'pac'.
2021-07-26 14:18:24 +02:00
Andrea Corallo
e43ca2cbae PATCH [3/10] arm: add 'aut' instruction for Armv8.1-M pacbti extension
gas/
2021-06-11  Andrea Corallo  <andrea.corallo@arm.com>

	* config/tc-arm.c (insns): Add 'aut.'
	(T16_32_TAB): Add '_aut'.
	* testsuite/gas/arm/armv8_1-m-pacbti-bad.l: Add 'aut' tests.
	* testsuite/gas/arm/armv8_1-m-pacbti-bad.s: Likewise.
	* testsuite/gas/arm/armv8_1-m-pacbti.d: Likewise.
	* testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise.

opcodes/
2021-06-11  Andrea Corallo  <andrea.corallo@arm.com>

	* arm-dis.c (thumb32_opcodes): Add 'aut'.
2021-07-26 14:18:24 +02:00
Andrea Corallo
f1e1d7f305 PATCH [2/10] arm: add 'pacbti' instruction for Armv8.1-M pacbti extension
gas/
2021-06-11  Andrea Corallo  <andrea.corallo@arm.com>

	* config/tc-arm.c
	(enum operand_parse_code): Add OP_SP and OP_R12.
	(parse_operands): Add switch cases for OP_SP and OP_R12.
	(T16_32_TAB): Add '_pacbti'.
	(do_t_pacbti): New function.
	(insns): Add 'pacbti'.
	* testsuite/gas/arm/armv8_1-m-pacbti-bad.d: New file.
	* testsuite/gas/arm/armv8_1-m-pacbti-bad.l: Likewise.
	* testsuite/gas/arm/armv8_1-m-pacbti-bad.s: Likewise.
	* testsuite/gas/arm/armv8_1-m-pacbti.d: Add 'pacbti' to testcase.
	* testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise.

opcodes/
2021-06-11  Andrea Corallo  <andrea.corallo@arm.com>

	* arm-dis.c (thumb32_opcodes): Add 'pacbti' instruction.
2021-07-26 14:18:24 +02:00
Andrea Corallo
3751264cdd PATCH [1/10] arm: add 'bti' instruction for Armv8.1-M pacbti extension
gas/
2021-06-11  Andrea Corallo  <andrea.corallo@arm.com>

	* config/tc-arm.c (insns): Add 'bti' insn.
	* testsuite/gas/arm/armv8_1-m-pacbti.d: New file.
	* testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise.

opcodes/
2021-06-11  Andrea Corallo  <andrea.corallo@arm.com>

	* arm-dis.c (thumb32_opcodes): Add bti instruction.
2021-07-26 14:18:24 +02:00
Alex Coplan
e683cb4120 arm: Fix bugs with MVE vmov from two GPRs to vector lanes
The initial problem I wanted to fix here is that GAS was rejecting MVE
instructions such as:

vmov q3[2], q3[0], r2, r2

with:

Error: General purpose registers may not be the same -- `vmov q3[2],q3[0],r2,r2'

which is incorrect; such instructions are valid. Note that for moves in
the other direction, e.g.:

vmov r2, r2, q3[2], q3[0]

GAS is correct in rejecting this as it does not make sense to move both
lanes into the same register (the Arm ARM says this is CONSTRAINED
UNPREDICTABLE).

After fixing this issue, I added assembly/disassembly tests for these
vmovs. This revealed several disassembly issues, including incorrectly
marking the moves into vector lanes as UNPREDICTABLE, and disassembling
many of the vmovs as vector loads. These are now fixed.

gas/ChangeLog:

	* config/tc-arm.c (do_mve_mov): Only reject vmov if we're moving
	into the same GPR twice.
	* testsuite/gas/arm/mve-vmov-bad-2.l: Tweak error message.
	* testsuite/gas/arm/mve-vmov-3.d: New test.
	* testsuite/gas/arm/mve-vmov-3.s: New test.

opcodes/ChangeLog:

	* arm-dis.c (mve_opcodes): Fix disassembly of
	MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
	(is_mve_encoding_conflict): MVE vector loads should not match
	when P = W = 0.
	(is_mve_unpredictable): It's not unpredictable to use the same
	source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
2021-05-17 15:12:39 +01:00
Martin Liska
e9b095a538 Remove strneq macro and use startswith.
bfd/ChangeLog:

	* ecoff.c (strneq): Remove strneq and use startswith.
	(_bfd_ecoff_slurp_armap): Likewise.

binutils/ChangeLog:

	* elfcomm.h (strneq): Remove strneq and use startswith.
	* readelf.c (ia64_process_unwind): Likewise.
	(process_note): Likewise.

gas/ChangeLog:

	* config/obj-coff.c (strneq): Remove strneq and use startswith.
	(weak_is_altname): Likewise.
	(obj_coff_section): Likewise.
	* config/tc-cr16.c (process_label_constant): Likewise.
	* config/tc-crx.c (strneq): Likewise.

include/ChangeLog:

	* opcode/cr16.h (strneq): Remove strneq and use startswith.

ld/ChangeLog:

	* ldbuildid.c (strneq): Remove strneq and use startswith.
	(validate_build_id_style): Likewise.
	(compute_build_id_size): Likewise.

opcodes/ChangeLog:

	* arm-dis.c (strneq): Remove strneq and use startswith.
	* cr16-dis.c (print_insn_cr16): Likewise.
	* score-dis.c (streq): Likewise.
	(strneq): Likewise.
	* score7-dis.c (strneq): Likewise.
2021-04-01 15:00:56 +02:00
Alan Modra
78933a4ad9 Use bool in opcodes
cpu/
	* frv.opc: Replace bfd_boolean with bool, FALSE with false, and
	TRUE with true throughout.
opcodes/
	* sysdep.h (POISON_BFD_BOOLEAN): Define.
	* aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
	* aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
	* aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
	* arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
	* cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
	* disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
	* i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
	* microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
	* mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
	* msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
	* ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
	* tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
	* xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
	and TRUE with true throughout.
2021-03-31 10:49:23 +10:30
Alan Modra
63b4cc53dc TRUE/FALSE simplification
There is really no need to write code like "foo != 0 ? TRUE : FALSE"
unless we had stupidly defined FALSE as something other than 0 or TRUE
as something other than 1.  The simpler "foo != 0" does just as well.
Similarly "(condition == TRUE)" or "(condition == FALSE) can be
simplified to "(condition)" and "(!condition)" respectively.

I'll note that there is reason to use "integer_expression != 0" when
assigning a bfd_boolean rather than the simpler "integer_expression",
if you expect the variable to have 0 or 1 value.  It's probably even a
good idea to not rely on implicit conversion if bfd_boolean were _Bool.

bfd/
	* aoutx.h (aout_link_write_symbols): Don't cast boolean expression
	to bfd_boolean.
	* elf32-or1k.c (or1k_set_got_and_rela_sizes): Dont compare booleans
	against FALSE.
	* elf32-arc.c (name_for_global_symbol): Don't compare boolean to TRUE.
	(is_reloc_PC_relative): Don't use "boolean_condition ? TRUE : FALSE".
	(is_reloc_SDA_relative, is_reloc_for_GOT): Likewise.
	(is_reloc_for_PLT, is_reloc_for_TLS): Likewise.
	* elf32-arm.c (stm32l4xx_need_create_replacing_stub): Likewise.
	* elf32-nds32.c (insert_nds32_elf_blank): Likewise.
	* elf32-rx.c (rx_set_section_contents): Likewise.
	* elfnn-aarch64.c (elfNN_aarch64_final_link_relocate): Likewise.
	* elfxx-mips.c (_bfd_mips_elf_ignore_undef_symbol): Likewise.
	* mach-o.c (bfd_mach_o_read_command): Likewise.
	* targets.c (bfd_get_target_info): Likewise.
binutils/
	* dlltool.c (main): Don't use "boolean_condition ? TRUE : FALSE".
	* dwarf.c (read_and_display_attr_value): Likewise.
	(display_debug_str_offsets): Likewise.
	* objdump.c (dump_bfd): Likewise.
	* readelf.c (dump_section_as_strings): Likewise.
	(dump_section_as_bytes): Likewise.
gas/
	* atof-generic.c (FALSE, TRUE): Don't define.
	* config/obj-elf.h (FALSE, TRUE): Don't define.
	* config/obj-som.h (FALSE, TRUE): Don't define.
	* config/tc-hppa.h (FALSE, TRUE): Don't define.
	* config/tc-pdp11.c (FALSE, TRUE): Don't define.
	* config/tc-iq2000.h (obj_fix_adjustable): Delete.
	* config/tc-m32r.h (TC_FIX_ADJUSTABLE): Delete.
	* config/tc-mt.h (obj_fix_adjustable): Delete.
	* config/tc-nds32.h (TC_FIX_ADJUSTABLE): Delete.
	* config/tc-arc.c (parse_opcode_flags): Simplify boolean expression.
	(relaxable_flag, relaxable_operand, assemble_insn): Likewise.
	(tokenize_extregister): Likewise.
	* config/tc-csky.c (parse_opcode, get_operand_value): Likewise.
	(parse_operands_op, parse_operands, md_assemble): Likewise.
	* config/tc-d10v.c (build_insn): Likewise.
	* config/tc-score.c (s3_gen_insn_frag): Likewise.
	* config/tc-score7.c (s7_gen_insn_frag, s7_relax_frag): Likewise.
	* config/tc-tic6x.c (tic6x_update_features, md_assemble): Likewise.
	* config/tc-z80.c (emit_byte): Likewise.
include/
	* opcode/aarch64.h (alias_opcode_p): Simplify boolean expression.
	(opcode_has_alias, pseudo_opcode_p, optional_operand_p): Likewise.
	(opcode_has_special_coder): Likewise.
ld/
	* emultempl/aix.em (gld${EMULATION_NAME}_before_allocation): Simplify
	boolean expression.
	* lexsup.c (parse_args): Likewise.
	* pe-dll.c (pe_dll_id_target): Likewise.
opcodes/
	* aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
	(fp_qualifier_p, get_data_pattern): Likewise.
	(aarch64_get_operand_modifier_from_value): Likewise.
	(aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
	(operand_variant_qualifier_p): Likewise.
	(qualifier_value_in_range_constraint_p): Likewise.
	(aarch64_get_qualifier_esize): Likewise.
	(aarch64_get_qualifier_nelem): Likewise.
	(aarch64_get_qualifier_standard_value): Likewise.
	(get_lower_bound, get_upper_bound): Likewise.
	(aarch64_find_best_match, match_operands_qualifier): Likewise.
	(aarch64_print_operand): Likewise.
	* aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
	(operand_need_sign_extension, operand_need_shift_by_two): Likewise.
	(operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
	* arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
	* tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
	(print_insn_tic6x): Likewise.
2021-03-29 11:22:22 +10:30
Martin Liska
08dedd6631 Add startswith function and use it instead of CONST_STRNEQ.
bfd/ChangeLog:

	* bfd-in.h (startswith): Add startswith function.
	(CONST_STRNEQ): Remove.
	* bfd-in2.h (startswith): Regenerate with make headers.
	* archive.c (bfd_slurp_armap): Replace usage of CONST_STRNEQ with startswith.
	(_bfd_slurp_extended_name_table): Likewise.
	* archive64.c (_bfd_archive_64_bit_slurp_armap): Likewise.
	* bfd.c (bfd_get_sign_extend_vma): Likewise.
	(bfd_convert_section_size): Likewise.
	(bfd_convert_section_contents): Likewise.
	* coff-stgo32.c (go32exe_create_stub): Likewise.
	(go32exe_check_format): Likewise.
	* coffcode.h (styp_to_sec_flags): Likewise.
	(GNU_DEBUGALTLINK): Likewise.
	* coffgen.c (_bfd_coff_section_already_linked): Likewise.
	(coff_gc_sweep): Likewise.
	(bfd_coff_gc_sections): Likewise.
	* cofflink.c (coff_link_add_symbols): Likewise.
	(process_embedded_commands): Likewise.
	* compress.c (bfd_is_section_compressed_with_header): Likewise.
	(bfd_init_section_decompress_status): Likewise.
	* dwarf2.c (find_debug_info): Likewise.
	(place_sections): Likewise.
	* ecoff.c (_bfd_ecoff_slurp_armap): Likewise.
	* elf-m10300.c (_bfd_mn10300_elf_size_dynamic_sections): Likewise.
	* elf.c (_bfd_elf_make_section_from_shdr): Likewise.
	(assign_section_numbers): Likewise.
	(elfcore_grok_win32pstatus): Likewise.
	* elf32-arm.c (cmse_scan): Likewise.
	(elf32_arm_gc_mark_extra_sections): Likewise.
	(elf32_arm_size_dynamic_sections): Likewise.
	(is_arm_elf_unwind_section_name): Likewise.
	* elf32-bfin.c (bfin_size_dynamic_sections): Likewise.
	* elf32-cr16.c (_bfd_cr16_elf_size_dynamic_sections): Likewise.
	* elf32-cris.c (elf_cris_size_dynamic_sections): Likewise.
	* elf32-csky.c (csky_elf_size_dynamic_sections): Likewise.
	* elf32-hppa.c (elf32_hppa_size_dynamic_sections): Likewise.
	* elf32-iq2000.c (iq2000_elf_check_relocs): Likewise.
	* elf32-lm32.c (lm32_elf_size_dynamic_sections): Likewise.
	* elf32-m32r.c (m32r_elf_size_dynamic_sections): Likewise.
	* elf32-m68k.c (elf_m68k_size_dynamic_sections): Likewise.
	* elf32-metag.c (elf_metag_size_dynamic_sections): Likewise.
	* elf32-msp430.c (msp430_elf_relax_delete_bytes): Likewise.
	* elf32-nios2.c (nios2_elf32_size_dynamic_sections): Likewise.
	* elf32-or1k.c (or1k_elf_size_dynamic_sections): Likewise.
	* elf32-ppc.c (ppc_elf_size_dynamic_sections): Likewise.
	* elf32-s390.c (elf_s390_size_dynamic_sections): Likewise.
	* elf32-score.c (s3_bfd_score_elf_size_dynamic_sections): Likewise.
	* elf32-score7.c (s7_bfd_score_elf_size_dynamic_sections): Likewise.
	* elf32-sh.c (sh_elf_size_dynamic_sections): Likewise.
	* elf32-tic6x.c (is_tic6x_elf_unwind_section_name): Likewise.
	(elf32_tic6x_size_dynamic_sections): Likewise.
	* elf32-vax.c (elf_vax_size_dynamic_sections): Likewise.
	* elf32-xtensa.c (elf_xtensa_size_dynamic_sections): Likewise.
	(xtensa_is_insntable_section): Likewise.
	(xtensa_is_littable_section): Likewise.
	(xtensa_is_proptable_section): Likewise.
	(xtensa_property_section_name): Likewise.
	(xtensa_callback_required_dependence): Likewise.
	* elf64-alpha.c (elf64_alpha_size_dynamic_sections): Likewise.
	* elf64-hppa.c (elf64_hppa_size_dynamic_sections): Likewise.
	* elf64-ia64-vms.c (is_unwind_section_name): Likewise.
	(get_reloc_section): Likewise.
	(elf64_ia64_size_dynamic_sections): Likewise.
	(elf64_ia64_object_p): Likewise.
	* elf64-mmix.c (mmix_elf_add_symbol_hook): Likewise.
	* elf64-ppc.c (ppc64_elf_size_dynamic_sections): Likewise.
	* elf64-s390.c (elf_s390_size_dynamic_sections): Likewise.
	* elflink.c (elf_link_add_object_symbols): Likewise.
	(_bfd_elf_gc_mark_extra_sections): Likewise.
	(bfd_elf_parse_eh_frame_entries): Likewise.
	(_bfd_elf_section_already_linked): Likewise.
	* elfnn-aarch64.c (elfNN_aarch64_size_dynamic_sections): Likewise.
	* elfnn-ia64.c (is_unwind_section_name): Likewise.
	(elfNN_ia64_size_dynamic_sections): Likewise.
	(elfNN_ia64_object_p): Likewise.
	* elfxx-mips.c (FN_STUB_P): Likewise.
	(CALL_STUB_P): Likewise.
	(CALL_FP_STUB_P): Likewise.
	(_bfd_mips_elf_section_from_shdr): Likewise.
	(_bfd_mips_elf_fake_sections): Likewise.
	(_bfd_mips_elf_size_dynamic_sections): Likewise.
	(_bfd_mips_final_write_processing): Likewise.
	(_bfd_mips_elf_final_link): Likewise.
	* elfxx-sparc.c (_bfd_sparc_elf_size_dynamic_sections): Likewise.
	* elfxx-x86.c (elf_i386_is_reloc_section): Likewise.
	(elf_x86_64_is_reloc_section): Likewise.
	* hpux-core.c (thread_section_p): Likewise.
	* libcoff.h (bfd_pei_p): Likewise.
	* linker.c (REAL): Likewise.
	(unwrap_hash_lookup): Likewise.
	(_bfd_generic_link_add_one_symbol): Likewise.
	* mmo.c (mmo_internal_write_section): Likewise.
	* osf-core.c (osf_core_core_file_p): Likewise.
	* pef.c (bfd_pef_print_symbol): Likewise.
	* pei-x86_64.c (pex64_print_all_pdata_sections): Likewise.
	* som.c (som_slurp_symbol_table): Likewise.
	(som_slurp_armap): Likewise.
	* wasm-module.c (wasm_compute_custom_section_file_position): Likewise.

binutils/ChangeLog:

	* dlltool.c (scan_drectve_symbols): Replace usage of CONST_STRNEQ with startswith.
	* emul_aix.c (ar_emul_aix_parse_arg): Likewise.
	* objcopy.c (is_mergeable_note_section): Likewise.
	* objdump.c (dump_dwarf_section): Likewise.
	* prdbg.c (pr_method_type): Likewise.
	(pr_class_baseclass): Likewise.
	(tg_class_baseclass): Likewise.
	* readelf.c (process_lto_symbol_tables): Likewise.
	* stabs.c (ULLHIGH): Likewise.
	(parse_stab_argtypes): Likewise.
	(stab_demangle_function_name): Likewise.

gas/ChangeLog:

	* config/tc-i386.c (md_parse_option): Replace usage of CONST_STRNEQ with startswith.
	(x86_64_section_word): Likewise.
	* config/tc-sparc.c (md_parse_option): Likewise.

gdb/ChangeLog:

	* arm-tdep.c (show_disassembly_style_sfunc): Replace usage of CONST_STRNEQ with startswith.
	(_initialize_arm_tdep): Likewise.

ld/ChangeLog:

	* emultempl/aix.em: Replace usage of CONST_STRNEQ with startswith.
	* emultempl/beos.em: Likewise.
	* emultempl/elf.em: Likewise.
	* emultempl/pe.em: Likewise.
	* emultempl/pep.em: Likewise.
	* emultempl/xtensaelf.em: Likewise.
	* ldctor.c (ctor_prio): Likewise.
	* ldelf.c (ldelf_try_needed): Likewise.
	(ldelf_parse_ld_so_conf): Likewise.
	(ldelf_after_open): Likewise.
	(output_rel_find): Likewise.
	(ldelf_place_orphan): Likewise.
	* ldfile.c (ldfile_add_library_path): Likewise.
	* ldlang.c (lang_add_input_file): Likewise.
	* ldmain.c (get_sysroot): Likewise.
	(get_emulation): Likewise.
	(add_archive_element): Likewise.
	* ldwrite.c (unsplittable_name): Likewise.
	(clone_section): Likewise.
	* lexsup.c (parse_args): Likewise.
	* pe-dll.c (is_import): Likewise.
	(pe_implied_import_dll): Likewise.

opcodes/ChangeLog:

	* aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
	* arc-dis.c (parse_option): Likewise.
	* arm-dis.c (parse_arm_disassembler_options): Likewise.
	* cris-dis.c (print_with_operands): Likewise.
	* h8300-dis.c (bfd_h8_disassemble): Likewise.
	* i386-dis.c (print_insn): Likewise.
	* ia64-gen.c (fetch_insn_class): Likewise.
	(parse_resource_users): Likewise.
	(in_iclass): Likewise.
	(lookup_specifier): Likewise.
	(insert_opcode_dependencies): Likewise.
	* mips-dis.c (parse_mips_ase_option): Likewise.
	(parse_mips_dis_option): Likewise.
	* s390-dis.c (disassemble_init_s390): Likewise.
	* wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
2021-03-22 11:01:43 +01:00
Alan Modra
250d07de5c Update year range in copyright notice of binutils files 2021-01-01 10:31:05 +10:30
Alan Modra
279edac53d C++ comments
binutils isn't c99 (yet).  This replaces or removes some C++ style
comments.

bfd/
	* arc-got.h: Use C style comments.
	* coff-z80.c: Likewise.
	* elf32-csky.c: Likewise.
	* peXXigen.c: Likewise.
	* elf32-m32c.c (m32c_elf_relax_delete_bytes): Remove commented out
	code.
binutils/
	* dwarf.c: Use C style comments.
	* resrc.c: Likewise.
gas/
	* config/tc-s12z.c: Use C style comments.
	* config/tc-z80.c: Likewise.
	* config/tc-xtensa.c (emit_ld_r_n): Remove commented out code.
include/
	* coff/internal.h: Use C style comments.
	* coff/pe.h: Likewise.
	* elf/ppc64.h: Likewise.
opcodes/
	* arm-dis.c: Use C style comments.
	* cr16-opc.c: Likewise.
	* ft32-dis.c: Likewise.
	* moxie-opc.c: Likewise.
	* tic54x-dis.c: Likewise.
	* s12z-opc.c: Remove useless comment.
	* xgate-dis.c: Likewise.
2020-06-29 10:07:56 +09:30
Alex Coplan
26417f1919 [PATCH] arm: Add DFB instruction for ARMv8-R
gas/ChangeLog:
2020-06-08  Alex Coplan  <alex.coplan@arm.com>

	* config/tc-arm.c (insns): Add dfb.
	* testsuite/gas/arm/dfb.d: New test.
	* testsuite/gas/arm/dfb.s: Input for test.

opcodes/ChangeLog:
2020-06-08  Alex Coplan  <alex.coplan@arm.com>

	* arm-dis.c (arm_opcodes): Add dfb.
	(thumb32_opcodes): Add dfb.
2020-06-08 15:16:29 +01:00
Fredrik Strupe
e409955ddc [PATCH v2] binutils: arm: Fix disassembly of conditional VDUPs.
VDUP (neon) instructions can be conditional, but this is not taken into
account in the current master. This commit fixes that by i) fixing the
VDUP instruction masks and ii) adding logic for disassembling
conditional neon instructions.

opcodes	* arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
	(print_insn_neon): Support disassembly of conditional
	instructions.

binutils* testsuite/binutils-all/arm/vdup-cond.d: New test for testing that
	conditional VDUP instructions are disassembled correctly.
	* testsuite/binutils-all/arm/vdup-cond.s: New file used by
	vdup-cond.d.
	* testsuite/binutils-all/arm/vdup-thumb.d: New test for testing
	that VDUP instructions (which are conditional in A32) can be
	disassembled in thumb mode.
	* testsuite/binutils-all/arm/vdup-cond.s: New file used by
	vdup-thumb.d.
2020-04-17 17:25:19 +01:00
Matthew Malcomson
5aae9ae97f [binutils][arm] Implement Custom Datapath Extensions for MVE
Here we implement the custom datapath extensions for MVE.

This required the following changes:

- Adding a new register argument type (that takes either an MVE vector or
  a Neon S or D register).
- Adding two new immediate operands types (0-127 and 0-4095).
- Using the Neon type machinery to distinguish between instruction
  types.  This required the introduction of new neon shapes to account
  for the coprocessor operands to these instructions.
- Adding a new disassembly character to `print_insn_cde` to handle the
  new register types.

Specification can be found at
https://developer.arm.com/docs/ddi0607/latest

Successfully regression tested on arm-none-eabi, and arm-wince-pe.

gas/ChangeLog:

2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/tc-arm.c (NEON_MAX_TYPE_ELS): Increment to account for
	instructions that can have 5 arguments.
	(enum operand_parse_code): Add new operands.
	(parse_operands): Account for new operands.
	(S5): New macro.
	(enum neon_shape_el): Introduce P suffixes for coprocessor.
	(neon_select_shape): Account for P suffix.
	(LOW1): Move macro to global position.
	(HI4): Move macro to global position.
	(vcx_assign_vec_d): New.
	(vcx_assign_vec_m): New.
	(vcx_assign_vec_n): New.
	(enum vcx_reg_type): New.
	(vcx_get_reg_type): New.
	(vcx_size_pos): New.
	(vcx_vec_pos): New.
	(vcx_handle_shape): New.
	(vcx_ensure_register_in_range): New.
	(vcx_handle_register_arguments): New.
	(vcx_handle_insn_block): New.
	(vcx_handle_common_checks): New.
	(do_vcx1): New.
	(do_vcx2): New.
	(do_vcx3): New.
	* testsuite/gas/arm/cde-missing-fp.d: New test.
	* testsuite/gas/arm/cde-missing-fp.l: New test.
	* testsuite/gas/arm/cde-missing-mve.d: New test.
	* testsuite/gas/arm/cde-missing-mve.l: New test.
	* testsuite/gas/arm/cde-mve-or-neon.d: New test.
	* testsuite/gas/arm/cde-mve-or-neon.s: New test.
	* testsuite/gas/arm/cde-mve.s: New test.
	* testsuite/gas/arm/cde-warnings.l:
	* testsuite/gas/arm/cde-warnings.s:
	* testsuite/gas/arm/cde.d:
	* testsuite/gas/arm/cde.s:

opcodes/ChangeLog:

2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>

	* arm-dis.c (print_insn_cde): Define 'V' parse character.
	(cde_opcodes): Add VCX* instructions.
2020-02-10 16:50:14 +00:00
Matthew Malcomson
4934a27c8c [binutils][arm] arm support for ARMv8.m Custom Datapath Extension
This patch is part of a series that adds support for the Armv8.m
ARMv8.m Custom Datapath Extension to binutils.

This patch introduces the Custom Instructions Class 1/2/3 (Single/
Dual, Accumulator/Non-accumulator varianats) to the arm backend.

The following Custom Instructions are added: cx1, cx1a,
cx1d, cx1da, cx2, cx2a, cx2d, cx2da, cx3, cx3a, cx3d, cx3da.

Specification can be found at
https://developer.arm.com/docs/ddi0607/latest

This patch distinguishes between enabling CDE for different coprocessor
numbers by defining multiple architecture flags.  This means that the
parsing of the architecture extension flags is kept entirely in the
existing code path.

We introduce a new IT block state to indicate the behaviour of these
instructions.  This new state allows being used in an IT block or
outside an IT block, but does not allow the instruction to be used
inside a VPT block.
We need this since the CX*A instruction versions can be used in IT
blocks, but they aren't to have the conditional suffixes on them.  Hence
we need to mark an instruction as allowed in either position.

We also need a new flag to objdump, in order to determine whether to
disassemble an instruction as CDE related or not.

Successfully regression tested on arm-none-eabi, and arm-wince-pe.

gas/ChangeLog:

2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
	    Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/tc-arm.c (arm_ext_cde*): New feature sets for each
	CDE coprocessor that can be enabled.
	(enum pred_instruction_type): New pred type.
	(BAD_NO_VPT): New error message.
	(BAD_CDE): New error message.
	(BAD_CDE_COPROC): New error message.
	(enum operand_parse_code): Add new immediate operands.
	(parse_operands): Account for new immediate operands.
	(check_cde_operand): New.
	(cde_coproc_enabled): New.
	(cde_coproc_pos): New.
	(cde_handle_coproc): New.
	(cxn_handle_predication): New.
	(do_custom_instruction_1): New.
	(do_custom_instruction_2): New.
	(do_custom_instruction_3): New.
	(do_cx1): New.
	(do_cx1a): New.
	(do_cx1d): New.
	(do_cx1da): New.
	(do_cx2): New.
	(do_cx2a): New.
	(do_cx2d): New.
	(do_cx2da): New.
	(do_cx3): New.
	(do_cx3a): New.
	(do_cx3d): New.
	(do_cx3da): New.
	(handle_pred_state): Define new IT block behaviour.
	(insns): Add newn CX*{,d}{,a} instructions.
	(CDE_EXTENSIONS,armv8m_main_ext_table,armv8_1m_main_ext_table):
	Define new cdecp extension strings.
	* doc/c-arm.texi: Document new cdecp extension arguments.
	* testsuite/gas/arm/cde-scalar.d: New test.
	* testsuite/gas/arm/cde-scalar.s: New test.
	* testsuite/gas/arm/cde-warnings.d: New test.
	* testsuite/gas/arm/cde-warnings.l: New test.
	* testsuite/gas/arm/cde-warnings.s: New test.
	* testsuite/gas/arm/cde.d: New test.
	* testsuite/gas/arm/cde.s: New test.

include/ChangeLog:

2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
	    Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/arm.h (ARM_EXT2_CDE): New extension macro.
	(ARM_EXT2_CDE0): New extension macro.
	(ARM_EXT2_CDE1): New extension macro.
	(ARM_EXT2_CDE2): New extension macro.
	(ARM_EXT2_CDE3): New extension macro.
	(ARM_EXT2_CDE4): New extension macro.
	(ARM_EXT2_CDE5): New extension macro.
	(ARM_EXT2_CDE6): New extension macro.
	(ARM_EXT2_CDE7): New extension macro.

opcodes/ChangeLog:

2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
	    Matthew Malcomson  <matthew.malcomson@arm.com>

	* arm-dis.c (struct cdeopcode32): New.
	(CDE_OPCODE): New macro.
	(cde_opcodes): New disassembly table.
	(regnames): New option to table.
	(cde_coprocs): New global variable.
	(print_insn_cde): New
	(print_insn_thumb32): Use print_insn_cde.
	(parse_arm_disassembler_options): Parse coprocN args.
2020-02-10 16:50:14 +00:00
Alan Modra
2bddb71a74 ubsan: arm: out of bounds array access
.inst 0x81bdfe9f

disassembles as
   0:	81bdfe9f 	ldaexdhi	pc, reg-names-std, [sp]

I'm quite sure "reg-names-std" isn't an ARM register.

	* arm-dis.c (print_insn_arm): Wrap 'T' value.
2020-01-20 15:45:50 +10:30
Andre Vieira
2da2eaf4ce [binutils][arm] PR25376 Change MVE into a CORE_HIGH feature
This patch moves MVE feature bits into the CORE_HIGH section.  This makes sure
.fpu and -mfpu does not reset the bits set by MVE. This is important because
.fpu has no option to "set" these same bits and thus, mimic'ing GCC, we choose
to define MVE as an architecture extension rather than put it together with
other the legacy fpu features.

This will enable the following behavior:
.arch armv8.1-m.main
.arch mve
.fpu fpv5-sp-d16               #does not disable mve.
vadd.i32 q0, q1, q2

This patch also makes sure MVE is not taken into account during auto-detect.
This was already the case, but because we moved the MVE bits to the
architecture feature space we must make sure ARM_ANY does not include MVE.

gas/ChangeLog:
2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	PR 25376
	* config/tc-arm.c (mve_ext, mve_fp_ext): Use CORE_HIGH.
	(armv8_1m_main_ext_table): Use CORE_HIGH for mve.
	* testsuite/arm/armv8_1-m-fpu-mve-1.s: New.
	* testsuite/arm/armv8_1-m-fpu-mve-1.d: New.
	* testsuite/arm/armv8_1-m-fpu-mve-2.s: New.
	* testsuite/arm/armv8_1-m-fpu-mve-2.d: New.

include/ChangeLog:
2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	PR 25376
	* opcodes/arm.h (FPU_MVE, FPU_MVE_FPU): Move these features to...
	(ARM_EXT2_MVE, ARM_EXT2_MVE_FP): ... the CORE_HIGH space.
	(ARM_ANY): Redefine to not include any MVE bits.
	(ARM_FEATURE_ALL): Removed.

opcodes/ChangeLog:
2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	PR 25376
	* opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
	(neon_opcodes): Likewise.
	(select_arm_features): Make sure we enable MVE bits when selecting
	armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
	any architecture.
2020-01-16 14:33:01 +00:00
Thomas Troeger
1d67fe3b6e Add an option to objdump's disassembler to generate ascii art diagrams showing the destinations of flow control instructions.
binutils* objdump.c (visualize_jumps, color_output, extended_color_output)
	(detected_jumps): New variables.
	(usage): Add the new jump visualization options.
	(option_values): Add new option value.
	(long_options): Add the new option.
	(jump_info_new, jump_info_free): New functions.
	(jump_info_min_address, jump_info_max_address): Likewise.
	(jump_info_end_address, jump_info_is_start_address): Likewise.
	(jump_info_is_end_address, jump_info_size): Likewise.
	(jump_info_unlink, jump_info_insert): Likewise.
	(jump_info_add_front, jump_info_move_linked): Likewise.
	(jump_info_intersect, jump_info_merge): Likewise.
	(jump_info_sort, jump_info_visualize_address): Likewise.
	(disassemble_jumps): New function - used to locate jumps.
	(disassemble_bytes): Add ascii art generation.
	(disassemble_section): Add scan to locate jumps.
	(main): Parse the new visualization option.
	* doc/binutils.texi: Document the new feature.
	* NEWS: Mention the new feature.

opcodes	* arm-dis.c (print_insn_arm): Fill in insn info fields for control
	flow instructions.
	(print_insn_thumb16, print_insn_thumb32): Likewise.
	(print_insn): Initialize the insn info.
	* i386-dis.c (print_insn): Initialize the insn info fields, and
	detect jumps.
2020-01-13 12:36:55 +00:00
Alan Modra
b3adc24a07 Update year range in copyright notice of binutils files 2020-01-01 18:42:54 +10:30
Alan Modra
ebd1c6d1d3 ubsan: arm: shift exponent 32 is too large for 32-bit type 'unsigned int'
* arm-dis.c (print_insn_arm): Don't shift by 32 on unsigned int var.
2019-12-24 12:01:42 +10:30
Alan Modra
2480b6fa94 More signed overflow fixes
The arc fix in create_map avoiding signed overflow by casting an
unsigned char to unsigned int before shifting, shows one of the
dangers of blinding doing that.  The problem in this case was that the
variable storing the value, newAuxRegister->address, was a long.
Using the unsigned cast meant that the 32-bit value was zero extended
when long is 64 bits.  Previously we had a sign extension.  Net result
was that comparisons in arcExtMap_auxRegName didn't match.  Of course,
I could have cast the 32-bit unsigned value back to signed before
storing in a long, but it's neater to just use an unsigned int for the
address.

opcodes/
	* alpha-opc.c (OP): Avoid signed overflow.
	* arm-dis.c (print_insn): Likewise.
	* mcore-dis.c (print_insn_mcore): Likewise.
	* pj-dis.c (get_int): Likewise.
	* ppc-opc.c (EBD15, EBD15BI): Likewise.
	* score7-dis.c (s7_print_insn): Likewise.
	* tic30-dis.c (print_insn_tic30): Likewise.
	* v850-opc.c (insert_SELID): Likewise.
	* vax-dis.c (print_insn_vax): Likewise.
	* arc-ext.c (create_map): Likewise.
	(struct ExtAuxRegister): Make "address" field unsigned int.
	(arcExtMap_auxRegName): Pass unsigned address.
	(dump_ARC_extmap): Adjust.
	* arc-ext.h (arcExtMap_auxRegName): Update prototype.
2019-12-18 18:38:13 +10:30
Mihail Ionescu
8b301fbb61 Arm: Change CRC from fpu feature to archititectural extension
This patch changes the CRC extension to use the core feature bits instead
of the coproc/fpu feature bits.
CRC is not an fpu feature and it causes issues with the new fpu reset
patch (f439988037). CRC can be set using
the '.arch_extension' directive, which sets bits in the coproc bitfield. When
a '.fpu' directive is encountered, the CRC feature bit gets removed and
there is no way to set it back using '.fpu'.
With this patch, CRC will be marked in the feature core bits, which prevents
it from getting removed when setting/changing the fpu options.

gas/ChangeLog:

	* config/tc-arm.c (arm_ext_crc): New.
	(crc_ext_armv8): Remove.
	(insns): Rename crc_ext_armv8 to arm_ext_crc.
	(arm_cpus): Replace CRC_EXT_ARMV8 with ARM_EXT2_CRC.
	(armv8a_ext_table, armv8r_ext_table,
	arm_option_extension_value_table): Redefine the crc
	extension in terms of ARM_EXT2_CRC.
	* gas/testsuite/gas/arm/crc-ext.s: New.
	* gas/testsuite/gas/arm/crc-ext.d: New.

include/ChangeLog:

	* opcode/arm.h (ARM_EXT2_CRC): New extension feature
	to replace CRC_EXT_ARMV8.
	(CRC_EXT_ARMV8): Remove and mark bit as unused.
	(ARM_ARCH_V8A_CRC, ARM_ARCH_V8_1A, ARM_ARCH_V8_2A,
	ARM_ARCH_V8_3A, ARM_ARCH_V8_4A, ARM_ARCH_V8_5A,
	ARM_ARCH_V8_6A): Redefine using ARM_EXT2_CRC instead of
	CRC_EXT_ARMV8.

opcodes/ChangeLog:

	* opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
	Change the coproc CRC conditions to use the extension
	feature set, second word, base on ARM_EXT2_CRC.
2019-11-22 13:47:26 +00:00
Mihail Ionescu
ce760a7620 [binutils][arm] Update the decoding of MVE VMOV, VMVN
This patch updates the decoding of the VMOV and VMVN instructions which depend on cmode.
Previously VMOV and VMVN with cmode 1101 were not allowed.
The cmode changes also required updating of the MVE conflict checking.
Now instructions with opcodes 0xef800d50 and 0xef800e70 correctly get decoded as VMOV
and VMVN, respectively.

2019-11-12  Mihail Ionescu  <mihail.ionescu@arm.com>

	* opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
	cmode 1101.
	(is_mve_encoding_conflict): Update cmode conflict checks for
	MVE_VMVN_IMM.

2019-11-12  Mihail Ionescu  <mihail.ionescu@arm.com>

	* gas/config/tc-arm.c (do_neon_mvn): Allow mve_ext cmode=0xd.
	* testsuite/gas/arm/mve-vmov-vmvn-vorr-vbic.s: New test.
	* testsuite/gas/arm/mve-vmov-vmvn-vorr-vbic.d: Likewise.
2019-11-12 14:01:04 +00:00
Matthew Malcomson
616ce08e1c [Patch][binutils][arm] Armv8.6-A Matrix Multiply extension [9/10]
Hi,

This patch is part of a series that adds support for Armv8.6-A
(Matrix Multiply and BFloat16 extensions) to binutils.

This patch introduces the Matrix Multiply (Int8, F32, F64) extensions
to the arm backend.

The following Matrix Multiply instructions are added: vummla, vsmmla,
vusmmla, vusdot, vsudot[1].

[1]https://developer.arm.com/docs/ddi0597/latest/simd-and-floating-point-instructions-alphabetic-order

Committed on behalf of Mihail Ionescu.

gas/ChangeLog:

2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>

	* config/tc-arm.c (arm_ext_i8mm): New feature set.
	(do_vusdot): New.
	(do_vsudot): New.
	(do_vsmmla): New.
	(do_vummla): New.
	(insns): Add vsmmla, vummla, vusmmla, vusdot, vsudot mnemonics.
	(armv86a_ext_table): Add i8mm extension.
	(arm_extensions): Move bf16 extension to context sensitive table.
	(armv82a_ext_table, armv84a_ext_table, armv85a_ext_table):
	Move bf16 extension to context sensitive table.
	(armv86a_ext_table): Add i8mm extension.
	* doc/c-arm.texi: Document i8mm extension.
	* testsuite/gas/arm/i8mm.s: New test.
	* testsuite/gas/arm/i8mm.d: New test.
	* testsuite/gas/arm/bfloat17-cmdline-bad-3.d: Update test.

include/ChangeLog:

2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>

	* opcode/arm.h (ARM_EXT2_I8MM): New feature macro.

opcodes/ChangeLog:

2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>

	* arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.

Regression tested on arm-none-eabi.
Is this ok for trunk?

Regards,
Mihail
2019-11-07 17:20:08 +00:00
Matthew Malcomson
aab2c27d9f [binutils][arm] BFloat16 enablement [4/X]
Hi,

This patch is part of a series that adds support for Armv8.6-A
(Matrix Multiply and BFloat16 extensions) to binutils.

This patch introduces BFloat16 instructions to the arm backend.
The following BFloat16 instructions are added: vdot, vfma{l/t},
vmmla, vfmal{t/b}, vcvt, vcvt{t/b}.

gas/ChangeLog:

2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/tc-arm.c (arm_archs): Add armv8.6-a option.
	(cpu_arch_ver): Add TAG_CPU_ARCH_V8 tag for Armv8.6-a.
	* doc/c-arm.texi (-march): New armv8.6-a arch.
	* config/tc-arm.c (arm_ext_bf16): New feature set.
	(enum neon_el_type): Add NT_bfloat value.
	(B_MNEM_vfmat, B_MNEM_vfmab): New bfloat16 encoder
	helpers.
	(BAD_BF16): New message.
	(parse_neon_type): Add bf16 type specifier.
	(enum neon_type_mask): Add N_BF16 type.
	(type_chk_of_el_type): Account for NT_bfloat.
	(el_type_of_type_chk): Account for N_BF16.
	(neon_three_args): Split out from neon_three_same.
	(neon_three_same): Part split out into neon_three_args.
	(CVT_FLAVOUR_VAR): Add bf16_f32 cvt flavour.
	(do_neon_cvt_1): Account for vcvt.bf16.f32.
	(do_bfloat_vmla): New.
	(do_mve_vfma): New function to deal with the mnemonic clash between the BF16
	vfmat and the MVE vfma in a VPT block with a 't'rue condition.
	(do_neon_cvttb_1): Account for vcvt{t,b}.bf16.f32.
	(do_vdot): New
	(do_vmmla): New
	(insns): Add vdot and vmmla mnemonics.
	(arm_extensions): Add "bf16" extension.
	* doc/c-arm.texi: Document "bf16" extension.
	* testsuite/gas/arm/attr-march-armv8_6-a.d: New test.
	* testsuite/gas/arm/bfloat16-bad.d: New test.
	* testsuite/gas/arm/bfloat16-bad.l: New test.
	* testsuite/gas/arm/bfloat16-bad.s: New test.
	* testsuite/gas/arm/bfloat16-cmdline-bad-2.d: New test.
	* testsuite/gas/arm/bfloat16-cmdline-bad-3.d: New test.
	* testsuite/gas/arm/bfloat16-cmdline-bad.d: New test.
	* testsuite/gas/arm/bfloat16-neon.s: New test.
	* testsuite/gas/arm/bfloat16-non-neon.s: New test.
	* testsuite/gas/arm/bfloat16-thumb-bad.d: New test.
	* testsuite/gas/arm/bfloat16-thumb-bad.l: New test.
	* testsuite/gas/arm/bfloat16-thumb.d: New test.
	* testsuite/gas/arm/bfloat16-vfp.d: New test.
	* testsuite/gas/arm/bfloat16.d: New test.
	* testsuite/gas/arm/bfloat16.s: New test.

include/ChangeLog:

2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/arm.h (ARM_EXT2_V8_6A, ARM_AEXT2_V8_6A,
	ARM_ARCH_V8_6A): New.
	* opcode/arm.h (ARM_EXT2_BF16): New feature macro.
	(ARM_AEXT2_V8_6A): Include above macro in definition.

opcodes/ChangeLog:

2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>

	* arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
	Armv8.6-A.
	(coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
	(neon_opcodes): Add bfloat SIMD instructions.
	(print_insn_coprocessor): Add new control character %b to print
	condition code without checking cp_num.
	(print_insn_neon): Account for BFloat16 instructions that have no
	special top-byte handling.

Regression tested on arm-none-eabi.

Is it ok for trunk?

Regards,
Mihail
2019-11-07 16:56:12 +00:00
Matthew Malcomson
33593eafc9 [Patch][binutils][arm] Create a new generic coprocessor array [3/10]
Hi,

This patch is part of a series that adds support for Armv8.6-A
(Matrix Multiply and BFloat16 extensions) to binutils.

Some generic instructions match a large range of encoding space (e.g.
stc, mcr, mrc).
Currently these instructions are in the coprocessor_opcodes array, which
means they are checked before many other instructions when disassembling
arm and thumb32 codes.

This patch moves the generic instructions into a separate array to be
checked later on.
This is done in order to avoid instruction conflict between the generic
instructions and newer ones -- this has already been seen with MVE, and
is also a problem with BFloat16.

One way to avoid the conflict could be to swap the search order between
coprocessor_opcodes and neon_opcodes.
We avoid this since it's a larger change that may introduce extra bugs
(that aren't caught by the testsuite).

We have decided against searching the generic array after searching the
arm specific and thumb32 specific arrays with a similar reasoning about
keeping the change small.

Regression tested with arm-none-linux-gnueabihf.

Committed on behalf of Mihail Ionescu.

opcodes/ChangeLog:

2019-10-29  Mihail Ionescu  <mihail.ionescu@arm.com>
2019-10-29  Matthew Malcomson  <matthew.malcomson@arm.com>

	* arm-dis.c (print_insn_coprocessor,
	print_insn_generic_coprocessor): Create wrapper functions around
	the implementation of the print_insn_coprocessor control codes.
	(print_insn_coprocessor_1): Original print_insn_coprocessor
	function that now takes which array to look at as an argument.
	(print_insn_arm): Use both print_insn_coprocessor and
	print_insn_generic_coprocessor.
	(print_insn_thumb32): As above.

Is it ok for trunk?

Regards,
Mihail
2019-11-07 16:55:29 +00:00