For sim_fetch_register / sim_store_register: Add LENGTH parameter,
return actual size of register, 0 if not applicable, -1 of legacy implementation.
This commit is contained in:
Andrew Cagney
parent
c5efcf3c85
commit
fbb8b6b9ab
10 changed files with 256 additions and 146 deletions
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@ -1,5 +1,5 @@
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/* Main simulator entry points for the M32R.
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Copyright (C) 1996, 1997 Free Software Foundation, Inc.
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Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
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Contributed by Cygnus Support.
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This program is free software; you can redistribute it and/or modify
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@ -24,14 +24,49 @@ with this program; if not, write to the Free Software Foundation, Inc.,
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#include "libiberty.h"
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#include "bfd.h"
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#include "sim-core.h"
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#include "cpu-sim.h"
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/* Global state until sim_open starts creating and returning it
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[and the other simulator i/f fns take it as an argument]. */
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struct sim_state sim_global_state;
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static SIM_RC alloc_cpu (SIM_DESC, struct _bfd *, char **);
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static void free_state (SIM_DESC);
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/* FIXME: Do we *need* to pass state to the semantic routines? */
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STATE current_state;
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/* Records simulator descriptor so utilities like m32r_dump_regs can be
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called from gdb. */
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SIM_DESC current_state;
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/* Scan the args and bfd to see what kind of cpus are in use and allocate
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space for them. */
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static SIM_RC
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alloc_cpu (SIM_DESC sd, struct _bfd *abfd, char **argv)
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{
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/* Compute the size of the SIM_CPU struct.
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For now its the max of all the possible sizes. */
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int size = 0;
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const MACH *mach;
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for (mach = &machs[0]; MACH_NAME (mach) != NULL; ++mach)
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{
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int mach_size = IMP_PROPS_SIM_CPU_SIZE (MACH_IMP_PROPS (mach));
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size = mach_size > size ? mach_size : size;
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}
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if (size == 0)
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abort ();
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/* `sizeof (SIM_CPU)' is the size of the generic part, and `size' is the
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size of the cpu-specific part. */
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STATE_CPU (sd, 0) = zalloc (sizeof (SIM_CPU) + size);
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return SIM_RC_OK;
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}
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/* Cover function of sim_state_free to free the cpu buffers as well. */
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static void
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free_state (SIM_DESC sd)
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{
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if (STATE_CPU (sd, 0))
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zfree (STATE_CPU (sd, 0));
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sim_state_free (sd);
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}
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/* Create an instance of the simulator. */
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@ -42,16 +77,20 @@ sim_open (kind, callback, abfd, argv)
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struct _bfd *abfd;
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char **argv;
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{
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int i;
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SIM_DESC sd = &sim_global_state;
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SIM_DESC sd = sim_state_alloc (kind, callback);
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/* FIXME: until we alloc one, use the global. */
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memset (sd, 0, sizeof (sim_global_state));
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STATE_OPEN_KIND (sd) = kind;
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STATE_CALLBACK (sd) = callback;
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/* The cpu data is kept in a separately allocated chunk of memory. */
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if (alloc_cpu (sd, abfd, argv) != SIM_RC_OK)
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{
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free_state (sd);
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return 0;
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}
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if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
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return 0;
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{
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free_state (sd);
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return 0;
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}
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#if 0 /* FIXME: 'twould be nice if we could do this */
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/* These options override any module options.
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@ -61,34 +100,72 @@ sim_open (kind, callback, abfd, argv)
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sim_add_option_table (sd, extra_options);
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#endif
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/* Allocate core managed memory */
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sim_do_commandf (sd, "memory region 0,0x%lx", M32R_DEFAULT_MEM_SIZE);
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/* Allocate a handler for the MSPR register. */
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sim_core_attach (sd, NULL,
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0 /*level*/,
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access_write,
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0 /*space ???*/,
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MSPR_ADDR, 1 /*nr_bytes*/, 0 /*modulo*/,
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&m32r_mspr_device,
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NULL /*buffer*/);
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/* getopt will print the error message so we just have to exit if this fails.
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FIXME: Hmmm... in the case of gdb we need getopt to call
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print_filtered. */
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if (sim_parse_args (sd, argv) != SIM_RC_OK)
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{
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sim_module_uninstall (sd);
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free_state (sd);
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return 0;
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}
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/* check for/establish the a reference program image */
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if (sim_analyze_program (sd,
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(STATE_PROG_ARGV (sd) != NULL
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? *STATE_PROG_ARGV (sd)
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: NULL),
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abfd) != SIM_RC_OK)
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{
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sim_module_uninstall (sd);
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free_state (sd);
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return 0;
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}
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/* Establish any remaining configuration options. */
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if (sim_config (sd) != SIM_RC_OK)
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{
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sim_module_uninstall (sd);
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free_state (sd);
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return 0;
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}
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if (sim_post_argv_init (sd) != SIM_RC_OK)
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{
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sim_module_uninstall (sd);
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free_state (sd);
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return 0;
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}
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/* Initialize various cgen things not done by common framework. */
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cgen_init (sd);
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/* FIXME:wip */
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sim_core_attach (sd, NULL, attach_raw_memory, access_read_write_exec,
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0, 0, M32R_DEFAULT_MEM_SIZE, 0, NULL, NULL);
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{
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int i;
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/* Only needed for profiling, but the structure member is small. */
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for (i = 0; i < MAX_NR_PROCESSORS; ++i)
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memset (& CPU_M32R_PROFILE (STATE_CPU (sd, i)), 0,
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sizeof (CPU_M32R_PROFILE (STATE_CPU (sd, i))));
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/* Only needed for profiling, but the structure member is small. */
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for (i = 0; i < MAX_NR_PROCESSORS; ++i)
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memset (& CPU_M32R_MISC_PROFILE (STATE_CPU (sd, i)), 0,
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sizeof (CPU_M32R_MISC_PROFILE (STATE_CPU (sd, i))));
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}
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return &sim_global_state;
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/* Store in a global so things like sparc32_dump_regs can be invoked
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from the gdb command line. */
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current_state = sd;
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return sd;
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}
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void
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@ -98,7 +175,7 @@ sim_close (sd, quitting)
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{
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sim_module_uninstall (sd);
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}
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SIM_RC
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sim_create_inferior (sd, abfd, argv, envp)
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SIM_DESC sd;
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@ -106,21 +183,41 @@ sim_create_inferior (sd, abfd, argv, envp)
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char **argv;
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char **envp;
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{
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SIM_CPU *current_cpu = STATE_CPU (sd, 0);
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SIM_ADDR addr;
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SI taddr;
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if (abfd != NULL)
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addr = bfd_get_start_address (abfd);
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else
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addr = 0;
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taddr = endian_h2t_4 (addr);
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sim_store_register (sd, PC_REGNUM, (unsigned char *) &taddr, 4);
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#if 0
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STATE_ARGV (sd) = sim_copy_argv (argv);
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STATE_ENVP (sd) = sim_copy_argv (envp);
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#endif
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if (abfd != NULL)
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STATE_CPU_CPU (sd, 0)->pc = bfd_get_start_address (abfd);
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else
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STATE_CPU_CPU (sd, 0)->pc = 0;
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return SIM_RC_OK;
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}
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int
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sim_stop (SIM_DESC sd)
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{
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return engine_stop (sd);
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switch (STATE_ARCHITECTURE (sd)->mach)
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{
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case bfd_mach_m32r :
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return m32r_engine_stop (sd);
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/* start-sanitize-m32rx */
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#ifdef HAVE_CPU_M32RX
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case bfd_mach_m32rx :
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return m32rx_engine_stop (sd);
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#endif
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/* end-sanitize-m32rx */
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default :
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abort ();
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}
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}
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void
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@ -128,32 +225,20 @@ sim_resume (sd, step, siggnal)
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SIM_DESC sd;
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int step, siggnal;
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{
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engine_run (sd, step, siggnal);
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}
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void
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sim_stop_reason (sd, reason, sigrc)
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SIM_DESC sd;
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enum sim_stop *reason;
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int *sigrc;
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{
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sim_cpu *cpu = STATE_CPU (sd, 0);
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/* Map sim_state to sim_stop. */
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switch (CPU_EXEC_STATE (cpu))
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switch (STATE_ARCHITECTURE (sd)->mach)
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{
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case EXEC_STATE_EXITED :
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*reason = sim_exited;
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*sigrc = CPU_HALT_SIGRC (cpu);
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case bfd_mach_m32r :
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m32r_engine_run (sd, step, siggnal);
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break;
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case EXEC_STATE_STOPPED :
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*reason = sim_stopped;
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*sigrc = sim_signal_to_host (CPU_HALT_SIGRC (cpu));
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break;
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case EXEC_STATE_SIGNALLED :
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*reason = sim_signalled;
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*sigrc = sim_signal_to_host (CPU_HALT_SIGRC (cpu));
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/* start-sanitize-m32rx */
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#ifdef HAVE_CPU_M32RX
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case bfd_mach_m32rx :
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m32rx_engine_run (sd, step, siggnal);
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break;
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#endif
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/* end-sanitize-m32rx */
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default :
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abort ();
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}
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}
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@ -171,7 +256,7 @@ print_m32r_misc_cpu (SIM_CPU *cpu, int verbose)
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sim_io_printf (sd, " %-*s %s\n\n",
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PROFILE_LABEL_WIDTH, "Fill nops:",
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sim_add_commas (buf, sizeof (buf),
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CPU_M32R_PROFILE (cpu).fillnop_count));
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CPU_M32R_MISC_PROFILE (cpu).fillnop_count));
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}
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}
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@ -185,101 +270,56 @@ sim_info (sd, verbose)
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/* The contents of BUF are in target byte order. */
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void
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sim_fetch_register (sd, rn, buf)
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int
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sim_fetch_register (sd, rn, buf, length)
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SIM_DESC sd;
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int rn;
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unsigned char *buf;
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int length;
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{
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if (rn < 16)
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SETTWI (buf, STATE_CPU_CPU (sd, 0)->h_gr[rn]);
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else if (rn < 21)
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SETTWI (buf, STATE_CPU_CPU (sd, 0)->h_cr[rn - 16]);
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else switch (rn) {
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case PC_REGNUM:
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SETTWI (buf, STATE_CPU_CPU (sd, 0)->pc);
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switch (STATE_ARCHITECTURE (sd)->mach)
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{
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case bfd_mach_m32r :
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m32r_fetch_register (sd, rn, buf);
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break;
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case ACCL_REGNUM:
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SETTWI (buf, GETLODI (STATE_CPU_CPU (sd, 0)->h_accum));
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/* start-sanitize-m32rx */
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#ifdef HAVE_CPU_M32RX
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case bfd_mach_m32rx :
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m32rx_fetch_register (sd, rn, buf);
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break;
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case ACCH_REGNUM:
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SETTWI (buf, GETHIDI (STATE_CPU_CPU (sd, 0)->h_accum));
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break;
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#if 0
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case 23: *reg = STATE_CPU_CPU (sd, 0)->h_cond; break;
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case 24: *reg = STATE_CPU_CPU (sd, 0)->h_sm; break;
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case 25: *reg = STATE_CPU_CPU (sd, 0)->h_bsm; break;
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case 26: *reg = STATE_CPU_CPU (sd, 0)->h_ie; break;
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case 27: *reg = STATE_CPU_CPU (sd, 0)->h_bie; break;
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case 28: *reg = STATE_CPU_CPU (sd, 0)->h_bcarry; break; /* rename: bc */
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case 29: memcpy (buf, &STATE_CPU_CPU (sd, 0)->h_bpc, sizeof(WI)); break; /* duplicate */
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#endif
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default: abort ();
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}
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/* end-sanitize-m32rx */
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default :
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abort ();
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}
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return -1;
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}
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/* The contents of BUF are in target byte order. */
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void
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sim_store_register (sd, rn, buf)
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int
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sim_store_register (sd, rn, buf, length)
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SIM_DESC sd;
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int rn;
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unsigned char *buf;
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int length;
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{
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if (rn < 16)
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STATE_CPU_CPU (sd, 0)->h_gr[rn] = GETTWI (buf);
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else if (rn < 21)
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STATE_CPU_CPU (sd, 0)->h_cr[rn - 16] = GETTWI (buf);
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else switch (rn) {
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case PC_REGNUM:
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STATE_CPU_CPU (sd, 0)->pc = GETTWI (buf);
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switch (STATE_ARCHITECTURE (sd)->mach)
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{
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case bfd_mach_m32r :
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m32r_store_register (sd, rn, buf);
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break;
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case ACCL_REGNUM:
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SETLODI (STATE_CPU_CPU (sd, 0)->h_accum, GETTWI (buf));
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/* start-sanitize-m32rx */
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#ifdef HAVE_CPU_M32RX
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case bfd_mach_m32rx :
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m32rx_store_register (sd, rn, buf);
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break;
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case ACCH_REGNUM:
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SETHIDI (STATE_CPU_CPU (sd, 0)->h_accum, GETTWI (buf));
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break;
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#if 0
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case 23: STATE_CPU_CPU (sd, 0)->h_cond = *reg; break;
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case 24: STATE_CPU_CPU (sd, 0)->h_sm = *reg; break;
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case 25: STATE_CPU_CPU (sd, 0)->h_bsm = *reg; break;
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case 26: STATE_CPU_CPU (sd, 0)->h_ie = *reg; break;
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case 27: STATE_CPU_CPU (sd, 0)->h_bie = *reg; break;
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case 28: STATE_CPU_CPU (sd, 0)->h_bcarry = *reg; break; /* rename: bc */
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case 29: memcpy (&STATE_CPU_CPU (sd, 0)->h_bpc, buf, sizeof(DI)); break; /* duplicate */
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#endif
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}
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}
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int
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sim_read (sd, addr, buf, len)
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SIM_DESC sd;
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SIM_ADDR addr;
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unsigned char *buf;
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int len;
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{
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#if 1
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return sim_core_read_buffer (sd, NULL, sim_core_read_map,
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buf, addr, len);
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#else
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return (*STATE_MEM_READ (sd)) (sd, addr, buf, len);
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#endif
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}
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int
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sim_write (sd, addr, buf, len)
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SIM_DESC sd;
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SIM_ADDR addr;
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unsigned char *buf;
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int len;
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{
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#if 1
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return sim_core_write_buffer (sd, NULL, sim_core_write_map,
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buf, addr, len);
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#else
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return (*STATE_MEM_WRITE (sd)) (sd, addr, buf, len);
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#endif
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/* end-sanitize-m32rx */
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default :
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abort ();
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}
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return -1;
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}
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void
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@ -287,5 +327,17 @@ sim_do_command (sd, cmd)
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SIM_DESC sd;
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char *cmd;
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{
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sim_io_error (sd, "sim_do_command - unimplemented");
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if (sim_args_command (sd, cmd) != SIM_RC_OK)
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sim_io_eprintf (sd, "Unknown command `%s'\n", cmd);
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}
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/* The semantic code invokes this for illegal (unrecognized) instructions. */
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void
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sim_engine_illegal_insn (current_cpu, pc)
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SIM_CPU *current_cpu;
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PCADDR pc;
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{
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sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc,
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sim_stopped, SIM_SIGILL);
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}
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