[AArch64] Fix off by one error in instruction relaxation mask.
The AArch64 TLSDESC to IE relaxation code uses a bit mask intended to ensure that destination register in a relaxed ldr instruction is always X0. The mask has an off by one error resulting in the most significant bit of the destination register being retained in the relaxed instruction. The issue generally appears when the compiler emits TLS accesses code under high register pressure resulting in a broken code sequence.
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4 changed files with 11 additions and 2 deletions
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@ -1,3 +1,7 @@
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2014-04-15 Marcus Shawcroft <marcus.shawcroft@arm.com>
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* (elfNN_aarch64_tls_relax): Fix instruction mask.
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2014-04-14 Alan Modra <amodra@gmail.com>
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* elf32-ppc.c (BA): Define
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@ -3957,7 +3957,7 @@ elfNN_aarch64_tls_relax (struct elf_aarch64_link_hash_table *globals,
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ldr xd, [x0, #:tlsdesc_lo12:var] => ldr x0, [x0, #:gottprel_lo12:var]
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*/
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insn = bfd_getl32 (contents + rel->r_offset);
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insn &= 0xfffffff0;
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insn &= 0xffffffe0;
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bfd_putl32 (insn, contents + rel->r_offset);
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return bfd_reloc_continue;
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}
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@ -1,3 +1,8 @@
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2014-04-15 Marcus Shawcroft <marcus.shawcroft@arm.com>
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* ld-aarch64/tls-relax-gdesc-ie.s (var): Adjust test case
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to include all 5 bits of LDR destination register.
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2014-04-10 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
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* ld-avr/norelax_diff.d: New testcase.
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@ -4,7 +4,7 @@ var:
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.word 2
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.text
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adrp x0, :tlsdesc:var
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ldr x1, [x0, #:tlsdesc_lo12:var]
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ldr x17, [x0, #:tlsdesc_lo12:var]
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add x0, x0, :tlsdesc_lo12:var
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.tlsdesccall var
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blr x1
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