x86: convert RegMask and RegBND from bitfield to enumerator
This is to further shrink the operand type representation.
This commit is contained in:
Jan Beulich
parent
3528c362d9
commit
f74a630727
9 changed files with 14617 additions and 14596 deletions
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@ -1,3 +1,9 @@
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2019-11-08 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (optimize_encoding, build_modrm_byte,
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check_VecOperations, parse_real_register): Use "class" instead
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of "regmask" and "regbnd" fields.
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2019-11-08 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (match_mem_size, operand_size_match,
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@ -4154,7 +4154,7 @@ optimize_encoding (void)
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else
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return;
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}
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else if (i.tm.operand_types[0].bitfield.regmask)
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else if (i.tm.operand_types[0].bitfield.class == RegMask)
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{
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i.tm.base_opcode &= 0xff;
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i.tm.opcode_modifier.vexw = VEXW0;
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@ -7682,8 +7682,8 @@ build_modrm_byte (void)
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for (op = 0; op < i.operands; op++)
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{
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if (i.types[op].bitfield.class == Reg
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|| i.types[op].bitfield.regbnd
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|| i.types[op].bitfield.regmask
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|| i.types[op].bitfield.class == RegBND
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|| i.types[op].bitfield.class == RegMask
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|| i.types[op].bitfield.class == SReg
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|| i.types[op].bitfield.class == RegCR
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|| i.types[op].bitfield.class == RegDR
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@ -9238,7 +9238,7 @@ check_VecOperations (char *op_string, char *op_end)
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else if ((mask = parse_register (op_string, &end_op)) != NULL)
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{
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/* k0 can't be used for write mask. */
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if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
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if (mask->reg_type.bitfield.class != RegMask || !mask->reg_num)
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{
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as_bad (_("`%s%s' can't be used for write mask"),
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register_prefix, mask->reg_name);
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@ -10935,7 +10935,8 @@ parse_real_register (char *reg_string, char **end_op)
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if (!cpu_arch_flags.bitfield.cpuavx512f)
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{
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if (r->reg_type.bitfield.zmmword || r->reg_type.bitfield.regmask)
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if (r->reg_type.bitfield.zmmword
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|| r->reg_type.bitfield.class == RegMask)
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return (const reg_entry *) NULL;
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if (!cpu_arch_flags.bitfield.cpuavx)
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@ -10948,7 +10949,7 @@ parse_real_register (char *reg_string, char **end_op)
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}
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}
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if (r->reg_type.bitfield.regbnd && !cpu_arch_flags.bitfield.cpumpx)
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if (r->reg_type.bitfield.class == RegBND && !cpu_arch_flags.bitfield.cpumpx)
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return (const reg_entry *) NULL;
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/* Don't allow fake index register unless allow_index_reg isn't 0. */
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@ -1,3 +1,18 @@
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2019-11-08 Jan Beulich <jbeulich@suse.com>
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* i386-gen.c (operand_type_init): Add Class= to
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OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
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OPERAND_TYPE_REGBND entry.
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(operand_classes): Add RegMask and RegBND entries.
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(operand_types): Drop RegMask and RegBND entry.
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* i386-opc.h (enum operand_class): Add RegMask and RegBND.
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(RegMask, RegBND): Delete.
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(union i386_operand_type): Remove regmask and regbnd fields.
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* i386-opc.tbl (RegMask, RegBND): Define.
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* i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
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Class=RegBND.
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* i386-init.h, i386-tbl.h: Re-generate.
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2019-11-08 Jan Beulich <jbeulich@suse.com>
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* i386-gen.c (operand_type_init): Add Class= to
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@ -448,7 +448,9 @@ static initializer operand_type_init[] =
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{ "OPERAND_TYPE_REGZMM",
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"Class=RegSIMD|Zmmword" },
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{ "OPERAND_TYPE_REGMASK",
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"RegMask" },
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"Class=RegMask" },
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{ "OPERAND_TYPE_REGBND",
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"Class=RegBND" },
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{ "OPERAND_TYPE_ESSEG",
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"EsSeg" },
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{ "OPERAND_TYPE_ACC8",
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@ -481,8 +483,6 @@ static initializer operand_type_init[] =
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"Imm32|Imm32S|Imm64|Disp32|Disp64" },
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{ "OPERAND_TYPE_ANYIMM",
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"Imm1|Imm8|Imm8S|Imm16|Imm32|Imm32S|Imm64" },
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{ "OPERAND_TYPE_REGBND",
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"RegBND" },
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};
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typedef struct bitfield
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@ -689,13 +689,14 @@ static const struct {
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CLASS (RegTR),
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CLASS (RegMMX),
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CLASS (RegSIMD),
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CLASS (RegMask),
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CLASS (RegBND),
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};
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#undef CLASS
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static bitfield operand_types[] =
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{
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BITFIELD (RegMask),
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BITFIELD (Imm1),
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BITFIELD (Imm8),
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BITFIELD (Imm8S),
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@ -725,7 +726,6 @@ static bitfield operand_types[] =
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BITFIELD (Zmmword),
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BITFIELD (Unspecified),
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BITFIELD (Anysize),
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BITFIELD (RegBND),
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#ifdef OTUnused
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BITFIELD (OTUnused),
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#endif
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@ -1365,196 +1365,196 @@
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#define OPERAND_TYPE_NONE \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define OPERAND_TYPE_REG8 \
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{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define OPERAND_TYPE_REG16 \
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{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define OPERAND_TYPE_REG32 \
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{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define OPERAND_TYPE_REG64 \
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{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }
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#define OPERAND_TYPE_IMM1 \
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{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define OPERAND_TYPE_IMM8 \
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{ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define OPERAND_TYPE_IMM8S \
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{ { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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{ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define OPERAND_TYPE_IMM16 \
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{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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{ { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define OPERAND_TYPE_IMM32 \
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{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define OPERAND_TYPE_IMM32S \
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{ { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define OPERAND_TYPE_IMM64 \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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{ { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define OPERAND_TYPE_BASEINDEX \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define OPERAND_TYPE_DISP8 \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define OPERAND_TYPE_DISP16 \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define OPERAND_TYPE_DISP32 \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define OPERAND_TYPE_DISP32S \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define OPERAND_TYPE_DISP64 \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define OPERAND_TYPE_INOUTPORTREG \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define OPERAND_TYPE_SHIFTCOUNT \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define OPERAND_TYPE_CONTROL \
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{ { 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define OPERAND_TYPE_TEST \
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{ { 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define OPERAND_TYPE_DEBUG \
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{ { 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define OPERAND_TYPE_FLOATREG \
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{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
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#define OPERAND_TYPE_FLOATACC \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
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#define OPERAND_TYPE_SREG \
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{ { 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define OPERAND_TYPE_JUMPABSOLUTE \
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define OPERAND_TYPE_REGMMX \
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{ { 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
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#define OPERAND_TYPE_REGXMM \
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{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }
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#define OPERAND_TYPE_REGYMM \
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{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }
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#define OPERAND_TYPE_REGZMM \
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{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }
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0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
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#define OPERAND_TYPE_REGMASK \
|
||||
{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ESSEG \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ACC8 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ACC16 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ACC32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ACC64 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP16_32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ANYDISP \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM16_32 \
|
||||
{ { 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM16_32S \
|
||||
{ { 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM16_32_32S \
|
||||
{ { 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32_64 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32_32S_DISP32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM64_DISP64 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32_32S_64_DISP32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32_32S_64_DISP32_64 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ANYIMM \
|
||||
{ { 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
{ { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REGBND \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } }
|
||||
{ { 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ESSEG \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ACC8 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ACC16 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ACC32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ACC64 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP16_32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ANYDISP \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM16_32 \
|
||||
{ { 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM16_32S \
|
||||
{ { 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM16_32_32S \
|
||||
{ { 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32_64 \
|
||||
{ { 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32_32S_DISP32 \
|
||||
{ { 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM64_DISP64 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32_32S_64_DISP32 \
|
||||
{ { 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32_32S_64_DISP32_64 \
|
||||
{ { 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ANYIMM \
|
||||
{ { 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
|
|
|||
|
|
@ -715,6 +715,8 @@ enum operand_class
|
|||
RegTR, /* Test register */
|
||||
RegMMX, /* MMX register */
|
||||
RegSIMD, /* XMM/YMM/ZMM registers, distinguished by operand size */
|
||||
RegMask, /* Vector Mask register */
|
||||
RegBND, /* Bound register */
|
||||
};
|
||||
|
||||
/* Position of operand_type bits. */
|
||||
|
|
@ -723,8 +725,6 @@ enum
|
|||
{
|
||||
/* Class */
|
||||
Class = CLASS_WIDTH - 1,
|
||||
/* Vector Mask registers */
|
||||
RegMask,
|
||||
/* 1 bit immediate */
|
||||
Imm1,
|
||||
/* 8 bit immediate */
|
||||
|
|
@ -791,9 +791,6 @@ enum
|
|||
/* Any memory size. */
|
||||
Anysize,
|
||||
|
||||
/* Bound register. */
|
||||
RegBND,
|
||||
|
||||
/* The number of bits in i386_operand_type. */
|
||||
OTNum
|
||||
};
|
||||
|
|
@ -812,7 +809,6 @@ typedef union i386_operand_type
|
|||
struct
|
||||
{
|
||||
unsigned int class:CLASS_WIDTH;
|
||||
unsigned int regmask:1;
|
||||
unsigned int imm1:1;
|
||||
unsigned int imm8:1;
|
||||
unsigned int imm8s:1;
|
||||
|
|
@ -842,7 +838,6 @@ typedef union i386_operand_type
|
|||
unsigned int zmmword:1;
|
||||
unsigned int unspecified:1;
|
||||
unsigned int anysize:1;
|
||||
unsigned int regbnd:1;
|
||||
#ifdef OTUnused
|
||||
unsigned int unused:(OTNumOfBits - OTUnused);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -41,6 +41,10 @@
|
|||
#define RegYMM Class=RegSIMD|Ymmword
|
||||
#define RegZMM Class=RegSIMD|Zmmword
|
||||
|
||||
#define RegMask Class=RegMask
|
||||
|
||||
#define RegBND Class=RegBND
|
||||
|
||||
#define Size16 Size=SIZE16
|
||||
#define Size32 Size=SIZE32
|
||||
#define Size64 Size=SIZE64
|
||||
|
|
|
|||
|
|
@ -96,14 +96,14 @@ r13, Class=Reg|Qword|BaseIndex, RegRex, 5, Dw2Inval, 13
|
|||
r14, Class=Reg|Qword|BaseIndex, RegRex, 6, Dw2Inval, 14
|
||||
r15, Class=Reg|Qword|BaseIndex, RegRex, 7, Dw2Inval, 15
|
||||
// Vector mask registers.
|
||||
k0, RegMask, 0, 0, 93, 118
|
||||
k1, RegMask, 0, 1, 94, 119
|
||||
k2, RegMask, 0, 2, 95, 120
|
||||
k3, RegMask, 0, 3, 96, 121
|
||||
k4, RegMask, 0, 4, 97, 122
|
||||
k5, RegMask, 0, 5, 98, 123
|
||||
k6, RegMask, 0, 6, 99, 124
|
||||
k7, RegMask, 0, 7, 100, 125
|
||||
k0, Class=RegMask, 0, 0, 93, 118
|
||||
k1, Class=RegMask, 0, 1, 94, 119
|
||||
k2, Class=RegMask, 0, 2, 95, 120
|
||||
k3, Class=RegMask, 0, 3, 96, 121
|
||||
k4, Class=RegMask, 0, 4, 97, 122
|
||||
k5, Class=RegMask, 0, 5, 98, 123
|
||||
k6, Class=RegMask, 0, 6, 99, 124
|
||||
k7, Class=RegMask, 0, 7, 100, 125
|
||||
// Segment registers.
|
||||
es, Class=SReg, 0, 0, 40, 50
|
||||
cs, Class=SReg, 0, 1, 41, 51
|
||||
|
|
@ -279,10 +279,10 @@ zmm29, Class=RegSIMD|Zmmword, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval
|
|||
zmm30, Class=RegSIMD|Zmmword, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval
|
||||
zmm31, Class=RegSIMD|Zmmword, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval
|
||||
// Bound registers for MPX
|
||||
bnd0, RegBND, 0, 0, Dw2Inval, Dw2Inval
|
||||
bnd1, RegBND, 0, 1, Dw2Inval, Dw2Inval
|
||||
bnd2, RegBND, 0, 2, Dw2Inval, Dw2Inval
|
||||
bnd3, RegBND, 0, 3, Dw2Inval, Dw2Inval
|
||||
bnd0, Class=RegBND, 0, 0, Dw2Inval, Dw2Inval
|
||||
bnd1, Class=RegBND, 0, 1, Dw2Inval, Dw2Inval
|
||||
bnd2, Class=RegBND, 0, 2, Dw2Inval, Dw2Inval
|
||||
bnd3, Class=RegBND, 0, 3, Dw2Inval, Dw2Inval
|
||||
// No Class=Reg will make these registers rejected for all purposes except
|
||||
// for addressing. This saves creating one extra type for RIP/EIP.
|
||||
rip, Qword, RegRex64, RegIP, Dw2Inval, 16
|
||||
|
|
|
|||
28898
opcodes/i386-tbl.h
28898
opcodes/i386-tbl.h
File diff suppressed because it is too large
Load diff
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Add table
Reference in a new issue