PowerPC64: align plt_branch stubs
plt_branch stubs are similar to plt_call stubs in that they branch via bctr. Align them too. bfd/ * elf64-ppc.c (ppc_size_one_stub): Align plt_branch stubs as for plt_call stubs. ld/ * testsuite/ld-powerpc/elfv2exe.d: Adjust for plt_branch changes. * testsuite/ld-powerpc/notoc.d: Likewise. * testsuite/ld-powerpc/notoc.wf: Likewise. * testsuite/ld-powerpc/notoc3.d: Likewise. * testsuite/ld-powerpc/pr23937.d: Likewise.
This commit is contained in:
Alan Modra
parent
0f0d9373a3
commit
f40bb390bb
6 changed files with 78 additions and 67 deletions
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@ -12393,6 +12393,8 @@ ppc_size_one_stub (struct bfd_hash_entry *gen_entry, void *in_arg)
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if (PPC_LO (r2off) != 0)
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size += 4;
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}
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pad = plt_stub_pad (htab->params->plt_stub_align, stub_offset, size);
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stub_offset += pad;
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}
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else if (info->emitrelocations)
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{
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@ -12415,6 +12417,38 @@ ppc_size_one_stub (struct bfd_hash_entry *gen_entry, void *in_arg)
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odd = off & 4;
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off = targ - off;
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if (stub_entry->type.sub == ppc_stub_notoc)
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extra = size_power10_offset (off, odd);
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else
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extra = size_offset (off - 8);
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/* Include branch insn plus those in the offset sequence. */
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size += 4 + extra;
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/* If the branch can't reach, use a plt_branch.
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The branch insn is at the end, or "extra" bytes along. So
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its offset will be "extra" bytes less that that already
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calculated. */
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if (off - extra + (1 << 25) >= (bfd_vma) (1 << 26))
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{
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stub_entry->type.main = ppc_stub_plt_branch;
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size += 4;
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pad = plt_stub_pad (htab->params->plt_stub_align, stub_offset, size);
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if (pad != 0)
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{
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stub_offset += pad;
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off -= pad;
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odd ^= pad & 4;
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size -= extra;
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if (stub_entry->type.sub == ppc_stub_notoc)
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extra = size_power10_offset (off, odd);
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else
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extra = size_offset (off - 8);
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size += extra;
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}
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}
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else if (info->emitrelocations)
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stub_entry->group->stub_sec->reloc_count +=1;
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if (info->emitrelocations)
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{
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unsigned int num_rel;
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@ -12426,17 +12460,6 @@ ppc_size_one_stub (struct bfd_hash_entry *gen_entry, void *in_arg)
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stub_entry->group->stub_sec->flags |= SEC_RELOC;
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}
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if (stub_entry->type.sub == ppc_stub_notoc)
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extra = size_power10_offset (off, odd);
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else
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extra = size_offset (off - 8);
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/* Include branch insn plus those in the offset sequence. */
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size += 4 + extra;
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/* The branch insn is at the end, or "extra" bytes along. So
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its offset will be "extra" bytes less that that already
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calculated. */
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off -= extra;
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if (stub_entry->type.sub != ppc_stub_notoc)
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{
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/* After the bcl, lr has been modified so we need to emit
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@ -12451,15 +12474,6 @@ ppc_size_one_stub (struct bfd_hash_entry *gen_entry, void *in_arg)
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stub_entry->group->eh_size += eh_advance_size (delta) + 6;
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stub_entry->group->lr_restore = lr_used + 8;
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}
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/* If the branch can't reach, use a plt_branch. */
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if (off + (1 << 25) >= (bfd_vma) (1 << 26))
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{
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stub_entry->type.main = ppc_stub_plt_branch;
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size += 4;
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}
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else if (info->emitrelocations)
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stub_entry->group->stub_sec->reloc_count +=1;
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}
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else if (stub_entry->type.sub >= ppc_stub_notoc)
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{
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@ -12,18 +12,17 @@ Disassembly of section \.text:
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.*: (e9 8c 7f f0|f0 7f 8c e9) ld r12,32752\(r12\)
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.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
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.*: (4e 80 04 20|20 04 80 4e) bctr
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0+100000d0 <.*\.plt_branch\.f2>:
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#...
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0+100000e0 <.*\.plt_branch\.f2>:
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.*: (3d 82 ff ff|ff ff 82 3d) addis r12,r2,-1
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.*: (e9 8c 7f f8|f8 7f 8c e9) ld r12,32760\(r12\)
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.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
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.*: (4e 80 04 20|20 04 80 4e) bctr
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0+100000e0 <.*\.long_branch\.f5>:
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0+100000f0 <.*\.long_branch\.f5>:
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.*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\)
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.*: (48 00 00 6c|6c 00 00 48) b .* <f5>
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\.\.\.
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.*: (48 00 00 5c|5c 00 00 48) b .* <f5>
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#...
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0+10000100 <(f1|_start)>:
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.*: (3c 40 10 02|02 10 40 3c) lis r2,4098
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.*: (38 42 82 00|00 82 42 38) addi r2,r2,-32256
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@ -15,7 +15,7 @@ Disassembly of section \.text:
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.* <.*\.long_branch\.g1>:
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.*: (18 00 41 f8|f8 41 00 18) std r2,24\(r1\)
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.*: (8c 00 00 48|48 00 00 8c) b .* <g1>
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#...
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.* <.*\.plt_branch\.ext>:
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.*: (a6 02 88 7d|7d 88 02 a6) mflr r12
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.*: (05 00 9f 42|42 9f 00 05) bcl .*
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@ -25,7 +25,7 @@ Disassembly of section \.text:
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.*: (ff ff 8c 61|61 8c ff ff) ori r12,r12,65535
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.*: (c6 07 9c 79|79 9c 07 c6) sldi r28,r12,32
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.*: (ff ef 8c 65|65 8c ef ff) oris r12,r12,61439
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.*: (28 ff 8c 61|61 8c ff 28) ori r12,r12,65320
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.*: (18 ff 8c 61|61 8c ff 18) ori r12,r12,65304
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.*: (14 62 8b 7d|7d 8b 62 14) add r12,r11,r12
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.*: (a6 03 89 7d|7d 89 03 a6) mtctr r12
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.*: (20 04 80 4e|4e 80 04 20) bctr
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@ -35,58 +35,57 @@ Disassembly of section \.text:
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.*: (05 00 9f 42|42 9f 00 05) bcl .*
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.*: (a6 02 68 7d|7d 68 02 a6) mflr r11
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.*: (a6 03 88 7d|7d 88 03 a6) mtlr r12
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.*: (64 00 8b 39|39 8b 00 64) addi r12,r11,100
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.*: (58 00 00 48|48 00 00 58) b .* <f2>
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.*: (54 00 8b 39|39 8b 00 54) addi r12,r11,84
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.*: (.. .. 00 48|48 00 .. ..) b .* <f2>
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.* <.*\.long_branch\.g2>:
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.*: (a6 02 88 7d|7d 88 02 a6) mflr r12
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.*: (05 00 9f 42|42 9f 00 05) bcl .*
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.*: (a6 02 68 7d|7d 68 02 a6) mflr r11
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.*: (a6 03 88 7d|7d 88 03 a6) mtlr r12
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.*: (80 00 8b 39|39 8b 00 80) addi r12,r11,128
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.*: (74 00 00 48|48 00 00 74) b .* <g2>
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\.\.\.
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.*: (70 00 8b 39|39 8b 00 70) addi r12,r11,112
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.*: (.. .. 00 48|48 00 .. ..) b .* <g2>
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#...
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.* <f1>:
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.*: (01 00 00 48|48 00 00 01) bl .* <f1>
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.*: (bd ff ff 4b|4b ff ff bd) bl .* <.*\.long_branch\.f2>
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.*: (11 00 00 48|48 00 00 11) bl .* <g1>
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.*: (cd ff ff 4b|4b ff ff cd) bl .* <.*\.long_branch\.g2>
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.*: (81 ff ff 4b|4b ff ff 81) bl .* <.*\.plt_branch\.ext>
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.*: (.. .. ff 4b|4b ff .. ..) bl .* <.*\.long_branch\.f2>
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.*: (.. .. 00 48|48 00 .. ..) bl .* <g1>
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.*: (.. .. ff 4b|4b ff .. ..) bl .* <.*\.long_branch\.g2>
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.*: (.. .. ff 4b|4b ff .. ..) bl .* <.*\.plt_branch\.ext>
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.*: (20 00 80 4e|4e 80 00 20) blr
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.* <g1>:
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.*: (a9 ff ff 4b|4b ff ff a9) bl .* <.*\.long_branch\.f2>
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.*: (e5 ff ff 4b|4b ff ff e5) bl .* <f1>
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.*: (b9 ff ff 4b|4b ff ff b9) bl .* <.*\.long_branch\.g2>
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.*: (f5 ff ff 4b|4b ff ff f5) bl .* <g1>
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.*: (.. .. ff 4b|4b ff .. ..) bl .* <.*\.long_branch\.f2>
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.*: (.. .. ff 4b|4b ff .. ..) bl .* <f1>
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.*: (.. .. ff 4b|4b ff .. ..) bl .* <.*\.long_branch\.g2>
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.*: (.. .. ff 4b|4b ff .. ..) bl .* <g1>
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.*: (20 00 80 4e|4e 80 00 20) blr
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.* <f2>:
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.*: (01 10 40 3c|3c 40 10 01) lis r2,4097
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.*: (00 80 42 38|38 42 80 00) addi r2,r2,-32768
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.*: (4d ff ff 4b|4b ff ff 4d) bl .* <.*\.long_branch\.f1>
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.*: (.. .. ff 4b|4b ff .. ..) bl .* <.*\.long_branch\.f1>
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.*: (18 00 41 e8|e8 41 00 18) ld r2,24\(r1\)
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.*: (f9 ff ff 4b|4b ff ff f9) bl .* <f2\+0x8>
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.*: (.. .. ff 4b|4b ff .. ..) bl .* <f2\+0x8>
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.*: (00 00 00 60|60 00 00 00) nop
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.*: (45 ff ff 4b|4b ff ff 45) bl .* <.*\.long_branch\.g1>
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.*: (.. .. ff 4b|4b ff .. ..) bl .* <.*\.long_branch\.g1>
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.*: (18 00 41 e8|e8 41 00 18) ld r2,24\(r1\)
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.*: (1d 00 00 48|48 00 00 1d) bl .* <g2\+0x8>
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.*: (.. .. 00 48|48 00 .. ..) bl .* <g2\+0x8>
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.*: (00 00 00 60|60 00 00 00) nop
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.*: (3d ff ff 4b|4b ff ff 3d) bl .* <.*\.plt_branch\.ext>
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.*: (.. .. ff 4b|4b ff .. ..) bl .* <.*\.plt_branch\.ext>
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.*: (00 00 00 60|60 00 00 00) nop
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.*: (20 00 80 4e|4e 80 00 20) blr
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.* <g2>:
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.*: (01 10 40 3c|3c 40 10 01) lis r2,4097
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.*: (00 80 42 38|38 42 80 00) addi r2,r2,-32768
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.*: (cd ff ff 4b|4b ff ff cd) bl .* <f2\+0x8>
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.*: (.. .. ff 4b|4b ff .. ..) bl .* <f2\+0x8>
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.*: (00 00 00 60|60 00 00 00) nop
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.*: (11 ff ff 4b|4b ff ff 11) bl .* <.*\.long_branch\.f1>
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.*: (.. .. ff 4b|4b ff .. ..) bl .* <.*\.long_branch\.f1>
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.*: (18 00 41 e8|e8 41 00 18) ld r2,24\(r1\)
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.*: (f1 ff ff 4b|4b ff ff f1) bl .* <g2\+0x8>
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.*: (.. .. ff 4b|4b ff .. ..) bl .* <g2\+0x8>
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.*: (00 00 00 60|60 00 00 00) nop
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.*: (09 ff ff 4b|4b ff ff 09) bl .* <.*\.long_branch\.g1>
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.*: (.. .. ff 4b|4b ff .. ..) bl .* <.*\.long_branch\.g1>
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.*: (18 00 41 e8|e8 41 00 18) ld r2,24\(r1\)
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.*: (20 00 80 4e|4e 80 00 20) blr
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@ -11,17 +11,17 @@ Contents of the \.eh_frame section:
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DW_CFA_def_cfa: r1 ofs 0
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00000014 0000000000000024 00000018 FDE cie=00000000 pc=00000000100000c0\.\.0000000010000140
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DW_CFA_advance_loc: 24 to 00000000100000d8
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DW_CFA_advance_loc: 40 to 00000000100000e8
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DW_CFA_register: r65 in r12
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DW_CFA_advance_loc: 8 to 00000000100000e0
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DW_CFA_advance_loc: 8 to 00000000100000f0
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DW_CFA_restore_extended: r65
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DW_CFA_advance_loc: 40 to 0000000010000108
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DW_CFA_advance_loc: 40 to 0000000010000118
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DW_CFA_register: r65 in r12
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DW_CFA_advance_loc: 8 to 0000000010000110
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DW_CFA_advance_loc: 8 to 0000000010000120
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DW_CFA_restore_extended: r65
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DW_CFA_advance_loc: 16 to 0000000010000120
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DW_CFA_advance_loc: 16 to 0000000010000130
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DW_CFA_register: r65 in r12
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DW_CFA_advance_loc: 8 to 0000000010000128
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DW_CFA_advance_loc: 8 to 0000000010000138
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DW_CFA_restore_extended: r65
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DW_CFA_nop
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DW_CFA_nop
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@ -14,12 +14,12 @@ Disassembly of section \.text:
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.* <.*\.long_branch\.g1>:
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.*: (18 00 41 f8|f8 41 00 18) std r2,24\(r1\)
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.*: (.. .. 00 48|48 00 .. ..) b .* <g1>
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#...
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.* <.*\.plt_branch\.ext>:
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.*: (00 20 60 3d|3d 60 20 00) lis r11,8192
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.*: (00 00 6b 61|61 6b 00 00) ori r11,r11,0
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.*: (ff ef 13 06|06 13 ef ff) pla r12,-268435736 # 0
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.*: (e8 fe 80 39|39 80 fe e8)
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.*: (ff ef 13 06|06 13 ef ff) pla r12,-268435752 # 0
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.*: (d8 fe 80 39|39 80 fe d8)
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.*: (46 17 6b 79|79 6b 17 46) sldi r11,r11,34
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.*: (14 62 8b 7d|7d 8b 62 14) add r12,r11,r12
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.*: (a6 03 89 7d|7d 89 03 a6) mtctr r12
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@ -30,17 +30,16 @@ Disassembly of section \.text:
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.* <.*\.long_branch\.f2>:
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.*: (00 00 00 60|60 00 00 00) nop
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.*: (00 00 10 06|06 10 00 00) pla r12,108 # .* <f2>
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.*: (6c 00 80 39|39 80 00 6c)
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.*: (00 00 10 06|06 10 00 00) pla r12,92 # .* <f2>
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.*: (5c 00 80 39|39 80 00 5c)
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.*: (.. .. 00 48|48 00 .. ..) b .* <f2>
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.* <.*\.long_branch\.g2>:
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.*: (00 00 00 60|60 00 00 00) nop
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.*: (00 00 10 06|06 10 00 00) pla r12,144 # .* <g2>
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.*: (90 00 80 39|39 80 00 90)
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.*: (00 00 10 06|06 10 00 00) pla r12,128 # .* <g2>
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.*: (80 00 80 39|39 80 00 80)
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.*: (.. .. 00 48|48 00 .. ..) b .* <g2>
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#...
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.* <f1>:
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.*: (01 00 00 48|48 00 00 01) bl .* <f1>
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.*: (.. .. ff 4b|4b ff .. ..) bl .* <.*\.long_branch\.f2>
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@ -4,7 +4,7 @@
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# Check that the IRELATIVE addend is magic+0, not magic+8
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#...
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.* R_PPC64_IRELATIVE +10000180
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.* R_PPC64_IRELATIVE +100001a0
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#...
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.*: 0+10000180 +20 IFUNC +LOCAL +DEFAULT .* magic
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.*: 0+100001a0 +20 IFUNC +LOCAL +DEFAULT .* magic
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#pass
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Reference in a new issue