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Add support for the AVR Tiny series of microcontrollers.

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* archures.c: add avrtiny architecture for avr target.
	* bfd-in2.h: Regenerate.
	* cpu-avr.c (arch_info_struct): add avrtiny arch info.
	* elf32-avr.c (elf_avr_howto_table): new relocation R_AVR_LDS_STS_16
	added for 16 bit LDS/STS instruction of avrtiny arch.
	(avr_reloc_map): reloc R_AVR_LDS_STS_16 is mapped to
	BFD_RELOC_AVR_LDS_STS_16.
	(bfd_elf_avr_final_write_processing): select machine number avrtiny arch.
	(elf32_avr_object_p): set machine number for avrtiny arch.
	* libbfd.h: Regenerate.
	* reloc.c: Add documentation for BFD_RELOC_AVR_LDS_STS_16 reloc.

         * config/tc-avr.c (mcu_types): Add avrtiny arch.
	Add avrtiny arch devices attiny4, attiny5, attiny9, attiny10, attiny20
	and attiny40.
	(md_show_usage): Add avrtiny arch in usage message.
	(avr_operand): validate and issue error for invalid register for avrtiny.
	add new reloc exp for 16 bit lds/sts instruction.
	(md_apply_fix): check 16 bit lds/sts operand for out of range and encode.
	(md_assemble): check ISA for arch and issue diagnostic.

	* include/elf/avr.h (E_AVR_MACH_AVRTINY): define avrtiny machine number.
	(R_AVR_LDS_STS_16): define 16 bit lds/sts reloc number.
	* include/opcode/avr.h (AVR_ISA_TINY): define avrtiny specific ISA.
	(AVR_ISA_2xxxa): define ISA without LPM.
	(AVR_ISA_AVRTINY): define avrtiny arch ISA.
	Add doc for contraint used in 16 bit lds/sts.
	Adjust ISA group for icall, ijmp, pop and push.
	Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
	* opcodes/avr-dis.c (avr_operand): Handle constraint j for 16 bit lds/sts.
	(print_insn_avr): do not select opcode if insn ISA is avrtiny and machine
	is not avrtiny.

	* Makefile.am (ALL_EMULATION_SOURCES): add avrtiny emulation source.
	(eavrtiny.c): add rules for avrtiny emulation source.
	* Makefile.in: Regenerate.
	* configure.tgt: Add avrtiny to avr target emulations.
	* scripttempl/avrtiny.sc: New file.
	linker script template for avrtiny arch.
	* emulparams/avrtiny.sh: New file.
	emulation parameters for avrtiny arch.
This commit is contained in:
Barney Stratford 2014-07-01 10:20:17 +01:00 • committed by Nick Clifton
parent ba8e7d1e24
commit f36e88862f
23 changed files with 649 additions and 165 deletions
Download patch file Download diff file Expand all files Collapse all files

18
bfd/ChangeLog
View file

@ -1,3 +1,21 @@
2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
Pitchumani Sivanupandi <pitchumani.s@atmel.com>
Soundararajan <Sounderarajan.D@atmel.com>
* archures.c: Add avrtiny architecture for avr target.
* cpu-avr.c (arch_info_struct): Add avrtiny arch info.
* elf32-avr.c (elf_avr_howto_table): New relocation R_AVR_LDS_STS_16
added for 16 bit LDS/STS instruction of avrtiny arch.
(avr_reloc_map): Reloc R_AVR_LDS_STS_16 is mapped to
BFD_RELOC_AVR_LDS_STS_16.
(bfd_elf_avr_final_write_processing): Select machine number
avrtiny arch.
(elf32_avr_object_p): Set machine number for avrtiny arch.
* reloc.c: Add documentation for BFD_RELOC_AVR_LDS_STS_16 reloc.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
2014-06-26 Nick Clifton <nickc@redhat.com>
PR binutils/16949

1
bfd/archures.c
View file

@ -410,6 +410,7 @@ DESCRIPTION
.#define bfd_mach_avr5 5
.#define bfd_mach_avr51 51
.#define bfd_mach_avr6 6
.#define bfd_mach_avrtiny 100
.#define bfd_mach_avrxmega1 101
.#define bfd_mach_avrxmega2 102
.#define bfd_mach_avrxmega3 103

5
bfd/bfd-in2.h
View file

@ -2195,6 +2195,7 @@ enum bfd_architecture
#define bfd_mach_avr5 5
#define bfd_mach_avr51 51
#define bfd_mach_avr6 6
#define bfd_mach_avrtiny 100
#define bfd_mach_avrxmega1 101
#define bfd_mach_avrxmega2 102
#define bfd_mach_avrxmega3 103
@ -4475,6 +4476,10 @@ value. */
BFD_RELOC_AVR_DIFF16,
BFD_RELOC_AVR_DIFF32,
/* This is a 7 bit reloc for the AVR that stores SRAM address for 16bit
lds and sts instructions supported only tiny core. */
BFD_RELOC_AVR_LDS_STS_16,
/* Renesas RL78 Relocations. */
BFD_RELOC_RL78_NEG8,
BFD_RELOC_RL78_NEG16,

31
bfd/cpu-avr.c
View file

@ -67,7 +67,6 @@ compatible (const bfd_arch_info_type * a,
return a;
if (a->mach == bfd_mach_avr31 && b->mach == bfd_mach_avr3)
return b;
if (a->mach == bfd_mach_avr3 && b->mach == bfd_mach_avr35)
return a;
if (a->mach == bfd_mach_avr35 && b->mach == bfd_mach_avr3)
@ -78,7 +77,6 @@ compatible (const bfd_arch_info_type * a,
if (a->mach == bfd_mach_avr51 && b->mach == bfd_mach_avr5)
return b;
return NULL;
}
@ -135,25 +133,28 @@ static const bfd_arch_info_type arch_info_struct[] =
/* 3-Byte PC. */
N (22, bfd_mach_avr6, "avr:6", FALSE, & arch_info_struct[10]),
/* Xmega 1 */
N (24, bfd_mach_avrxmega1, "avr:101", FALSE, & arch_info_struct[11]),
/* Tiny core (AVR Tiny). */
N (16, bfd_mach_avrtiny, "avr:100", FALSE, & arch_info_struct[11]),
/* Xmega 2 */
N (24, bfd_mach_avrxmega2, "avr:102", FALSE, & arch_info_struct[12]),
/* Xmega 1. */
N (24, bfd_mach_avrxmega1, "avr:101", FALSE, & arch_info_struct[12]),
/* Xmega 3 */
N (24, bfd_mach_avrxmega3, "avr:103", FALSE, & arch_info_struct[13]),
/* Xmega 2. */
N (24, bfd_mach_avrxmega2, "avr:102", FALSE, & arch_info_struct[13]),
/* Xmega 4 */
N (24, bfd_mach_avrxmega4, "avr:104", FALSE, & arch_info_struct[14]),
/* Xmega 3. */
N (24, bfd_mach_avrxmega3, "avr:103", FALSE, & arch_info_struct[14]),
/* Xmega 5 */
N (24, bfd_mach_avrxmega5, "avr:105", FALSE, & arch_info_struct[15]),
/* Xmega 4. */
N (24, bfd_mach_avrxmega4, "avr:104", FALSE, & arch_info_struct[15]),
/* Xmega 6 */
N (24, bfd_mach_avrxmega6, "avr:106", FALSE, & arch_info_struct[16]),
/* Xmega 5. */
N (24, bfd_mach_avrxmega5, "avr:105", FALSE, & arch_info_struct[16]),
/* Xmega 7 */
/* Xmega 6. */
N (24, bfd_mach_avrxmega6, "avr:106", FALSE, & arch_info_struct[17]),
/* Xmega 7. */
N (24, bfd_mach_avrxmega7, "avr:107", FALSE, NULL)
};

49
bfd/elf32-avr.c
View file

@ -33,13 +33,8 @@ static bfd_boolean debug_relax = FALSE;
static bfd_boolean debug_stubs = FALSE;
static bfd_reloc_status_type
bfd_elf_avr_diff_reloc (bfd *abfd,
arelent *reloc_entry,
asymbol *symbol,
void *data,
asection *input_section,
bfd *output_bfd,
char **error_message);
bfd_elf_avr_diff_reloc (bfd *, arelent *, asymbol *, void *,
asection *, bfd *, char **);
/* Hash table initialization and handling. Code is taken from the hppa port
and adapted to the needs of AVR. */
@ -604,6 +599,20 @@ static reloc_howto_type elf_avr_howto_table[] =
FALSE, /* partial_inplace */
0, /* src_mask */
0xffffffff, /* dst_mask */
FALSE), /* pcrel_offset */
/* 7 bit immediate for LDS/STS in Tiny core. */
HOWTO (R_AVR_LDS_STS_16, /* type */
0, /* rightshift */
1, /* size (0 = byte, 1 = short, 2 = long) */
7, /* bitsize */
FALSE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont,/* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_AVR_LDS_STS_16", /* name */
FALSE, /* partial_inplace */
0xffff, /* src_mask */
0xffff, /* dst_mask */
FALSE) /* pcrel_offset */
};
@ -649,7 +658,8 @@ static const struct avr_reloc_map avr_reloc_map[] =
{ BFD_RELOC_AVR_8_HLO, R_AVR_8_HLO8 },
{ BFD_RELOC_AVR_DIFF8, R_AVR_DIFF8 },
{ BFD_RELOC_AVR_DIFF16, R_AVR_DIFF16 },
{ BFD_RELOC_AVR_DIFF32, R_AVR_DIFF32 }
{ BFD_RELOC_AVR_DIFF32, R_AVR_DIFF32 },
{ BFD_RELOC_AVR_LDS_STS_16, R_AVR_LDS_STS_16}
};
/* Meant to be filled one day with the wrap around address for the
@ -1227,6 +1237,17 @@ avr_final_link_relocate (reloc_howto_type * howto,
r = bfd_reloc_ok;
break;
case R_AVR_LDS_STS_16:
contents += rel->r_offset;
srel = (bfd_signed_vma) relocation + rel->r_addend;
if ((srel & 0xFFFF) < 0x40 || (srel & 0xFFFF) > 0xbf)
return bfd_reloc_outofrange;
srel = srel & 0x7f;
x = bfd_get_16 (input_bfd, contents);
x |= (srel & 0x0f) | ((srel & 0x30) << 5) | ((srel & 0x40) << 2);
bfd_put_16 (input_bfd, x, contents);
break;
default:
r = _bfd_final_link_relocate (howto, input_bfd, input_section,
contents, rel->r_offset,
@ -1439,6 +1460,10 @@ bfd_elf_avr_final_write_processing (bfd *abfd,
case bfd_mach_avrxmega7:
val = E_AVR_MACH_XMEGA7;
break;
case bfd_mach_avrtiny:
val = E_AVR_MACH_AVRTINY;
break;
}
elf_elfheader (abfd)->e_machine = EM_AVR;
@ -1529,6 +1554,10 @@ elf32_avr_object_p (bfd *abfd)
case E_AVR_MACH_XMEGA7:
e_set = bfd_mach_avrxmega7;
break;
case E_AVR_MACH_AVRTINY:
e_set = bfd_mach_avrtiny;
break;
}
}
return bfd_default_set_arch_mach (abfd, bfd_arch_avr,
@ -1605,8 +1634,8 @@ elf32_avr_adjust_diff_reloc_value (bfd *abfd,
/* Reduce the diff value by count bytes and write it back into section
contents. */
if (shrinked_insn_address >= start_address &&
shrinked_insn_address <= end_address)
if (shrinked_insn_address >= start_address
&& shrinked_insn_address <= end_address)
{
switch (ELF32_R_TYPE (irel->r_info))
{

1
bfd/libbfd.h
View file

@ -2041,6 +2041,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
"BFD_RELOC_AVR_DIFF8",
"BFD_RELOC_AVR_DIFF16",
"BFD_RELOC_AVR_DIFF32",
"BFD_RELOC_AVR_LDS_STS_16",
"BFD_RELOC_RL78_NEG8",
"BFD_RELOC_RL78_NEG16",
"BFD_RELOC_RL78_NEG24",

5
bfd/reloc.c
View file

@ -4789,6 +4789,11 @@ ENUMDOC
assuming no relaxation. The relocation encodes the position of the
second symbol so the linker can determine whether to adjust the field
value.
ENUM
BFD_RELOC_AVR_LDS_STS_16
ENUMDOC
This is a 7 bit reloc for the AVR that stores SRAM address for 16bit
lds and sts instructions supported only tiny core.
ENUM
BFD_RELOC_RL78_NEG8
ENUMX

16
gas/ChangeLog
View file

@ -1,3 +1,19 @@
2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
Pitchumani Sivanupandi <pitchumani.s@atmel.com>
Soundararajan <Sounderarajan.D@atmel.com>
* config/tc-avr.c (mcu_types): Add avrtiny arch.
Add avrtiny arch devices attiny4, attiny5, attiny9, attiny10, attiny20
and attiny40.
(md_show_usage): Add avrtiny arch in usage message.
(avr_operand): validate and issue error for invalid register for avrtiny.
add new reloc exp for 16 bit lds/sts instruction.
(md_apply_fix): check 16 bit lds/sts operand for out of range and encode.
(md_assemble): check ISA for arch and issue diagnostic.
* NEWS: Mention new support.
* doc/c-avr.texi: Document support for avrtiny architecture.
2014-06-27 Alan Modra <amodra@gmail.com>
* config/obj-macho.c (obj_mach_o_set_symbol_qualifier): Don't set

2
gas/NEWS
View file

@ -1,5 +1,7 @@
-*- text -*-
* Add support for the AVR Tiny microcontrollers.
* Replace support for openrisc and or32 with support for or1k.
* Enhanced the ARM port to accept the assembler output from the CodeComposer

69
gas/config/tc-avr.c
View file

@ -89,6 +89,7 @@ static struct mcu_type_s mcu_types[] =
{"avrxmega5", AVR_ISA_XMEGA, bfd_mach_avrxmega5},
{"avrxmega6", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
{"avrxmega7", AVR_ISA_XMEGA, bfd_mach_avrxmega7},
{"avrtiny", AVR_ISA_AVRTINY, bfd_mach_avrtiny},
{"at90s1200", AVR_ISA_1200, bfd_mach_avr1},
{"attiny11", AVR_ISA_AVR1, bfd_mach_avr1},
{"attiny12", AVR_ISA_AVR1, bfd_mach_avr1},
@ -323,6 +324,12 @@ static struct mcu_type_s mcu_types[] =
{"atxmega128a1", AVR_ISA_XMEGA, bfd_mach_avrxmega7},
{"atxmega128a1u", AVR_ISA_XMEGAU, bfd_mach_avrxmega7},
{"atxmega128a4u", AVR_ISA_XMEGAU, bfd_mach_avrxmega7},
{"attiny4", AVR_ISA_AVRTINY, bfd_mach_avrtiny},
{"attiny5", AVR_ISA_AVRTINY, bfd_mach_avrtiny},
{"attiny9", AVR_ISA_AVRTINY, bfd_mach_avrtiny},
{"attiny10", AVR_ISA_AVRTINY, bfd_mach_avrtiny},
{"attiny20", AVR_ISA_AVRTINY, bfd_mach_avrtiny},
{"attiny40", AVR_ISA_AVRTINY, bfd_mach_avrtiny},
{NULL, 0, 0}
};
@ -513,7 +520,7 @@ md_show_usage (FILE *stream)
" avrxmega5 - XMEGA, > 64K, <= 128K FLASH, > 64K RAM\n"
" avrxmega6 - XMEGA, > 128K, <= 256K FLASH, <= 64K RAM\n"
" avrxmega7 - XMEGA, > 128K, <= 256K FLASH, > 64K RAM\n"
" or immediate microcontroller name.\n"));
" avrtiny - AVR Tiny core with 16 gp registers\n"));
fprintf (stream,
_(" -mall-opcodes accept all AVR opcodes, even if not supported by MCU\n"
" -mno-skip-bug disable warnings for skipping two-word instructions\n"
@ -876,8 +883,20 @@ avr_operand (struct avr_opcodes_s *opcode,
str = input_line_pointer;
}
if (op_mask <= 31)
if (avr_mcu->mach == bfd_mach_avrtiny)
{
if (op_mask < 16 || op_mask > 31)
{
as_bad (_("register name or number from 16 to 31 required"));
break;
}
}
else if (op_mask > 31)
{
as_bad (_("register name or number from 0 to 31 required"));
break;
}
switch (*op)
{
case 'a':
@ -905,9 +924,6 @@ avr_operand (struct avr_opcodes_s *opcode,
break;
}
break;
}
as_bad (_("register name or number from 0 to 31 required"));
break;
case 'e':
{
@ -1014,6 +1030,12 @@ avr_operand (struct avr_opcodes_s *opcode,
&op_expr, FALSE, BFD_RELOC_16);
break;
case 'j':
str = parse_exp (str, &op_expr);
fix_new_exp (frag_now, where, opcode->insn_size * 2,
&op_expr, FALSE, BFD_RELOC_AVR_LDS_STS_16);
break;
case 'M':
{
bfd_reloc_code_real_type r_type;
@ -1415,11 +1437,21 @@ md_apply_fix (fixS *fixP, valueT * valP, segT seg)
bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value), where);
break;
case BFD_RELOC_AVR_LDS_STS_16:
if ((value < 0x40) || (value > 0xBF))
as_warn_where (fixP->fx_file, fixP->fx_line,
_("operand out of range: 0x%lx"),
(unsigned long)value);
insn |= ((value & 0xF) | ((value & 0x30) << 5) | ((value & 0x40) << 2));
bfd_putl16 ((bfd_vma) insn, where);
break;
case BFD_RELOC_AVR_6:
if ((value > 63) || (value < 0))
as_bad_where (fixP->fx_file, fixP->fx_line,
_("operand out of range: %ld"), value);
bfd_putl16 ((bfd_vma) insn | ((value & 7) | ((value & (3 << 3)) << 7) | ((value & (1 << 5)) << 8)), where);
bfd_putl16 ((bfd_vma) insn | ((value & 7) | ((value & (3 << 3)) << 7)
| ((value & (1 << 5)) << 8)), where);
break;
case BFD_RELOC_AVR_6_ADIW:
@ -1594,6 +1626,28 @@ md_assemble (char *str)
opcode = (struct avr_opcodes_s *) hash_find (avr_hash, op);
if (opcode && !avr_opt.all_opcodes)
{
/* Check if the instruction's ISA bit is ON in the ISA bits of the part
specified by the user. If not look for other instructions
specifications with same mnemonic who's ISA bits matches.
This requires include/opcode/avr.h to have the instructions with
same mnenomic to be specified in sequence. */
while ((opcode->isa & avr_mcu->isa) != opcode->isa)
{
opcode++;
if (opcode->name && strcmp(op, opcode->name))
{
as_bad (_("illegal opcode %s for mcu %s"),
opcode->name, avr_mcu->name);
return;
}
}
}
if (opcode == NULL)
{
as_bad (_("unknown opcode `%s'"), op);
@ -1606,9 +1660,6 @@ md_assemble (char *str)
if (*str && *opcode->constraints == '?')
++opcode;
if (!avr_opt.all_opcodes && (opcode->isa & avr_mcu->isa) != opcode->isa)
as_bad (_("illegal opcode %s for mcu %s"), opcode->name, avr_mcu->name);
dwarf2_emit_insn (0);
/* We used to set input_line_pointer to the result of get_operands,

61
gas/doc/c-avr.texi
View file

@ -82,40 +82,47 @@ at90pwm216, at90pwm316, atmega32c1, atmega64c1, atmega16m1, atmega32m1,
atmega64m1, atmega16u4, atmega32u4, atmega32u6, at90usb646, at90usb647, at94k,
at90scr100, ata5790, ata5795).
Instruction set avr51 is for the enhanced AVR core with exactly 128K program
memory space (MCU types: atmega128, atmega128a, atmega1280, atmega1281,
atmega1284, atmega1284p, atmega128rfa1, atmega128rfr2, atmega1284rfr2,
at90can128, at90usb1286, at90usb1287, m3000).
Instruction set avr51 is for the enhanced AVR core with exactly 128K
program memory space (MCU types: atmega128, atmega128a, atmega1280,
atmega1281, atmega1284, atmega1284p, atmega128rfa1, atmega128rfr2,
atmega1284rfr2, at90can128, at90usb1286, at90usb1287, m3000).
Instruction set avr6 is for the enhanced AVR core with a 3-byte PC (MCU types:
atmega2560, atmega2561, atmega256rfr2, atmega2564rfr2).
Instruction set avr6 is for the enhanced AVR core with a 3-byte PC
(MCU types: atmega2560, atmega2561, atmega256rfr2, atmega2564rfr2).
Instruction set avrxmega2 is for the XMEGA AVR core with 8K to 64K program
memory space and less than 64K data space (MCU types: atxmega16a4, atxmega16a4u,
atxmega16c4, atxmega16d4, atxmega16x1, atxmega32a4, atxmega32a4u, atxmega32c4,
atxmega32d4, atxmega16e5, atxmega8e5, atxmega32e5, atxmega32x1).
Instruction set avrxmega2 is for the XMEGA AVR core with 8K to 64K
program memory space and less than 64K data space (MCU types:
atxmega16a4, atxmega16a4u, atxmega16c4, atxmega16d4, atxmega16x1,
atxmega32a4, atxmega32a4u, atxmega32c4, atxmega32d4, atxmega16e5,
atxmega8e5, atxmega32e5, atxmega32x1).
Instruction set avrxmega3 is for the XMEGA AVR core with 8K to 64K program
memory space and greater than 64K data space (MCU types: none).
Instruction set avrxmega3 is for the XMEGA AVR core with 8K to 64K
program memory space and greater than 64K data space (MCU types:
none).
Instruction set avrxmega4 is for the XMEGA AVR core with up to 64K program
memory space and less than 64K data space (MCU types: atxmega64a3, atxmega64a3u,
atxmega64a4u, atxmega64b1, atxmega64b3, atxmega64c3, atxmega64d3, atxmega64d4).
Instruction set avrxmega4 is for the XMEGA AVR core with up to 64K
program memory space and less than 64K data space (MCU types:
atxmega64a3, atxmega64a3u, atxmega64a4u, atxmega64b1, atxmega64b3,
atxmega64c3, atxmega64d3, atxmega64d4).
Instruction set avrxmega5 is for the XMEGA AVR core with up to 64K program
memory space and greater than 64K data space (MCU types: atxmega64a1,
atxmega64a1u).
Instruction set avrxmega5 is for the XMEGA AVR core with up to 64K
program memory space and greater than 64K data space (MCU types:
atxmega64a1, atxmega64a1u).
Instruction set avrxmega6 is for the XMEGA AVR core with larger than 64K program
memory space and less than 64K data space (MCU types: atxmega128a3,
atxmega128a3u, atxmega128c3, atxmega128d3, atxmega128d4, atxmega192a3,
atxmega192a3u, atxmega128b1, atxmega128b3, atxmega192c3, atxmega192d3,
atxmega256a3, atxmega256a3u, atxmega256a3b, atxmega256a3bu, atxmega256c3,
atxmega256d3, atxmega384c3, atxmega256d3).
Instruction set avrxmega6 is for the XMEGA AVR core with larger than
64K program memory space and less than 64K data space (MCU types:
atxmega128a3, atxmega128a3u, atxmega128c3, atxmega128d3, atxmega128d4,
atxmega192a3, atxmega192a3u, atxmega128b1, atxmega128b3, atxmega192c3,
atxmega192d3, atxmega256a3, atxmega256a3u, atxmega256a3b,
atxmega256a3bu, atxmega256c3, atxmega256d3, atxmega384c3,
atxmega256d3).
Instruction set avrxmega7 is for the XMEGA AVR core with larger than 64K program
memory space and greater than 64K data space (MCU types: atxmega128a1,
atxmega128a1u, atxmega128a4u).
Instruction set avrxmega7 is for the XMEGA AVR core with larger than
64K program memory space and greater than 64K data space (MCU types:
atxmega128a1, atxmega128a1u, atxmega128a4u).
Instruction set avrtiny is for the ATtiny4/5/9/10/20/40
microcontrollers.
@cindex @code{-mall-opcodes} command line option, AVR
@item -mall-opcodes

14
include/elf/ChangeLog
View file

@ -1,3 +1,17 @@
2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
Pitchumani Sivanupandi <pitchumani.s@atmel.com>
Soundararajan <Sounderarajan.D@atmel.com>
* avr.h (E_AVR_MACH_AVRTINY): Define avrtiny machine number.
(R_AVR_LDS_STS_16): Define 16 bit lds/sts reloc number.
* include/opcode/avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
(AVR_ISA_2xxxa): Define ISA without LPM.
(AVR_ISA_AVRTINY): Define avrtiny arch ISA.
Add doc for contraint used in 16 bit lds/sts.
Adjust ISA group for icall, ijmp, pop and push.
Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
2014-04-22 Christian Svensson <blue@cmd.nu>
* common.h: Remove openrisc and or32 support. Add support for or1k.

2
include/elf/avr.h
View file

@ -40,6 +40,7 @@
#define E_AVR_MACH_AVR5 5
#define E_AVR_MACH_AVR51 51
#define E_AVR_MACH_AVR6 6
#define E_AVR_MACH_AVRTINY 100
#define E_AVR_MACH_XMEGA1 101
#define E_AVR_MACH_XMEGA2 102
#define E_AVR_MACH_XMEGA3 103
@ -83,6 +84,7 @@ START_RELOC_NUMBERS (elf_avr_reloc_type)
RELOC_NUMBER (R_AVR_DIFF8, 30)
RELOC_NUMBER (R_AVR_DIFF16, 31)
RELOC_NUMBER (R_AVR_DIFF32, 32)
RELOC_NUMBER (R_AVR_LDS_STS_16, 33)
END_RELOC_NUMBERS (R_AVR_max)
#endif /* _ELF_AVR_H */

12
include/opcode/ChangeLog
View file

@ -1,3 +1,15 @@
2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
Pitchumani Sivanupandi <pitchumani.s@atmel.com>
Soundararajan <Sounderarajan.D@atmel.com>
* avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
(AVR_ISA_2xxxa): Define ISA without LPM.
(AVR_ISA_AVRTINY): Define avrtiny arch ISA.
Add doc for contraint used in 16 bit lds/sts.
Adjust ISA group for icall, ijmp, pop and push.
Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
2014-05-19 Nick Clifton <nickc@redhat.com>
* msp430.h (struct msp430_operand_s): Add vshift field.

20
include/opcode/avr.h
View file

@ -22,6 +22,7 @@
#define AVR_ISA_LPM 0x0002 /* device has LPM */
#define AVR_ISA_LPMX 0x0004 /* device has LPM Rd,Z[+] */
#define AVR_ISA_SRAM 0x0008 /* device has SRAM (LD, ST, PUSH, POP, ...) */
#define AVR_ISA_TINY 0x0010 /* device has Tiny core specific encodings */
#define AVR_ISA_MEGA 0x0020 /* device has >8K program memory (JMP and CALL
supported, no 8K wrap on RJMP and RCALL) */
#define AVR_ISA_MUL 0x0040 /* device has new core (MUL, FMUL, ...) */
@ -37,6 +38,7 @@
#define AVR_ISA_TINY1 (AVR_ISA_1200 | AVR_ISA_LPM)
#define AVR_ISA_2xxx (AVR_ISA_TINY1 | AVR_ISA_SRAM)
#define AVR_ISA_2xxxa (AVR_ISA_1200 | AVR_ISA_SRAM)
/* For the attiny26 which is missing LPM Rd,Z+. */
#define AVR_ISA_2xxe (AVR_ISA_2xxx | AVR_ISA_LPMX)
#define AVR_ISA_RF401 (AVR_ISA_2xxx | AVR_ISA_MOVW | AVR_ISA_LPMX)
@ -72,6 +74,9 @@
AVR_ISA_ELPM | AVR_ISA_ELPMX | AVR_ISA_SPM | \
AVR_ISA_BRK | AVR_ISA_EIND | AVR_ISA_MOVW)
#define AVR_ISA_AVRTINY (AVR_ISA_1200 | AVR_ISA_BRK | AVR_ISA_SRAM | \
AVR_ISA_TINY)
#define REGISTER_P(x) ((x) == 'r' \
|| (x) == 'd' \
|| (x) == 'w' \
@ -94,7 +99,7 @@
`ld r,b' or `st b,r' respectively - next opcode entry)? */
#define AVR_DISP0_P(x) (((x) & 0xFC07) == 0x8000)
/* constraint letters
/* Constraint letters:
r - any register
d - `ldi' register (r16-r31)
v - `movw' even register (r0, r2, ..., r28, r30)
@ -110,6 +115,7 @@
p - Port address value from 0 to 31. (cbi, sbi, sbic, sbis)
K - immediate value from 0 to 63 (used in `adiw', `sbiw')
i - immediate value
j - 7 bit immediate value from 0x40 to 0xBF (for 16-bit 'lds'/'sts')
l - signed pc relative offset from -64 to 63
L - signed pc relative offset from -2048 to 2047
h - absolute code address (call, jmp)
@ -160,8 +166,8 @@ AVR_INSN (sez, "", "1001010000011000", 1, AVR_ISA_1200, 0x9418)
AVR_INSN (bclr, "S", "100101001SSS1000", 1, AVR_ISA_1200, 0x9488)
AVR_INSN (bset, "S", "100101000SSS1000", 1, AVR_ISA_1200, 0x9408)
AVR_INSN (icall,"", "1001010100001001", 1, AVR_ISA_2xxx, 0x9509)
AVR_INSN (ijmp, "", "1001010000001001", 1, AVR_ISA_2xxx, 0x9409)
AVR_INSN (icall,"", "1001010100001001", 1, AVR_ISA_2xxxa,0x9509)
AVR_INSN (ijmp, "", "1001010000001001", 1, AVR_ISA_2xxxa,0x9409)
AVR_INSN (lpm, "?", "1001010111001000", 1, AVR_ISA_TINY1,0x95c8)
AVR_INSN (lpm, "r,z", "1001000ddddd010+", 1, AVR_ISA_LPMX, 0x9004)
@ -261,8 +267,8 @@ AVR_INSN (dec, "r", "1001010rrrrr1010", 1, AVR_ISA_1200, 0x940a)
AVR_INSN (inc, "r", "1001010rrrrr0011", 1, AVR_ISA_1200, 0x9403)
AVR_INSN (lsr, "r", "1001010rrrrr0110", 1, AVR_ISA_1200, 0x9406)
AVR_INSN (neg, "r", "1001010rrrrr0001", 1, AVR_ISA_1200, 0x9401)
AVR_INSN (pop, "r", "1001000rrrrr1111", 1, AVR_ISA_2xxx, 0x900f)
AVR_INSN (push, "r", "1001001rrrrr1111", 1, AVR_ISA_2xxx, 0x920f)
AVR_INSN (pop, "r", "1001000rrrrr1111", 1, AVR_ISA_2xxxa,0x900f)
AVR_INSN (push, "r", "1001001rrrrr1111", 1, AVR_ISA_2xxxa,0x920f)
AVR_INSN (ror, "r", "1001010rrrrr0111", 1, AVR_ISA_1200, 0x9407)
AVR_INSN (swap, "r", "1001010rrrrr0010", 1, AVR_ISA_1200, 0x9402)
@ -280,7 +286,9 @@ AVR_INSN (fmul, "a,a", "000000110ddd1rrr", 1, AVR_ISA_MUL, 0x0308)
AVR_INSN (fmuls,"a,a", "000000111ddd0rrr", 1, AVR_ISA_MUL, 0x0380)
AVR_INSN (fmulsu,"a,a","000000111ddd1rrr", 1, AVR_ISA_MUL, 0x0388)
AVR_INSN (sts, "j,d", "10101kkkddddkkkk", 1, AVR_ISA_TINY, 0xA800)
AVR_INSN (sts, "i,r", "1001001ddddd0000", 2, AVR_ISA_2xxx, 0x9200)
AVR_INSN (lds, "d,j", "10100kkkddddkkkk", 1, AVR_ISA_TINY, 0xA000)
AVR_INSN (lds, "r,i", "1001000ddddd0000", 2, AVR_ISA_2xxx, 0x9000)
/* Special case for b+0, `e' must be next entry after `b',
@ -295,6 +303,6 @@ AVR_INSN (st, "e,r", "100!001rrrrree-+", 1, AVR_ISA_1200, 0x8200)
AVR_INSN (eicall, "", "1001010100011001", 1, AVR_ISA_EIND, 0x9519)
AVR_INSN (eijmp, "", "1001010000011001", 1, AVR_ISA_EIND, 0x9419)
/* DES instruction for encryption and decryption */
/* DES instruction for encryption and decryption. */
AVR_INSN (des, "E", "10010100EEEE1011", 1, AVR_ISA_DES, 0x940B)

14
ld/ChangeLog
View file

@ -1,3 +1,17 @@
2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
Pitchumani Sivanupandi <pitchumani.s@atmel.com>
Soundararajan <Sounderarajan.D@atmel.com>
* Makefile.am (ALL_EMULATION_SOURCES): Add avrtiny emulation source.
(eavrtiny.c): Add rules for avrtiny emulation source.
* Makefile.in: Regenerate.
* configure.tgt: Add avrtiny to avr target emulations.
* scripttempl/avrtiny.sc: New file. Linker script template for
avrtiny arch.
* emulparams/avrtiny.sh: New file. Emulation parameters for
avrtiny arch.
2014-06-30 Ulrich Drepper <drepper@gmail.com>
* lexsup.c (parse_args): Check whether provided SONAME is empty

5
ld/Makefile.am
View file

@ -193,6 +193,7 @@ ALL_EMULATION_SOURCES = \
eavrxmega5.c \
eavrxmega6.c \
eavrxmega7.c \
eavrtiny.c \
ecoff_i860.c \
ecoff_sparc.c \
ecrisaout.c \
@ -848,6 +849,10 @@ eavrxmega7.c: $(srcdir)/emulparams/avrxmega7.sh \
$(srcdir)/emultempl/avrelf.em $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \
${GEN_DEPENDS}
eavrtiny.c: $(srcdir)/emulparams/avrtiny.sh \
$(srcdir)/emultempl/avrelf.em $(ELF_DEPS) $(srcdir)/scripttempl/avrtiny.sc \
${GEN_DEPENDS}
ecoff_i860.c: $(srcdir)/emulparams/coff_i860.sh \
$(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/i860coff.sc ${GEN_DEPENDS}

6
ld/Makefile.in
View file

@ -500,6 +500,7 @@ ALL_EMULATION_SOURCES = \
eavrxmega5.c \
eavrxmega6.c \
eavrxmega7.c \
eavrtiny.c \
ecoff_i860.c \
ecoff_sparc.c \
ecrisaout.c \
@ -1087,6 +1088,7 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eavr5.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eavr51.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eavr6.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eavrtiny.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eavrxmega1.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eavrxmega2.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eavrxmega3.Po@am__quote@
@ -2287,6 +2289,10 @@ eavrxmega7.c: $(srcdir)/emulparams/avrxmega7.sh \
$(srcdir)/emultempl/avrelf.em $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \
${GEN_DEPENDS}
eavrtiny.c: $(srcdir)/emulparams/avrtiny.sh \
$(srcdir)/emultempl/avrelf.em $(ELF_DEPS) $(srcdir)/scripttempl/avrtiny.sc \
${GEN_DEPENDS}
ecoff_i860.c: $(srcdir)/emulparams/coff_i860.sh \
$(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/i860coff.sc ${GEN_DEPENDS}

2
ld/configure.tgt
View file

@ -140,7 +140,7 @@ arm*-*-uclinux*) targ_emul=armelf_linux
arm-*-vxworks) targ_emul=armelf_vxworks ;;
arm*-*-conix*) targ_emul=armelf ;;
avr-*-*) targ_emul=avr2
targ_extra_emuls="avr1 avr25 avr3 avr31 avr35 avr4 avr5 avr51 avr6 avrxmega1 avrxmega2 avrxmega3 avrxmega4 avrxmega5 avrxmega6 avrxmega7"
targ_extra_emuls="avr1 avr25 avr3 avr31 avr35 avr4 avr5 avr51 avr6 avrxmega1 avrxmega2 avrxmega3 avrxmega4 avrxmega5 avrxmega6 avrxmega7 avrtiny"
;;
bfin-*-elf) targ_emul=elf32bfin;
targ_extra_emuls="elf32bfinfd"

13
ld/emulparams/avrtiny.sh Normal file
View file

@ -0,0 +1,13 @@
ARCH=avr:100
MACHINE=
SCRIPT_NAME=avrtiny
OUTPUT_FORMAT="elf32-avr"
MAXPAGESIZE=1
EMBEDDED=yes
TEMPLATE_NAME=elf32
TEXT_ORIGIN=0x0
TEXT_LENGTH=4K
DATA_ORIGIN=0x0800040
DATA_LENGTH=0x100
EXTRA_EM_FILE=avrelf

250
ld/scripttempl/avrtiny.sc Normal file
View file

@ -0,0 +1,250 @@
cat <<EOF
OUTPUT_FORMAT("${OUTPUT_FORMAT}","${OUTPUT_FORMAT}","${OUTPUT_FORMAT}")
OUTPUT_ARCH(${ARCH})
MEMORY
{
text (rx) : ORIGIN = $TEXT_ORIGIN, LENGTH = $TEXT_LENGTH
data (rw!x) : ORIGIN = $DATA_ORIGIN, LENGTH = $DATA_LENGTH
/* Provide offsets for config, lock and signature to match
production file format. Ignore offsets in datasheet. */
config (rw!x) : ORIGIN = 0x820000, LENGTH = 2
lock (rw!x) : ORIGIN = 0x830000, LENGTH = 2
signature (rw!x) : ORIGIN = 0x840000, LENGTH = 4
}
SECTIONS
{
/* Read-only sections, merged into text segment: */
${TEXT_DYNAMIC+${DYNAMIC}}
.hash ${RELOCATING-0} : { *(.hash) }
.dynsym ${RELOCATING-0} : { *(.dynsym) }
.dynstr ${RELOCATING-0} : { *(.dynstr) }
.gnu.version ${RELOCATING-0} : { *(.gnu.version) }
.gnu.version_d ${RELOCATING-0} : { *(.gnu.version_d) }
.gnu.version_r ${RELOCATING-0} : { *(.gnu.version_r) }
.rel.init ${RELOCATING-0} : { *(.rel.init) }
.rela.init ${RELOCATING-0} : { *(.rela.init) }
.rel.text ${RELOCATING-0} :
{
*(.rel.text)
${RELOCATING+*(.rel.text.*)}
${RELOCATING+*(.rel.gnu.linkonce.t*)}
}
.rela.text ${RELOCATING-0} :
{
*(.rela.text)
${RELOCATING+*(.rela.text.*)}
${RELOCATING+*(.rela.gnu.linkonce.t*)}
}
.rel.fini ${RELOCATING-0} : { *(.rel.fini) }
.rela.fini ${RELOCATING-0} : { *(.rela.fini) }
.rel.rodata ${RELOCATING-0} :
{
*(.rel.rodata)
${RELOCATING+*(.rel.rodata.*)}
${RELOCATING+*(.rel.gnu.linkonce.r*)}
}
.rela.rodata ${RELOCATING-0} :
{
*(.rela.rodata)
${RELOCATING+*(.rela.rodata.*)}
${RELOCATING+*(.rela.gnu.linkonce.r*)}
}
.rel.data ${RELOCATING-0} :
{
*(.rel.data)
${RELOCATING+*(.rel.data.*)}
${RELOCATING+*(.rel.gnu.linkonce.d*)}
}
.rela.data ${RELOCATING-0} :
{
*(.rela.data)
${RELOCATING+*(.rela.data.*)}
${RELOCATING+*(.rela.gnu.linkonce.d*)}
}
.rel.ctors ${RELOCATING-0} : { *(.rel.ctors) }
.rela.ctors ${RELOCATING-0} : { *(.rela.ctors) }
.rel.dtors ${RELOCATING-0} : { *(.rel.dtors) }
.rela.dtors ${RELOCATING-0} : { *(.rela.dtors) }
.rel.got ${RELOCATING-0} : { *(.rel.got) }
.rela.got ${RELOCATING-0} : { *(.rela.got) }
.rel.bss ${RELOCATING-0} : { *(.rel.bss) }
.rela.bss ${RELOCATING-0} : { *(.rela.bss) }
.rel.plt ${RELOCATING-0} : { *(.rel.plt) }
.rela.plt ${RELOCATING-0} : { *(.rela.plt) }
/* Internal text space or external memory. */
.text ${RELOCATING-0} : ${RELOCATING+ AT (0x0)}
{
*(.vectors)
KEEP(*(.vectors))
/* For data that needs to reside in the lower 64k of progmem. */
*(.progmem.gcc*)
*(.progmem*)
${RELOCATING+. = ALIGN(2);}
${CONSTRUCTING+ __trampolines_start = . ; }
/* The jump trampolines for the 16-bit limited relocs will reside here. */
*(.trampolines)
*(.trampolines*)
${CONSTRUCTING+ __trampolines_end = . ; }
/* For future tablejump instruction arrays for 3 byte pc devices.
We don't relax jump/call instructions within these sections. */
*(.jumptables)
*(.jumptables*)
/* For code that needs to reside in the lower 128k progmem. */
*(.lowtext)
*(.lowtext*)
${CONSTRUCTING+ __ctors_start = . ; }
${CONSTRUCTING+ *(.ctors) }
${CONSTRUCTING+ __ctors_end = . ; }
${CONSTRUCTING+ __dtors_start = . ; }
${CONSTRUCTING+ *(.dtors) }
${CONSTRUCTING+ __dtors_end = . ; }
KEEP(SORT(*)(.ctors))
KEEP(SORT(*)(.dtors))
/* From this point on, we don't bother about wether the insns are
below or above the 16 bits boundary. */
*(.init0) /* Start here after reset. */
KEEP (*(.init0))
*(.init1)
KEEP (*(.init1))
*(.init2) /* Clear __zero_reg__, set up stack pointer. */
KEEP (*(.init2))
*(.init3)
KEEP (*(.init3))
*(.init4) /* Initialize data and BSS. */
KEEP (*(.init4))
*(.init5)
KEEP (*(.init5))
*(.init6) /* C++ constructors. */
KEEP (*(.init6))
*(.init7)
KEEP (*(.init7))
*(.init8)
KEEP (*(.init8))
*(.init9) /* Call main(). */
KEEP (*(.init9))
*(.text)
${RELOCATING+. = ALIGN(2);}
*(.text.*)
${RELOCATING+. = ALIGN(2);}
*(.fini9) /* _exit() starts here. */
KEEP (*(.fini9))
*(.fini8)
KEEP (*(.fini8))
*(.fini7)
KEEP (*(.fini7))
*(.fini6) /* C++ destructors. */
KEEP (*(.fini6))
*(.fini5)
KEEP (*(.fini5))
*(.fini4)
KEEP (*(.fini4))
*(.fini3)
KEEP (*(.fini3))
*(.fini2)
KEEP (*(.fini2))
*(.fini1)
KEEP (*(.fini1))
*(.fini0) /* Infinite loop after program termination. */
KEEP (*(.fini0))
${RELOCATING+ _etext = . ; }
} ${RELOCATING+ > text}
.data ${RELOCATING-0} : ${RELOCATING+AT (ADDR (.text) + SIZEOF (.text))}
{
${RELOCATING+ PROVIDE (__data_start = .) ; }
*(.data)
KEEP (*(.data))
*(.data*)
*(.rodata) /* We need to include .rodata here if gcc is used */
*(.rodata*) /* with -fdata-sections. */
*(.gnu.linkonce.d*)
${RELOCATING+. = ALIGN(2);}
${RELOCATING+ _edata = . ; }
${RELOCATING+ PROVIDE (__data_end = .) ; }
} ${RELOCATING+ > data}
.bss ${RELOCATING-0} :${RELOCATING+ AT (ADDR (.bss))}
{
${RELOCATING+ PROVIDE (__bss_start = .) ; }
*(.bss)
*(.bss*)
*(COMMON)
${RELOCATING+ PROVIDE (__bss_end = .) ; }
} ${RELOCATING+ > data}
${RELOCATING+ __data_load_start = LOADADDR(.data); }
${RELOCATING+ __data_load_end = __data_load_start + SIZEOF(.data); }
/* Global data not cleared after reset. */
.noinit ${RELOCATING-0}:
{
${RELOCATING+ PROVIDE (__noinit_start = .) ; }
*(.noinit*)
${RELOCATING+ PROVIDE (__noinit_end = .) ; }
${RELOCATING+ _end = . ; }
${RELOCATING+ PROVIDE (__heap_start = .) ; }
} ${RELOCATING+ > data}
.lock ${RELOCATING-0}:
{
KEEP(*(.lock*))
} ${RELOCATING+ > lock}
.signature ${RELOCATING-0}:
{
KEEP(*(.signature*))
} ${RELOCATING+ > signature}
.config ${RELOCATING-0}:
{
KEEP(*(.config*))
} ${RELOCATING+ > config}
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info) *(.gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
}
EOF

9
opcodes/ChangeLog
View file

@ -1,3 +1,12 @@
2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
Pitchumani Sivanupandi <pitchumani.s@atmel.com>
Soundararajan <Sounderarajan.D@atmel.com>
* avr-dis.c (avr_operand): Handle constraint j for 16 bit lds/sts.
(print_insn_avr): Do not select opcode if insn ISA is avrtiny and machine
is not avrtiny.
2014-06-26 Philippe De Muyter <phdm@macqel.be>
* or1k-desc.h (spr_field_masks): Add U suffix to the end of long

15
opcodes/avr-dis.c
View file

@ -187,6 +187,17 @@ avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constra
sprintf (buf, "0x%04X", insn2);
break;
case 'j':
{
unsigned int val = ((insn & 0xf) | ((insn & 0x600) >> 5)
| ((insn & 0x100) >> 2));
if (val > 0 && !(insn & 0x100))
val |= 0x80;
sprintf (buf, "0x%02x", val);
sprintf (buf, "%d", val);
}
break;
case 'M':
sprintf (buf, "0x%02X", ((insn & 0xf00) >> 4) | (insn & 0xf));
sprintf (comment, "%d", ((insn & 0xf00) >> 4) | (insn & 0xf));
@ -329,8 +340,12 @@ print_insn_avr (bfd_vma addr, disassemble_info *info)
for (opcode = avr_opcodes, maskptr = avr_bin_masks;
opcode->name;
opcode++, maskptr++)
{
if ((opcode->isa == AVR_ISA_TINY) && (info->mach != bfd_mach_avrtiny))
continue;
if ((insn & *maskptr) == opcode->bin_opcode)
break;
}
/* Special case: disassemble `ldd r,b+0' as `ld r,b', and
`std b+0,r' as `st b,r' (next entry in the table). */