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Add support for .extCondCode, .extCoreRegister and .extAuxRegister.

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gas/
2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>

	* testsuite/gas/arc/textauxregister.d: New file.
	* testsuite/gas/arc/textauxregister.s: Likewise.
	* testsuite/gas/arc/textcondcode.d: Likewise.
	* testsuite/gas/arc/textcondcode.s: Likewise.
	* testsuite/gas/arc/textcoreregister.d: Likewise.
	* testsuite/gas/arc/textcoreregister.s: Likewise.
	* testsuite/gas/arc/textpseudoop.d: Likewise.
	* testsuite/gas/arc/textpseudoop.s: Likewise.
	* testsuite/gas/arc/ld2.d: Update test.
	* testsuite/gas/arc/st.d: Likewise.
	* testsuite/gas/arc/taux.d: Likewise.
	* doc/c-arc.texi (ARC Directives): Add .extCondCode,
	.extCoreRegister and .extAuxRegister documentation.
	* config/tc-arc.c (arc_extcorereg): New function.
	(md_pseudo_table): Add .extCondCode, .extCoreRegister and
	.extAuxRegister pseudo-ops.
	(extRegister_t): New type.
	(ext_condcode, arc_aux_hash): New global variable.
	(find_opcode_match): Check for extensions.
	(preprocess_operands): Likewise.
	(md_begin): Add aux registers in a hash.
	(assemble_insn): Update use arc_flags member.
	(tokenize_extregister): New function.
	(create_extcore_section): Likewise.
	* config/tc-arc.h (MAX_FLAG_NAME_LENGHT): Increase to 10.
	(arc_flags): Delete code, add flgp.

include/
2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>

	* opcode/arc.h (flag_class_t): Update.
	(ARC_OPCODE_NONE): Define.
	(ARC_OPCODE_ARCALL): Likewise.
	(ARC_OPCODE_ARCFPX): Likewise.
	(ARC_REGISTER_READONLY): Likewise.
	(ARC_REGISTER_WRITEONLY): Likewise.
	(ARC_REGISTER_NOSHORT_CUT): Likewise.
	(arc_aux_reg): Add cpu.

opcodes/
2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-dis.c (find_format): Check for extension flags.
	(print_flags): New function.
	(print_insn_arc): Update for .extCondCode, .extCoreRegister and
	.extAuxRegister.
	* arc-ext.c (arcExtMap_coreRegName): Use
	LAST_EXTENSION_CORE_REGISTER.
	(arcExtMap_coreReadWrite): Likewise.
	(dump_ARC_extmap): Update printing.
	* arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
	(arc_aux_regs): Add cpu field.
	* arc-regs.h: Add cpu field, lower case name aux registers.

Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
This commit is contained in:
Claudiu Zissulescu 2016-04-06 16:08:04 +02:00
parent 1c2e355e48
commit f36e33dac1
23 changed files with 1114 additions and 476 deletions
Download patch file Download diff file Expand all files Collapse all files

24
include/opcode/arc.h
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@ -77,15 +77,19 @@ typedef enum
/* Flags class. */
typedef enum
{
F_CLASS_NONE,
F_CLASS_NONE = 0,
/* At most one flag from the set of flags can appear in the
instruction. */
F_CLASS_OPTIONAL,
F_CLASS_OPTIONAL = (1 << 0),
/* Exactly one from from the set of flags must appear in the
instruction. */
F_CLASS_REQUIRED,
F_CLASS_REQUIRED = (1 << 1),
/* The conditional code can be extended over the standard variants
via .extCondCode pseudo-op. */
F_CLASS_EXTEND = (1 << 2)
} flag_class_t;
/* The opcode table is an array of struct arc_opcode. */
@ -132,12 +136,18 @@ struct arc_opcode
extern const struct arc_opcode arc_opcodes[];
/* CPU Availability. */
#define ARC_OPCODE_NONE 0x0000
#define ARC_OPCODE_ARC600 0x0001 /* ARC 600 specific insns. */
#define ARC_OPCODE_ARC700 0x0002 /* ARC 700 specific insns. */
#define ARC_OPCODE_ARCv2EM 0x0004 /* ARCv2 EM specific insns. */
#define ARC_OPCODE_ARCv2HS 0x0008 /* ARCv2 HS specific insns. */
#define ARC_OPCODE_NPS400 0x0010 /* NPS400 specific insns. */
/* CPU combi. */
#define ARC_OPCODE_ARCALL (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 \
| ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
#define ARC_OPCODE_ARCFPX (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM)
/* CPU extensions. */
#define ARC_EA 0x0001
#define ARC_CD 0x0001 /* Mutual exclusive with EA. */
@ -406,6 +416,11 @@ struct arc_aux_reg
/* Register address. */
int address;
/* One bit flags for the opcode. These are primarily used to
indicate specific processors and environments support the
instructions. */
unsigned cpu;
/* AUX register subclass. */
insn_subclass_t subclass;
@ -503,6 +518,9 @@ extern const unsigned arc_num_relax_opcodes;
#define ARC_SUFFIX_COND (1 << 1)
#define ARC_SUFFIX_FLAG (1 << 2)
#define ARC_REGISTER_READONLY (1 << 0)
#define ARC_REGISTER_WRITEONLY (1 << 1)
#define ARC_REGISTER_NOSHORT_CUT (1 << 2)
/* Constants needed to initialize extension instructions. */
extern const unsigned char flags_none[MAX_INSN_FLGS + 1];