o Implement generic halt/restart/abort module.

Use in tic80 and d30v simulators.
o	Add signal hook to sim-core module
This commit is contained in:
Andrew Cagney 1997-05-19 03:42:33 +00:00
parent 11ab132f16
commit f03b093cd3
18 changed files with 1415 additions and 377 deletions

View file

@ -69,39 +69,4 @@ extern void engine_init
(SIM_DESC sd);
/* Mechanisms for stopping/restarting the simulation.
A non NULL CPU argument designates the processor that is initiating
the halt. After the simulation has stopped that processor should
be marked as the last one active */
extern void engine_error
(SIM_DESC sd,
sim_cpu *cpu,
instruction_address cia,
const char *fmt,
...);
extern void engine_halt
(SIM_DESC sd,
sim_cpu *cpu,
instruction_address cia,
enum sim_stop reason,
int siggnal);
extern void engine_restart
(SIM_DESC sd,
sim_cpu *cpu,
instruction_address cia);
/* SIMULATE INSTRUCTIONS, various different ways of achieving the same
thing (others later) */
extern void engine_run_until_stop
(SIM_DESC sd,
volatile int *keep_running);
extern void engine_step
(SIM_DESC sd);
#endif