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o Implement generic halt/restart/abort module.

Browse source 
Use in tic80 and d30v simulators.
o	Add signal hook to sim-core module
This commit is contained in:
Andrew Cagney 1997-05-19 03:42:33 +00:00
parent 11ab132f16
commit f03b093cd3
18 changed files with 1415 additions and 377 deletions
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25
sim/tic80/ChangeLog
View file

@ -1,3 +1,28 @@
Fri May 16 14:35:30 1997 Andrew Cagney <cagney@b1.cygnus.com>
* insns (illegal, fp_unavailable): Halt instead of abort the
simulator.
* insns: Replace calls to engine_error with sim_engine_abort.
Ditto for engine_halt V sim_engine_halt.
Tue May 13 15:24:12 1997 Andrew Cagney <cagney@b2.cygnus.com>
* interp.c (engine_run_until_stop): Delete. Moved to common.
(engine_step): Ditto.
(engine_step): Ditto.
(engine_halt): Ditto.
(engine_restart): Ditto.
(engine_halt): Ditto.
(engine_error): Ditto.
* sim-calls.c (sim_stop): Delete. Moved to common.
(sim_stop_reason): Ditto.
(sim_resume): Ditto.
* Makefile.in (SIM_OBJS): Link in generic sim-engine, sim-run,
sim-resume, sim-reason, sim-stop modules.
Fri May 16 11:57:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
* ic (compute): Drop check for REG == 0, now always forced to

10
sim/tic80/Makefile.in
View file

@ -10,7 +10,7 @@
# Not all of these need to be mentioned, only the necessary ones.
# List of object files, less common parts.
SIM_OBJS = sim-endian.o sim-bits.o sim-config.o interp.o \
SIM_OBJS = sim-endian.o sim-bits.o sim-config.o \
support.o idecode.o semantics.o itable.o misc.o \
sim-calls.o \
sim-events.o \
@ -22,7 +22,12 @@ SIM_OBJS = sim-endian.o sim-bits.o sim-config.o interp.o \
sim-options.o \
sim-trace.o \
sim-profile.o \
sim-fpu.o
sim-fpu.o \
sim-engine.o \
sim-run.o \
sim-resume.o \
sim-stop.o \
sim-reason.o
# List of extra dependencies.
# Generally this consists of simulator specific files included by sim-main.h.
@ -142,6 +147,7 @@ ENGINE_H = \
$(srcdir)/../common/sim-core.h \
$(srcdir)/../common/sim-events.h \
$(srcdir)/../common/sim-fpu.h \
$(srcdir)/../common/sim-engine.h \
idecode.o: $(ENGINE_H)
semantics.o: $(ENGINE_H)

109
sim/tic80/insns
View file

@ -21,12 +21,13 @@
// The following is called when ever an illegal instruction is encountered.
::internal::illegal
engine_error (SD, CPU, cia,
"illegal instruction at 0x%lx", cia.ip);
sim_io_eprintf (SD, "0x%lx: illegal instruction\n", (unsigned long) cia.ip);
sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIGILL);
// The following is called when ever an FP op is attempted with FPU disabled.
::internal::fp_unavailable
engine_error (SD, CPU, cia,
"floating-point unavailable at 0x%lx", cia.ip);
sim_io_eprintf (SD, "0x%lx: floating-point unavailable\n", (unsigned long) cia.ip);
sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIGFPE);
// Handle a branch instruction
instruction_address::function::do_branch:int annul, address_word target, int rLink_p, unsigned32 *rLink
@ -184,7 +185,7 @@ instruction_address::function::do_bcnd:instruction_address nia, int Cond, unsign
case 0: val = SEXT32 (source, 7); break;
case 1: val = SEXT32 (source, 15); break;
case 2: val = source; break;
default: engine_error (SD, CPU, cia, "bcnd - reserved size");
default: sim_engine_abort (SD, CPU, cia, "bcnd - reserved size");
}
switch (code)
{
@ -271,28 +272,28 @@ void::function::do_cmnd:signed32 source
int PP = EXTRACTED32 (source, 3, 0);
/* what is implemented? */
if (PP != 0)
engine_error (SD, CPU, cia, "0x%lx: cmnd - PPs not supported",
(unsigned long) cia.ip);
sim_engine_abort (SD, CPU, cia, "0x%lx: cmnd - PPs not supported",
(unsigned long) cia.ip);
if (VC != 0)
engine_error (SD, CPU, cia, "0x%lx: cmnd - VC not supported",
(unsigned long) cia.ip);
sim_engine_abort (SD, CPU, cia, "0x%lx: cmnd - VC not supported",
(unsigned long) cia.ip);
if (TC != 0)
engine_error (SD, CPU, cia, "0x%lx: cmnd - TC not supported",
(unsigned long) cia.ip);
sim_engine_abort (SD, CPU, cia, "0x%lx: cmnd - TC not supported",
(unsigned long) cia.ip);
if (MP)
{
if (Reset || Halt)
engine_halt (SD, CPU, cia, sim_exited, 0);
sim_engine_halt (SD, CPU, NULL, cia, sim_exited, 0);
if (Unhalt)
engine_error (SD, CPU, cia, "0x%lx: cmnd - Can not unhalt the MP",
(unsigned long) cia.ip);
sim_engine_abort (SD, CPU, cia, "0x%lx: cmnd - Can not unhalt the MP",
(unsigned long) cia.ip);
/* if (ICR || DCR); */
if (Task)
engine_error (SD, CPU, cia, "0x%lx: cmnd - Can not Task the MP",
(unsigned long) cia.ip);
sim_engine_abort (SD, CPU, cia, "0x%lx: cmnd - Can not Task the MP",
(unsigned long) cia.ip);
if (Msg)
engine_error (SD, CPU, cia, "0x%lx: cmnd - Msg to MP not suported",
(unsigned long) cia.ip);
sim_engine_abort (SD, CPU, cia, "0x%lx: cmnd - Msg to MP not suported",
(unsigned long) cia.ip);
}
TRACE_SINK1 (MY_INDEX, source);
31./,21.0b0000010,14.UI::::cmnd i
@ -401,11 +402,11 @@ sim_fpu::function::get_fp_reg:int reg, unsigned32 val, int precision
return sim_fpu_32to (val);
case 1: /* double */
if (reg < 0)
engine_error (SD, CPU, cia, "DP immediate invalid");
sim_engine_abort (SD, CPU, cia, "DP immediate invalid");
if (reg & 1)
engine_error (SD, CPU, cia, "DP FP register must be even");
sim_engine_abort (SD, CPU, cia, "DP FP register must be even");
if (reg <= 1)
engine_error (SD, CPU, cia, "DP FP register must be >= 2");
sim_engine_abort (SD, CPU, cia, "DP FP register must be >= 2");
return sim_fpu_64to (INSERTED64 (GPR (reg + 1), 63, 32)
| INSERTED64 (GPR (reg), 31, 0));
case 2: /* 32 bit signed integer */
@ -413,7 +414,7 @@ sim_fpu::function::get_fp_reg:int reg, unsigned32 val, int precision
case 3: /* 32 bit unsigned integer */
return sim_fpu_u32to (val);
default:
engine_error (SD, CPU, cia, "Unsupported FP precision");
sim_engine_abort (SD, CPU, cia, "Unsupported FP precision");
}
return sim_fpu_i32to (0);
void::function::set_fp_reg:int Dest, sim_fpu val, int PD
@ -428,9 +429,9 @@ void::function::set_fp_reg:int Dest, sim_fpu val, int PD
{
unsigned64 v = sim_fpu_to64 (val);
if (Dest & 1)
engine_error (SD, CPU, cia, "DP FP Dest register must be even");
sim_engine_abort (SD, CPU, cia, "DP FP Dest register must be even");
if (Dest <= 1)
engine_error (SD, CPU, cia, "DP FP Dest register must be >= 2");
sim_engine_abort (SD, CPU, cia, "DP FP Dest register must be >= 2");
GPR (Dest + 0) = VL4_8 (v);
GPR (Dest + 1) = VH4_8 (v);
break;
@ -446,7 +447,7 @@ void::function::set_fp_reg:int Dest, sim_fpu val, int PD
break;
}
default:
engine_error (SD, CPU, cia, "Unsupported FP precision");
sim_engine_abort (SD, CPU, cia, "Unsupported FP precision");
}
// fadd.{s|d}{s|d}{s|d}
@ -634,10 +635,10 @@ instruction_address::function::do_jsr:instruction_address nia, signed32 *rLink,
TRACE_UCOND_BR (MY_INDEX, target);
nia = do_branch (_SD, annul, target, 1, rLink);
if (nia.dp & 0x3)
engine_error (SD, CPU, cia,
"0x%lx: destination address 0x%lx misaligned",
(unsigned long) cia.ip,
(unsigned long) nia.dp);
sim_engine_abort (SD, CPU, cia,
"0x%lx: destination address 0x%lx misaligned",
(unsigned long) cia.ip,
(unsigned long) nia.dp);
return nia;
31.Link,26.Base,21.0b100010,15.A,14.SignedOffset::::jsr i
nia = do_jsr (_SD, nia, rLink, A, vSignedOffset, vBase);
@ -675,8 +676,8 @@ void::function::do_ld:int Dest, unsigned32 base, unsigned32 *rBase, int m , int
{
signed64 val;
if (Dest & 0x1)
engine_error (SD, CPU, cia, "0x%lx: ld.d to odd register %d",
cia.ip, Dest);
sim_engine_abort (SD, CPU, cia, "0x%lx: ld.d to odd register %d",
cia.ip, Dest);
addr = base + (S ? (offset << 3) : offset);
if (m)
*rBase = addr;
@ -687,7 +688,7 @@ void::function::do_ld:int Dest, unsigned32 base, unsigned32 *rBase, int m , int
break;
default:
addr = -1;
engine_error (SD, CPU, cia, "ld - invalid sz %d", sz);
sim_engine_abort (SD, CPU, cia, "ld - invalid sz %d", sz);
}
TRACE_LD (MY_INDEX, GPR(Dest), m, S, base, offset);
31.Dest,26.Base,21.0b0100,17.m,16.sz,14.SignedOffset::::ld i
@ -714,7 +715,7 @@ void::function::do_ld_u:unsigned32 *rDest, unsigned32 base, unsigned32 *rBase, i
break;
default:
addr = -1;
engine_error (SD, CPU, cia, "ld.u - invalid sz %d", sz);
sim_engine_abort (SD, CPU, cia, "ld.u - invalid sz %d", sz);
}
if (m)
*rBase = addr;
@ -867,9 +868,9 @@ void::function::do_shift:int Dest, unsigned32 source, int Merge, int i, int n, i
shiftmask = ~((1 << nRotate) - 1); /* inverted */
break;
default:
engine_error (SD, CPU, cia,
"0x%lx: Invalid merge (%d) for shift",
cia.ip, source);
sim_engine_abort (SD, CPU, cia,
"0x%lx: Invalid merge (%d) for shift",
cia.ip, source);
shiftmask = 0;
}
/* and the composite mask */
@ -894,9 +895,9 @@ void::function::do_shift:int Dest, unsigned32 source, int Merge, int i, int n, i
}
break;
default:
engine_error (SD, CPU, cia,
"0x%lx: Invalid merge (%d)",
cia.ip, source);
sim_engine_abort (SD, CPU, cia,
"0x%lx: Invalid merge (%d)",
cia.ip, source);
}
TRACE_SHIFT (MY_INDEX, GPR (Dest), input, i, n, Merge, EndMask, Rotate);
@ -942,9 +943,9 @@ void::function::do_st:int Source, unsigned32 base, unsigned32 *rBase, int m , in
{
signed64 val;
if (Source & 0x1)
engine_error (SD, CPU, cia,
"0x%lx: st.d with odd source register %d",
cia.ip, Source);
sim_engine_abort (SD, CPU, cia,
"0x%lx: st.d with odd source register %d",
cia.ip, Source);
addr = base + (S ? (offset << 3) : offset);
val = (V4_H8 (GPR(Source + 1)) | V4_L8 (GPR(Source)));
STORE (addr, 8, val);
@ -952,7 +953,7 @@ void::function::do_st:int Source, unsigned32 base, unsigned32 *rBase, int m , in
break;
default:
addr = -1;
engine_error (SD, CPU, cia, "st - invalid sz %d", sz);
sim_engine_abort (SD, CPU, cia, "st - invalid sz %d", sz);
}
if (m)
*rBase = addr;
@ -1035,7 +1036,7 @@ void::function::do_trap:unsigned32 trap_number
{
case 1: /* EXIT */
{
engine_halt (SD, CPU, cia, sim_exited, GPR(2));
sim_engine_halt (SD, CPU, NULL, cia, sim_exited, GPR(2));
break;
}
case 4: /* WRITE */
@ -1056,9 +1057,9 @@ void::function::do_trap:unsigned32 trap_number
sim_io_write_stderr (SD, &c, 1);
}
else
engine_error (SD, CPU, cia,
"0x%lx: write to invalid fid %d",
(unsigned long) cia.ip, GPR(2));
sim_engine_abort (SD, CPU, cia,
"0x%lx: write to invalid fid %d",
(unsigned long) cia.ip, GPR(2));
GPR(2) = GPR(6);
break;
}
@ -1069,13 +1070,13 @@ void::function::do_trap:unsigned32 trap_number
GPR(2) = -22; /* -EINVAL */
break;
}
engine_error (SD, CPU, cia,
"0x%lx: unknown syscall %d",
(unsigned long) cia.ip, GPR(15));
sim_engine_abort (SD, CPU, cia,
"0x%lx: unknown syscall %d",
(unsigned long) cia.ip, GPR(15));
}
break;
case 73:
engine_halt (SD, CPU, cia, sim_stopped, SIGTRAP);
sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIGTRAP);
/* Add a few traps for now to print the register state */
case 74:
@ -1096,9 +1097,9 @@ void::function::do_trap:unsigned32 trap_number
break;
default:
engine_error (SD, CPU, cia,
"0x%lx: unsupported trap %d",
(unsigned long) cia.ip, trap_number);
sim_engine_abort (SD, CPU, cia,
"0x%lx: unsupported trap %d",
(unsigned long) cia.ip, trap_number);
}
31./,27.0,26./,21.0b0000001,14.UTN::::trap i
do_trap (_SD, UTN);

21
sim/tic80/interp.c
View file

@ -36,16 +36,8 @@
#endif
#endif
void
engine_init (SIM_DESC sd)
{
memset (&STATE_CPU (sd, 0)->reg, 0, sizeof STATE_CPU (sd, 0)->reg);
memset (&STATE_CPU (sd, 0)->cia, 0, sizeof STATE_CPU (sd, 0)->cia);
CPU_STATE (STATE_CPU (sd, 0)) = sd;
}
/* Mechanisms for stopping/restarting the simulation */
#if 0
void
engine_error (SIM_DESC sd,
@ -59,13 +51,7 @@ engine_error (SIM_DESC sd,
sim_io_evprintf (sd, fmt, ap);
va_end (ap);
if (sd->halt_ok)
{
sim_io_eprintf (sd, "\n");
engine_halt (sd, cpu, cia, sim_stopped, SIGABRT);
}
else
sim_io_error (sd, " - aborting simulation");
sim_halt (sd, cpu, NULL, cia, sim_stopped, SIGABRT);
}
void
@ -139,3 +125,6 @@ engine_step (SIM_DESC sd)
engine_halt (sd, cpu, cia, sim_stopped, SIGTRAP);
}
}
#endif

44
sim/tic80/sim-calls.c
View file

@ -80,7 +80,13 @@ sim_open (SIM_OPEN_KIND kind, char **argv)
return 0;
}
engine_init(&simulation);
/* Initialize the main processor */
memset (&STATE_CPU (&simulation, 0)->reg, 0, sizeof STATE_CPU (&simulation, 0)->reg);
memset (&STATE_CPU (&simulation, 0)->acc, 0, sizeof STATE_CPU (&simulation, 0)->acc);
memset (&STATE_CPU (&simulation, 0)->cr, 0, sizeof STATE_CPU (&simulation, 0)->cr);
STATE_CPU (&simulation, 0)->is_user_mode = 0;
memset (&STATE_CPU (&simulation, 0)->cia, 0, sizeof STATE_CPU (&simulation, 0)->cia);
CPU_STATE (STATE_CPU (&simulation, 0)) = &simulation;
#define TIC80_MEM_START 0x2000000
#define TIC80_MEM_SIZE 0x100000
@ -230,42 +236,6 @@ sim_create_inferior (SIM_DESC sd,
}
volatile int keep_running = 1;
void
sim_stop_reason (SIM_DESC sd, enum sim_stop *reason, int *sigrc)
{
if (!keep_running)
{
*reason = sim_stopped;
*sigrc = SIGINT;
keep_running = 1;
}
else
{
*reason = simulation.reason;
*sigrc = simulation.siggnal;
}
}
int
sim_stop (SIM_DESC sd)
{
keep_running = 0;
return 1;
}
void
sim_resume (SIM_DESC sd, int step, int siggnal)
{
/* keep_running = 1 - in sim_stop_reason */
if (step)
engine_step (sd);
else
engine_run_until_stop (sd, &keep_running);
}
void
sim_do_command (SIM_DESC sd, char *cmd)
{

35
sim/tic80/sim-main.h
View file

@ -69,39 +69,4 @@ extern void engine_init
(SIM_DESC sd);
/* Mechanisms for stopping/restarting the simulation.
A non NULL CPU argument designates the processor that is initiating
the halt. After the simulation has stopped that processor should
be marked as the last one active */
extern void engine_error
(SIM_DESC sd,
sim_cpu *cpu,
instruction_address cia,
const char *fmt,
...);
extern void engine_halt
(SIM_DESC sd,
sim_cpu *cpu,
instruction_address cia,
enum sim_stop reason,
int siggnal);
extern void engine_restart
(SIM_DESC sd,
sim_cpu *cpu,
instruction_address cia);
/* SIMULATE INSTRUCTIONS, various different ways of achieving the same
thing (others later) */
extern void engine_run_until_stop
(SIM_DESC sd,
volatile int *keep_running);
extern void engine_step
(SIM_DESC sd);
#endif