Add support for unindexed form of Addressing Mode 5
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Nick Clifton
parent
062103babe
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f02232aaa3
8 changed files with 171 additions and 17 deletions
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@ -1,3 +1,8 @@
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2003-08-19 Nick Clifton <nickc@redhat.com>
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* config/tc-arm.c (cp_address_required_here): Add code to handle
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unindexed addressing mode.
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2003-08-19 Alan Modra <amodra@bigpond.net.au>
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* config/tc-ppc.c (md_parse_option): Handle -m440.
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@ -3329,22 +3329,96 @@ cp_address_required_here (str, wb_ok)
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{
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p++;
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if (wb_ok && skip_past_comma (& p) == SUCCESS)
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{
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/* [Rn], #expr */
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write_back = WRITE_BACK;
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skip_whitespace (p);
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if (reg == REG_PC)
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if (*p == '\0')
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{
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/* As an extension to the official ARM syntax we allow:
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[Rn]
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as a short hand for:
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[Rn,#0] */
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inst.instruction |= PRE_INDEX | INDEX_UP;
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*str = p;
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return SUCCESS;
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}
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if (skip_past_comma (& p) == FAIL)
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{
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inst.error = _("comma expected after closing square bracket");
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return FAIL;
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}
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skip_whitespace (p);
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if (*p == '#')
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{
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if (wb_ok)
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{
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inst.error = _("pc may not be used in post-increment");
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/* [Rn], #expr */
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write_back = WRITE_BACK;
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if (reg == REG_PC)
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{
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inst.error = _("pc may not be used in post-increment");
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return FAIL;
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}
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if (cp_address_offset (& p) == FAIL)
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return FAIL;
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}
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else
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pre_inc = PRE_INDEX | INDEX_UP;
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}
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else if (*p == '{')
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{
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int option;
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/* [Rn], {<expr>} */
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p++;
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skip_whitespace (p);
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if (my_get_expression (& inst.reloc.exp, & p))
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return FAIL;
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if (inst.reloc.exp.X_op == O_constant)
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{
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option = inst.reloc.exp.X_add_number;
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if (option > 255 || option < 0)
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{
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inst.error = _("'option' field too large");
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return FAIL;
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}
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skip_whitespace (p);
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if (*p != '}')
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{
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inst.error = _("'}' expected at end of 'option' field");
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return FAIL;
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}
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else
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{
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p++;
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inst.instruction |= option;
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inst.instruction |= INDEX_UP;
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}
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}
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else
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{
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inst.error = _("non-constant expressions for 'option' field not supported");
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return FAIL;
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}
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if (cp_address_offset (& p) == FAIL)
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return FAIL;
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}
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else
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pre_inc = PRE_INDEX | INDEX_UP;
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{
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inst.error = _("# or { expected after comma");
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return FAIL;
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}
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}
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else
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{
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@ -1,3 +1,9 @@
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2003-08-19 Nick Clifton <nickc@redhat.com>
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* gas/arm/copro.s: Add tests of Addressing Mode 5 (Unindexed).
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* gas/arm/arm.exp: Run copro.s as a dump test.
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* gas/arm/copro.d: New file: expected disassembly of copro.s
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2003-08-16 Jason Eckhardt <jle@rice.edu>
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* gas/i860/pseudo-ops01.{s,d}: New files.
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@ -40,7 +40,7 @@ if {[istarget *arm*-*-*] || [istarget "xscale-*-*"]} then {
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run_dump_test "arch5tej"
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gas_test "copro.s" "" $stdoptlist "Co processor instructions"
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run_dump_test "copro"
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gas_test "immed.s" "" $stdoptlist "immediate expressions"
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39
gas/testsuite/gas/arm/copro.d
Normal file
39
gas/testsuite/gas/arm/copro.d
Normal file
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@ -0,0 +1,39 @@
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#objdump: -dr --prefix-addresses --show-raw-insn
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#name: ARM CoProcessor Instructions
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#as: -march=armv5te -EL
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# Test the standard ARM co-processor instructions:
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.*: +file format .*arm.*
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Disassembly of section .text:
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0+000 <[^>]*> ee421103 dvfs f1, f2, f3
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0+004 <[^>]*> 0e3414a5 cfadddeq mvd1, mvd4, mvd5
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0+008 <[^>]*> ed939500 cfldr32 mvfx9, \[r3\]
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0+00c <[^>]*> edd1e108 ldfp f6, \[r1, #32\]
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0+010 <[^>]*> 4db200ff ldcmi 0, cr0, \[r2, #1020\]!
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0+014 <[^>]*> 5cf31710 ldcpll 7, cr1, \[r3\], #64
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0+018 <[^>]*> ed1f8001 ldc 0, cr8, \[pc, -#4\]
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0+01c <[^>]*> ed830500 cfstr32 mvfx0, \[r3\]
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0+020 <[^>]*> edc0f302 stcl 3, cr15, \[r0, #8\]
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0+024 <[^>]*> 0da2c419 cfstrseq mvf12, \[r2, #100\]!
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0+028 <[^>]*> 3ca4860c stccc 6, cr8, \[r4\], #48
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0+02c <[^>]*> ed0f7101 stfs f7, \[pc, -#4\]
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0+030 <[^>]*> ee715212 mrc 2, 3, r5, cr1, cr2, \{0\}
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0+034 <[^>]*> aeb1f4f2 mrcge 4, 5, pc, cr1, cr2, \{7\}
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0+038 <[^>]*> ee21f711 mcr 7, 1, pc, cr1, cr1, \{0\}
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0+03c <[^>]*> be228519 cfsh64lt mvdx8, mvdx2, #9
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0+040 <[^>]*> ec907300 ldc 3, cr7, \[r0\], \{0\}
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0+044 <[^>]*> ec816e01 stc 14, cr6, \[r1\], \{1\}
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0+048 <[^>]*> fc925502 ldc2 5, cr5, \[r2\], \{2\}
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0+04c <[^>]*> fc834603 stc2 6, cr4, \[r3\], \{3\}
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0+050 <[^>]*> ecd43704 ldcl 7, cr3, \[r4\], \{4\}
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0+054 <[^>]*> ecc52805 stcl 8, cr2, \[r5\], \{5\}
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0+058 <[^>]*> fcd61906 ldc2l 9, cr1, \[r6\], \{6\}
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0+05c <[^>]*> fcc70a07 stc2l 10, cr0, \[r7\], \{7\}
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0+060 <[^>]*> ecd88bff ldcl 11, cr8, \[r8\], \{255\}
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0+064 <[^>]*> ecc99cfe stcl 12, cr9, \[r9\], \{254\}
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0+068 <[^>]*> ec507d04 mrrc 13, 0, r7, r0, cr4
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0+06c <[^>]*> ec407e05 mcrr 14, 0, r7, r0, cr5
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0+070 <[^>]*> ec507fff mrrc 15, 15, r7, r0, cr15
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0+074 <[^>]*> ec407efe mcrr 14, 15, r7, r0, cr14
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@ -22,3 +22,20 @@ bar:
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mcr p7, 1, r15, cr1, cr1
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mcrlt 5, 1, r8, cr2, cr9, 0
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@ The following patterns test Addressing Mode 5 "Unindexed"
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ldc 3, c7, [r0], {0}
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stc p14, c6, [r1], {1}
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ldc2 5, c5, [r2], {2}
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stc2 p6, c4, [r3], {3}
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ldcl 7, c3, [r4], {4}
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stcl p8, c2, [r5], {5}
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ldc2l 9, c1, [r6], {6}
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stc2l p10, c0, [r7], {7}
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ldcl 11, c8, [r8], {255}
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stcl p12, c9, [r9], {254}
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mrrc 13, 0, r7, r0, cr4
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mcrr p14, 0, r7, r0, cr5
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mrrc 15, 15, r7, r0, cr15
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mcrr p14, 15, r7, r0, cr14
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@ -1,3 +1,8 @@
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2003-08-19 Nick Clifton <nickc@redhat.com>
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* arm-dis.c (print_insn_arm: case 'A'): Add code to
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disassemble unindexed form of Addressing Mode 5.
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2003-08-19 Alan Modra <amodra@bigpond.net.au>
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* ppc-opc.c (PPC440): Define.
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@ -445,9 +445,11 @@ print_insn_arm (pc, info, given)
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case 'A':
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func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
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if ((given & 0x01000000) != 0)
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if ((given & (1 << 24)) != 0)
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{
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int offset = given & 0xff;
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if (offset)
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func (stream, ", %s#%d]%s",
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((given & 0x00800000) == 0 ? "-" : ""),
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@ -459,12 +461,18 @@ print_insn_arm (pc, info, given)
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else
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{
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int offset = given & 0xff;
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if (offset)
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func (stream, "], %s#%d",
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((given & 0x00800000) == 0 ? "-" : ""),
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offset * 4);
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func (stream, "]");
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if (given & (1 << 21))
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{
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if (offset)
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func (stream, ", %s#%d",
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((given & 0x00800000) == 0 ? "-" : ""),
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offset * 4);
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}
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else
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func (stream, "]");
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func (stream, ", {%d}", offset);
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}
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break;
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