x86: re-work build_modrm_byte()'s register assignment
The function has accumulated a number of special cases for no real reason. Some were necessary because insn attributes (SwapSources in particular) weren't suitably utilized instead. Note that the addition of SwapSources actually increases consistency among the templates: Like others which already have the attribute, these are all insns where the VEX.VVVV-encoded register comes first (or last when looking at the SDM). Note that the vexvvvv attribute now has merely boolean meaning anymore, in line with the SDM long having dropped the NDS/NDD/DDS concept of identifying encoding variants. The fallout will be taken care of subsequently, though, to not further clutter the change here. As to the TILEZERO special case: If more instructions like this appeared, a new attribute would likely be the way to go. But as long as it's only a single insn, going from the mnemonic is cheaper.
This commit is contained in:
Jan Beulich
parent
5f784ec927
commit
ecb96e5549
3 changed files with 172 additions and 347 deletions
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@ -8022,6 +8022,22 @@ process_operands (void)
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else if (i.tm.opcode_modifier.immext)
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process_immext ();
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/* TILEZERO is unusual in that it has a single operand encoded in ModR/M.reg,
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not ModR/M.rm. To avoid special casing this in build_modrm_byte(), fake a
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new destination operand here, while converting the source one to register
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number 0. */
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if (i.tm.mnem_off == MN_tilezero)
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{
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i.op[1].regs = i.op[0].regs;
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i.op[0].regs -= i.op[0].regs->reg_num;
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i.types[1] = i.types[0];
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i.tm.operand_types[1] = i.tm.operand_types[0];
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i.flags[1] = i.flags[0];
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i.operands++;
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i.reg_operands++;
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i.tm.operands++;
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}
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if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
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{
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static const i386_operand_type regxmm = {
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@ -8253,17 +8269,27 @@ static const reg_entry *
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build_modrm_byte (void)
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{
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const reg_entry *default_seg = NULL;
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unsigned int source, dest;
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bool vex_3_sources = (i.reg_operands + i.mem_operands == 4);
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unsigned int source = i.imm_operands - i.tm.opcode_modifier.immext
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/* Compensate for kludge in md_assemble(). */
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+ i.tm.operand_types[0].bitfield.imm1;
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unsigned int dest = i.operands - 1 - i.tm.opcode_modifier.immext;
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unsigned int v, op, reg_slot = ~0;
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if (vex_3_sources)
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/* Accumulator (in particular %st), shift count (%cl), and alike need
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to be skipped just like immediate operands do. */
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if (i.tm.operand_types[source].bitfield.instance)
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++source;
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while (i.tm.operand_types[dest].bitfield.instance)
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--dest;
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for (op = source; op < i.operands; ++op)
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if (i.tm.operand_types[op].bitfield.baseindex)
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break;
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if (i.reg_operands + i.mem_operands + (i.tm.extension_opcode != None) == 4)
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{
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unsigned int nds, reg_slot;
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expressionS *exp;
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dest = i.operands - 1;
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nds = dest - 1;
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/* There are 2 kinds of instructions:
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1. 5 operands: 4 register operands or 3 register operands
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plus 1 memory operand plus one Imm4 operand, VexXDS, and
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@ -8275,18 +8301,12 @@ build_modrm_byte (void)
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&& i.tm.opcode_modifier.vexw
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&& i.tm.operand_types[dest].bitfield.class == RegSIMD);
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/* If VexW1 is set, the first non-immediate operand is the source and
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the second non-immediate one is encoded in the immediate operand. */
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if (i.tm.opcode_modifier.vexw == VEXW1)
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{
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source = i.imm_operands;
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reg_slot = i.imm_operands + 1;
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}
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/* Of the first two non-immediate operands the one with the template
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not allowing for a memory one is encoded in the immediate operand. */
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if (source == op)
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reg_slot = source + 1;
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else
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{
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source = i.imm_operands + 1;
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reg_slot = i.imm_operands;
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}
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reg_slot = source++;
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if (i.imm_operands == 0)
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{
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@ -8316,159 +8336,42 @@ build_modrm_byte (void)
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|= register_number (i.op[reg_slot].regs) << 4;
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gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
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}
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gas_assert (i.tm.operand_types[nds].bitfield.class == RegSIMD);
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i.vex.register_specifier = i.op[nds].regs;
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}
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else
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source = dest = 0;
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/* i.reg_operands MUST be the number of real register operands;
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implicit registers do not count. If there are 3 register
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operands, it must be a instruction with VexNDS. For a
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instruction with VexNDD, the destination register is encoded
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in VEX prefix. If there are 4 register operands, it must be
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a instruction with VEX prefix and 3 sources. */
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if (i.mem_operands == 0
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&& ((i.reg_operands == 2
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&& i.tm.opcode_modifier.vexvvvv <= VEXXDS)
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|| (i.reg_operands == 3
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&& i.tm.opcode_modifier.vexvvvv == VEXXDS)
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|| (i.reg_operands == 4 && vex_3_sources)))
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for (v = source + 1; v < dest; ++v)
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if (v != reg_slot)
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break;
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if (v >= dest)
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v = ~0;
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if (i.tm.extension_opcode != None)
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{
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switch (i.operands)
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{
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case 2:
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source = 0;
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break;
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case 3:
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/* When there are 3 operands, one of them may be immediate,
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which may be the first or the last operand. Otherwise,
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the first operand must be shift count register (cl) or it
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is an instruction with VexNDS. */
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gas_assert (i.imm_operands == 1
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|| (i.imm_operands == 0
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&& (i.tm.opcode_modifier.vexvvvv == VEXXDS
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|| (i.types[0].bitfield.instance == RegC
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&& i.types[0].bitfield.byte))));
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if (operand_type_check (i.types[0], imm)
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|| (i.types[0].bitfield.instance == RegC
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&& i.types[0].bitfield.byte))
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source = 1;
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else
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source = 0;
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break;
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case 4:
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/* When there are 4 operands, the first two must be 8bit
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immediate operands. The source operand will be the 3rd
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one.
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For instructions with VexNDS, if the first operand
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an imm8, the source operand is the 2nd one. If the last
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operand is imm8, the source operand is the first one. */
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gas_assert ((i.imm_operands == 2
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&& i.types[0].bitfield.imm8
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&& i.types[1].bitfield.imm8)
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|| (i.tm.opcode_modifier.vexvvvv == VEXXDS
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&& i.imm_operands == 1
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&& (i.types[0].bitfield.imm8
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|| i.types[0].bitfield.imm8s
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|| i.types[i.operands - 1].bitfield.imm8)));
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if (i.imm_operands == 2)
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source = 2;
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else
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{
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if (i.types[0].bitfield.imm8)
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source = 1;
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else
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source = 0;
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}
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break;
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case 5:
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gas_assert (!is_evex_encoding (&i.tm));
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gas_assert (i.imm_operands == 1 && vex_3_sources);
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break;
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default:
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abort ();
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}
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if (!vex_3_sources)
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{
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dest = source + 1;
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if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
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{
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/* For instructions with VexNDS, the register-only source
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operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
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register. It is encoded in VEX prefix. */
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i386_operand_type op;
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unsigned int vvvv;
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/* Swap two source operands if needed. */
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if (i.tm.opcode_modifier.operandconstraint == SWAP_SOURCES)
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{
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vvvv = source;
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source = dest;
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}
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else
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vvvv = dest;
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op = i.tm.operand_types[vvvv];
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if ((dest + 1) >= i.operands
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|| ((op.bitfield.class != Reg
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|| (!op.bitfield.dword && !op.bitfield.qword))
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&& op.bitfield.class != RegSIMD
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&& op.bitfield.class != RegMask))
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abort ();
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i.vex.register_specifier = i.op[vvvv].regs;
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dest++;
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}
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}
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i.rm.mode = 3;
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/* One of the register operands will be encoded in the i.rm.reg
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field, the other in the combined i.rm.mode and i.rm.regmem
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fields. If no form of this instruction supports a memory
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destination operand, then we assume the source operand may
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sometimes be a memory operand and so we need to store the
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destination in the i.rm.reg field. */
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if (!i.tm.opcode_modifier.regmem
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&& operand_type_check (i.tm.operand_types[dest], anymem) == 0)
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{
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i.rm.reg = i.op[dest].regs->reg_num;
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i.rm.regmem = i.op[source].regs->reg_num;
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set_rex_vrex (i.op[dest].regs, REX_R, i.tm.opcode_modifier.sse2avx);
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set_rex_vrex (i.op[source].regs, REX_B, false);
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}
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else
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{
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i.rm.reg = i.op[source].regs->reg_num;
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i.rm.regmem = i.op[dest].regs->reg_num;
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set_rex_vrex (i.op[dest].regs, REX_B, i.tm.opcode_modifier.sse2avx);
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set_rex_vrex (i.op[source].regs, REX_R, false);
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}
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if (flag_code != CODE_64BIT && (i.rex & REX_R))
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{
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if (i.types[!i.tm.opcode_modifier.regmem].bitfield.class != RegCR)
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abort ();
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i.rex &= ~REX_R;
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add_prefix (LOCK_PREFIX_OPCODE);
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}
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if (dest != source)
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v = dest;
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dest = ~0;
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}
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else
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{ /* If it's not 2 reg operands... */
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unsigned int mem;
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gas_assert (source < dest);
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if (i.tm.opcode_modifier.operandconstraint == SWAP_SOURCES
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&& source != op)
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{
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unsigned int tmp = source;
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source = v;
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v = tmp;
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}
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if (v < MAX_OPERANDS)
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{
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gas_assert (i.tm.opcode_modifier.vexvvvv);
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i.vex.register_specifier = i.op[v].regs;
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}
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if (op < i.operands)
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{
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if (i.mem_operands)
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{
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unsigned int fake_zero_displacement = 0;
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unsigned int op;
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for (op = 0; op < i.operands; op++)
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if (i.flags[op] & Operand_Mem)
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break;
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gas_assert (op < i.operands);
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gas_assert (i.flags[op] & Operand_Mem);
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if (i.tm.opcode_modifier.sib)
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{
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@ -8698,140 +8601,62 @@ build_modrm_byte (void)
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exp->X_add_symbol = (symbolS *) 0;
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exp->X_op_symbol = (symbolS *) 0;
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}
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}
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else
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{
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i.rm.mode = 3;
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i.rm.regmem = i.op[op].regs->reg_num;
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set_rex_vrex (i.op[op].regs, REX_B, false);
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}
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mem = op;
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if (op == dest)
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dest = ~0;
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if (op == source)
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source = ~0;
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}
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else
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{
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i.rm.mode = 3;
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if (!i.tm.opcode_modifier.regmem)
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{
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gas_assert (source < MAX_OPERANDS);
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i.rm.regmem = i.op[source].regs->reg_num;
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set_rex_vrex (i.op[source].regs, REX_B,
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dest >= MAX_OPERANDS && i.tm.opcode_modifier.sse2avx);
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source = ~0;
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}
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else
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mem = ~0;
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if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
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{
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i.vex.register_specifier = i.op[2].regs;
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if (!i.mem_operands)
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{
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i.rm.mode = 3;
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i.rm.regmem = i.op[1].regs->reg_num;
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if ((i.op[1].regs->reg_flags & RegRex) != 0)
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i.rex |= REX_B;
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}
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gas_assert (dest < MAX_OPERANDS);
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i.rm.regmem = i.op[dest].regs->reg_num;
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set_rex_vrex (i.op[dest].regs, REX_B, i.tm.opcode_modifier.sse2avx);
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dest = ~0;
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}
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/* Fill in i.rm.reg or i.rm.regmem field with register operand
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(if any) based on i.tm.extension_opcode. Again, we must be
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careful to make sure that segment/control/debug/test/MMX
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registers are coded into the i.rm.reg field. */
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else if (i.reg_operands)
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{
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unsigned int op;
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unsigned int vex_reg = ~0;
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for (op = 0; op < i.operands; op++)
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if (i.types[op].bitfield.class == Reg
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|| i.types[op].bitfield.class == RegBND
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|| i.types[op].bitfield.class == RegMask
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|| i.types[op].bitfield.class == SReg
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|| i.types[op].bitfield.class == RegCR
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|| i.types[op].bitfield.class == RegDR
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|| i.types[op].bitfield.class == RegTR
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|| i.types[op].bitfield.class == RegSIMD
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|| i.types[op].bitfield.class == RegMMX)
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break;
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if (vex_3_sources)
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op = dest;
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else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
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{
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/* For instructions with VexNDS, the register-only
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source operand is encoded in VEX prefix. */
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gas_assert (mem != (unsigned int) ~0);
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if (op > mem || i.tm.cpu_flags.bitfield.cpucmpccxadd)
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{
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vex_reg = op++;
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gas_assert (op < i.operands);
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}
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else
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{
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/* Check register-only source operand when two source
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operands are swapped. */
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if (!i.tm.operand_types[op].bitfield.baseindex
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&& i.tm.operand_types[op + 1].bitfield.baseindex)
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{
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vex_reg = op;
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op += 2;
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gas_assert (mem == (vex_reg + 1)
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&& op < i.operands);
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}
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else
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{
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vex_reg = op + 1;
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gas_assert (vex_reg < i.operands);
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}
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}
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}
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else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
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{
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/* For instructions with VexNDD, the register destination
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is encoded in VEX prefix. */
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if (i.mem_operands == 0)
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{
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/* There is no memory operand. */
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gas_assert ((op + 2) == i.operands);
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vex_reg = op + 1;
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}
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else
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{
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/* There are only 2 non-immediate operands. */
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gas_assert (op < i.imm_operands + 2
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&& i.operands == i.imm_operands + 2);
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vex_reg = i.imm_operands + 1;
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}
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}
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else
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gas_assert (op < i.operands);
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if (vex_reg != (unsigned int) ~0)
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{
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i386_operand_type *type = &i.tm.operand_types[vex_reg];
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if ((type->bitfield.class != Reg
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|| (!type->bitfield.dword && !type->bitfield.qword))
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&& type->bitfield.class != RegSIMD
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&& type->bitfield.class != RegMask)
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abort ();
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i.vex.register_specifier = i.op[vex_reg].regs;
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}
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/* Don't set OP operand twice. */
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if (vex_reg != op)
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{
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/* If there is an extension opcode to put here, the
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register number must be put into the regmem field. */
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if (i.tm.extension_opcode != None)
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{
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i.rm.regmem = i.op[op].regs->reg_num;
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set_rex_vrex (i.op[op].regs, REX_B,
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i.tm.opcode_modifier.sse2avx);
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}
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else
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{
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i.rm.reg = i.op[op].regs->reg_num;
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set_rex_vrex (i.op[op].regs, REX_R,
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i.tm.opcode_modifier.sse2avx);
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}
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}
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/* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
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must set it to 3 to indicate this is a register operand
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in the regmem field. */
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if (!i.mem_operands)
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i.rm.mode = 3;
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}
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/* Fill in i.rm.reg field with extension opcode (if any). */
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if (i.tm.extension_opcode != None)
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i.rm.reg = i.tm.extension_opcode;
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}
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/* Fill in i.rm.reg field with extension opcode (if any) or the
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appropriate register. */
|
||||
if (i.tm.extension_opcode != None)
|
||||
i.rm.reg = i.tm.extension_opcode;
|
||||
else if (!i.tm.opcode_modifier.regmem && dest < MAX_OPERANDS)
|
||||
{
|
||||
i.rm.reg = i.op[dest].regs->reg_num;
|
||||
set_rex_vrex (i.op[dest].regs, REX_R, i.tm.opcode_modifier.sse2avx);
|
||||
}
|
||||
else
|
||||
{
|
||||
gas_assert (source < MAX_OPERANDS);
|
||||
i.rm.reg = i.op[source].regs->reg_num;
|
||||
set_rex_vrex (i.op[source].regs, REX_R, false);
|
||||
}
|
||||
|
||||
if (flag_code != CODE_64BIT && (i.rex & REX_R))
|
||||
{
|
||||
gas_assert (i.types[!i.tm.opcode_modifier.regmem].bitfield.class == RegCR);
|
||||
i.rex &= ~REX_R;
|
||||
add_prefix (LOCK_PREFIX_OPCODE);
|
||||
}
|
||||
|
||||
return default_seg;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1749,18 +1749,18 @@ vpsravd, 0x6646, AVX2, Modrm|Vex|Space0F38|VexVVVV=1|VexW=1|CheckOperandSize|NoS
|
|||
vpsrlv<dq>, 0x6645, AVX2, Modrm|Vex|Space0F38|VexVVVV|<dq:vexw>|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
|
||||
|
||||
// AVX gather instructions
|
||||
vgatherdpd, 0x6692, AVX2, Modrm|Vex|Space0F38|VexVVVV|VexW1|CheckOperandSize|NoSuf|VecSIB128, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex, RegXMM|RegYMM }
|
||||
vgatherdps, 0x6692, AVX2, Modrm|Vex|Space0F38|VexVVVV|VexW0|NoSuf|VecSIB128, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM }
|
||||
vgatherdps, 0x6692, AVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW0|NoSuf|VecSIB256, { RegYMM, Dword|Unspecified|BaseIndex, RegYMM }
|
||||
vgatherqp<sd>, 0x6693, AVX2, Modrm|Vex|Space0F38|VexVVVV|<sd:vexw>|NoSuf|VecSIB128, { RegXMM, <sd:elem>|Unspecified|BaseIndex, RegXMM }
|
||||
vgatherqpd, 0x6693, AVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW1|NoSuf|VecSIB256, { RegYMM, Qword|Unspecified|BaseIndex, RegYMM }
|
||||
vgatherqps, 0x6693, AVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW0|NoSuf|VecSIB256, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM }
|
||||
vpgatherdd, 0x6690, AVX2, Modrm|Vex|Space0F38|VexVVVV|VexW0|NoSuf|VecSIB128, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM }
|
||||
vpgatherdd, 0x6690, AVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW0|NoSuf|VecSIB256, { RegYMM, Dword|Unspecified|BaseIndex, RegYMM }
|
||||
vpgatherdq, 0x6690, AVX2, Modrm|Vex|Space0F38|VexVVVV|VexW1|CheckOperandSize|NoSuf|VecSIB128, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex, RegXMM|RegYMM }
|
||||
vpgatherq<dq>, 0x6691, AVX2, Modrm|Vex|Space0F38|VexVVVV|<dq:vexw>|NoSuf|VecSIB128, { RegXMM, <dq:elem>|Unspecified|BaseIndex, RegXMM }
|
||||
vpgatherqd, 0x6691, AVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW0|NoSuf|VecSIB256, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM }
|
||||
vpgatherqq, 0x6691, AVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW1|NoSuf|VecSIB256, { RegYMM, Qword|Unspecified|BaseIndex, RegYMM }
|
||||
vgatherdpd, 0x6692, AVX2, Modrm|Vex|Space0F38|VexVVVV|VexW1|SwapSources|CheckOperandSize|NoSuf|VecSIB128, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex, RegXMM|RegYMM }
|
||||
vgatherdps, 0x6692, AVX2, Modrm|Vex128|Space0F38|VexVVVV|VexW0|SwapSources|NoSuf|VecSIB128, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM }
|
||||
vgatherdps, 0x6692, AVX2, Modrm|Vex256|Space0F38|VexVVVV|VexW0|SwapSources|NoSuf|VecSIB256, { RegYMM, Dword|Unspecified|BaseIndex, RegYMM }
|
||||
vgatherqp<sd>, 0x6693, AVX2, Modrm|Vex|Space0F38|VexVVVV|<sd:vexw>|SwapSources|NoSuf|VecSIB128, { RegXMM, <sd:elem>|Unspecified|BaseIndex, RegXMM }
|
||||
vgatherqpd, 0x6693, AVX2, Modrm|Vex256|Space0F38|VexVVVV|VexW1|SwapSources|NoSuf|VecSIB256, { RegYMM, Qword|Unspecified|BaseIndex, RegYMM }
|
||||
vgatherqps, 0x6693, AVX2, Modrm|Vex256|Space0F38|VexVVVV|VexW0|SwapSources|NoSuf|VecSIB256, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM }
|
||||
vpgatherdd, 0x6690, AVX2, Modrm|Vex128|Space0F38|VexVVVV|VexW0|SwapSources|NoSuf|VecSIB128, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM }
|
||||
vpgatherdd, 0x6690, AVX2, Modrm|Vex256|Space0F38|VexVVVV|VexW0|SwapSources|NoSuf|VecSIB256, { RegYMM, Dword|Unspecified|BaseIndex, RegYMM }
|
||||
vpgatherdq, 0x6690, AVX2, Modrm|Vex|Space0F38|VexVVVV|VexW1|SwapSources|CheckOperandSize|NoSuf|VecSIB128, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex, RegXMM|RegYMM }
|
||||
vpgatherq<dq>, 0x6691, AVX2, Modrm|Vex128|Space0F38|VexVVVV|<dq:vexw>|SwapSources|NoSuf|VecSIB128, { RegXMM, <dq:elem>|Unspecified|BaseIndex, RegXMM }
|
||||
vpgatherqd, 0x6691, AVX2, Modrm|Vex256|Space0F38|VexVVVV|VexW0|SwapSources|NoSuf|VecSIB256, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM }
|
||||
vpgatherqq, 0x6691, AVX2, Modrm|Vex256|Space0F38|VexVVVV|VexW1|SwapSources|NoSuf|VecSIB256, { RegYMM, Qword|Unspecified|BaseIndex, RegYMM }
|
||||
|
||||
// AES + AVX
|
||||
|
||||
|
|
@ -3321,7 +3321,7 @@ prefetchit1, 0xf18/6, PREFETCHI|x64, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex
|
|||
|
||||
// CMPCCXADD instructions.
|
||||
|
||||
cmp<cc>xadd, 0x66e<cc:opc>, CMPCCXADD|x64, Modrm|Vex|Space0F38|VexVVVV|CheckOperandSize|NoSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
|
||||
cmp<cc>xadd, 0x66e<cc:opc>, CMPCCXADD|x64, Modrm|Vex|Space0F38|VexVVVV|SwapSources|CheckOperandSize|NoSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
|
||||
|
||||
// CMPCCXADD instructions end.
|
||||
|
||||
|
|
|
|||
|
|
@ -35363,7 +35363,7 @@ static const insn_template i386_optab[] =
|
|||
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
1, 1, 1, 0, 0, 0 } } } },
|
||||
{ MN_vgatherdpd, 0x92, 3, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 1, 2, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
|
||||
|
|
@ -35407,7 +35407,7 @@ static const insn_template i386_optab[] =
|
|||
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
1, 1, 0, 0, 0, 0 } } } },
|
||||
{ MN_vgatherdps, 0x92, 3, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
|
||||
|
|
@ -35423,7 +35423,7 @@ static const insn_template i386_optab[] =
|
|||
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
1, 0, 0, 0, 0, 0 } } } },
|
||||
{ MN_vgatherdps, 0x92, 3, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 2, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
|
||||
|
|
@ -35481,7 +35481,7 @@ static const insn_template i386_optab[] =
|
|||
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 1, 0, 0, 0, 0 } } } },
|
||||
{ MN_vgatherqps, 0x93, 3, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
|
||||
|
|
@ -35497,7 +35497,7 @@ static const insn_template i386_optab[] =
|
|||
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
1, 0, 0, 0, 0, 0 } } } },
|
||||
{ MN_vgatherqps, 0x93, 3, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 2, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
|
||||
|
|
@ -35555,7 +35555,7 @@ static const insn_template i386_optab[] =
|
|||
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
1, 0, 0, 0, 0, 0 } } } },
|
||||
{ MN_vgatherqpd, 0x93, 3, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 1, 2, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
|
||||
|
|
@ -35571,7 +35571,7 @@ static const insn_template i386_optab[] =
|
|||
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
1, 0, 0, 0, 0, 0 } } } },
|
||||
{ MN_vgatherqpd, 0x93, 3, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 2, 1, 2, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
|
||||
|
|
@ -35629,7 +35629,7 @@ static const insn_template i386_optab[] =
|
|||
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 1, 0, 0, 0, 0 } } } },
|
||||
{ MN_vpgatherdd, 0x90, 3, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
|
||||
|
|
@ -35645,7 +35645,7 @@ static const insn_template i386_optab[] =
|
|||
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
1, 0, 0, 0, 0, 0 } } } },
|
||||
{ MN_vpgatherdd, 0x90, 3, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 2, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
|
||||
|
|
@ -35703,7 +35703,7 @@ static const insn_template i386_optab[] =
|
|||
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 1, 0, 0, 0, 0 } } } },
|
||||
{ MN_vpgatherdq, 0x90, 3, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 1, 2, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
|
||||
|
|
@ -35747,7 +35747,7 @@ static const insn_template i386_optab[] =
|
|||
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
1, 1, 0, 0, 0, 0 } } } },
|
||||
{ MN_vpgatherqd, 0x91, 3, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
|
||||
|
|
@ -35763,7 +35763,7 @@ static const insn_template i386_optab[] =
|
|||
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
1, 0, 0, 0, 0, 0 } } } },
|
||||
{ MN_vpgatherqd, 0x91, 3, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 2, 1, 1, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
|
||||
|
|
@ -35821,7 +35821,7 @@ static const insn_template i386_optab[] =
|
|||
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
1, 0, 0, 0, 0, 0 } } } },
|
||||
{ MN_vpgatherqq, 0x91, 3, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 1, 2, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
|
||||
|
|
@ -35837,7 +35837,7 @@ static const insn_template i386_optab[] =
|
|||
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
1, 0, 0, 0, 0, 0 } } } },
|
||||
{ MN_vpgatherqq, 0x91, 3, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 2, 1, 2, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
|
||||
|
|
@ -55329,7 +55329,7 @@ static const insn_template i386_optab[] =
|
|||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0 } } } },
|
||||
{ MN_cmpoxadd, 0xe0, 3, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
@ -55345,7 +55345,7 @@ static const insn_template i386_optab[] =
|
|||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
|
||||
0, 0, 0, 0, 1, 0 } } } },
|
||||
{ MN_cmpnoxadd, 0xe1, 3, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
@ -55361,7 +55361,7 @@ static const insn_template i386_optab[] =
|
|||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
|
||||
0, 0, 0, 0, 1, 0 } } } },
|
||||
{ MN_cmpbxadd, 0xe2, 3, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
@ -55377,7 +55377,7 @@ static const insn_template i386_optab[] =
|
|||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
|
||||
0, 0, 0, 0, 1, 0 } } } },
|
||||
{ MN_cmpcxadd, 0xe2, 3, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
@ -55393,7 +55393,7 @@ static const insn_template i386_optab[] =
|
|||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
|
||||
0, 0, 0, 0, 1, 0 } } } },
|
||||
{ MN_cmpnaexadd, 0xe2, 3, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
@ -55409,7 +55409,7 @@ static const insn_template i386_optab[] =
|
|||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
|
||||
0, 0, 0, 0, 1, 0 } } } },
|
||||
{ MN_cmpnbxadd, 0xe3, 3, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
@ -55425,7 +55425,7 @@ static const insn_template i386_optab[] =
|
|||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
|
||||
0, 0, 0, 0, 1, 0 } } } },
|
||||
{ MN_cmpncxadd, 0xe3, 3, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
@ -55441,7 +55441,7 @@ static const insn_template i386_optab[] =
|
|||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
|
||||
0, 0, 0, 0, 1, 0 } } } },
|
||||
{ MN_cmpaexadd, 0xe3, 3, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
@ -55457,7 +55457,7 @@ static const insn_template i386_optab[] =
|
|||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
|
||||
0, 0, 0, 0, 1, 0 } } } },
|
||||
{ MN_cmpexadd, 0xe4, 3, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
@ -55473,7 +55473,7 @@ static const insn_template i386_optab[] =
|
|||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
|
||||
0, 0, 0, 0, 1, 0 } } } },
|
||||
{ MN_cmpzxadd, 0xe4, 3, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
@ -55489,7 +55489,7 @@ static const insn_template i386_optab[] =
|
|||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
|
||||
0, 0, 0, 0, 1, 0 } } } },
|
||||
{ MN_cmpnexadd, 0xe5, 3, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
@ -55505,7 +55505,7 @@ static const insn_template i386_optab[] =
|
|||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
|
||||
0, 0, 0, 0, 1, 0 } } } },
|
||||
{ MN_cmpnzxadd, 0xe5, 3, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
@ -55521,7 +55521,7 @@ static const insn_template i386_optab[] =
|
|||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
|
||||
0, 0, 0, 0, 1, 0 } } } },
|
||||
{ MN_cmpbexadd, 0xe6, 3, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
@ -55537,7 +55537,7 @@ static const insn_template i386_optab[] =
|
|||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
|
||||
0, 0, 0, 0, 1, 0 } } } },
|
||||
{ MN_cmpnaxadd, 0xe6, 3, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
@ -55553,7 +55553,7 @@ static const insn_template i386_optab[] =
|
|||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
|
||||
0, 0, 0, 0, 1, 0 } } } },
|
||||
{ MN_cmpnbexadd, 0xe7, 3, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
@ -55569,7 +55569,7 @@ static const insn_template i386_optab[] =
|
|||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
|
||||
0, 0, 0, 0, 1, 0 } } } },
|
||||
{ MN_cmpaxadd, 0xe7, 3, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
@ -55585,7 +55585,7 @@ static const insn_template i386_optab[] =
|
|||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
|
||||
0, 0, 0, 0, 1, 0 } } } },
|
||||
{ MN_cmpsxadd, 0xe8, 3, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
@ -55601,7 +55601,7 @@ static const insn_template i386_optab[] =
|
|||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
|
||||
0, 0, 0, 0, 1, 0 } } } },
|
||||
{ MN_cmpnsxadd, 0xe9, 3, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
@ -55617,7 +55617,7 @@ static const insn_template i386_optab[] =
|
|||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
|
||||
0, 0, 0, 0, 1, 0 } } } },
|
||||
{ MN_cmppxadd, 0xea, 3, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
@ -55633,7 +55633,7 @@ static const insn_template i386_optab[] =
|
|||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
|
||||
0, 0, 0, 0, 1, 0 } } } },
|
||||
{ MN_cmppexadd, 0xea, 3, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
@ -55649,7 +55649,7 @@ static const insn_template i386_optab[] =
|
|||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
|
||||
0, 0, 0, 0, 1, 0 } } } },
|
||||
{ MN_cmpnpxadd, 0xeb, 3, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
@ -55665,7 +55665,7 @@ static const insn_template i386_optab[] =
|
|||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
|
||||
0, 0, 0, 0, 1, 0 } } } },
|
||||
{ MN_cmppoxadd, 0xeb, 3, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
@ -55681,7 +55681,7 @@ static const insn_template i386_optab[] =
|
|||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
|
||||
0, 0, 0, 0, 1, 0 } } } },
|
||||
{ MN_cmplxadd, 0xec, 3, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
@ -55697,7 +55697,7 @@ static const insn_template i386_optab[] =
|
|||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
|
||||
0, 0, 0, 0, 1, 0 } } } },
|
||||
{ MN_cmpngexadd, 0xec, 3, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
@ -55713,7 +55713,7 @@ static const insn_template i386_optab[] =
|
|||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
|
||||
0, 0, 0, 0, 1, 0 } } } },
|
||||
{ MN_cmpnlxadd, 0xed, 3, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
@ -55729,7 +55729,7 @@ static const insn_template i386_optab[] =
|
|||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
|
||||
0, 0, 0, 0, 1, 0 } } } },
|
||||
{ MN_cmpgexadd, 0xed, 3, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
@ -55745,7 +55745,7 @@ static const insn_template i386_optab[] =
|
|||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
|
||||
0, 0, 0, 0, 1, 0 } } } },
|
||||
{ MN_cmplexadd, 0xee, 3, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
@ -55761,7 +55761,7 @@ static const insn_template i386_optab[] =
|
|||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
|
||||
0, 0, 0, 0, 1, 0 } } } },
|
||||
{ MN_cmpngxadd, 0xee, 3, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
@ -55777,7 +55777,7 @@ static const insn_template i386_optab[] =
|
|||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
|
||||
0, 0, 0, 0, 1, 0 } } } },
|
||||
{ MN_cmpnlexadd, 0xef, 3, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
@ -55793,7 +55793,7 @@ static const insn_template i386_optab[] =
|
|||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0,
|
||||
0, 0, 0, 0, 1, 0 } } } },
|
||||
{ MN_cmpgxadd, 0xef, 3, SPACE_0F38, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 6, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue