Support fxsave64 and fxrstor64.
gas/testsuite/ 2009-12-03 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run x86-64-fxsave and x86-64-fxsave-intel. * gas/i386/rex.d: Updated for fxsave64. * gas/i386/x86-64-fxsave-intel.d: New. * gas/i386/x86-64-fxsave.d: Likewise. * gas/i386/x86-64-fxsave.s: Likewise. opcodes/ 2009-12-03 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (FXSAVE_Fixup): New. (FXSAVE): Likewise. (mod_table): Use FXSAVE on fxsave and fxrstor. * i386-opc.tbl: Add fxsave64 and fxrstor64. * i386-tbl.h: Regenerated.
This commit is contained in:
H.J. Lu
parent
90f5d9d961
commit
eacc9c891d
10 changed files with 208 additions and 6 deletions
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@ -1,3 +1,13 @@
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2009-12-03 H.J. Lu <hongjiu.lu@intel.com>
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* gas/i386/i386.exp: Run x86-64-fxsave and x86-64-fxsave-intel.
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* gas/i386/rex.d: Updated for fxsave64.
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* gas/i386/x86-64-fxsave-intel.d: New.
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* gas/i386/x86-64-fxsave.d: Likewise.
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* gas/i386/x86-64-fxsave.s: Likewise.
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2009-12-02 Nick Clifton <nickc@redhat.com>
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Richard Earnshaw <rearnsha@arm.com>
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@ -304,6 +304,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
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run_dump_test "x86-64-opcode-inval-intel"
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}
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run_dump_test "rexw"
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run_dump_test "x86-64-fxsave"
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run_dump_test "x86-64-fxsave-intel"
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run_dump_test "x86-64-arch-1"
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run_dump_test "x86-64-arch-2"
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run_dump_test "x86-64-xsave"
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@ -7,13 +7,13 @@ Disassembly of section .text:
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0+ <_start>:
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[ ]*[0-9a-f]+:[ ]+40 0f ae 00[ ]+rex fxsave[ ]+\(%rax\)
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[ ]*[0-9a-f]+:[ ]+48 0f ae 00[ ]+rex.W fxsave[ ]+\(%rax\)
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[ ]*[0-9a-f]+:[ ]+48 0f ae 00[ ]+fxsave64[ ]+\(%rax\)
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[ ]*[0-9a-f]+:[ ]+41 0f ae 00[ ]+fxsave[ ]+\(%r8\)
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[ ]*[0-9a-f]+:[ ]+49 0f ae 00[ ]+rex.WB? fxsave[ ]+\(%r8\)
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[ ]*[0-9a-f]+:[ ]+49 0f ae 00[ ]+fxsave64[ ]+\(%r8\)
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[ ]*[0-9a-f]+:[ ]+42 0f ae 04 05 00 00 00 00[ ]+fxsave[ ]+(0x0)?\(,%r8(,1)?\)
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[ ]*[0-9a-f]+:[ ]+4a 0f ae 04 05 00 00 00 00[ ]+rex.WX? fxsave[ ]+(0x0)?\(,%r8(,1)?\)
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[ ]*[0-9a-f]+:[ ]+4a 0f ae 04 05 00 00 00 00[ ]+fxsave64[ ]+(0x0)?\(,%r8(,1)?\)
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[ ]*[0-9a-f]+:[ ]+43 0f ae 04 00[ ]+fxsave[ ]+\(%r8,%r8(,1)?\)
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[ ]*[0-9a-f]+:[ ]+4b 0f ae 04 00[ ]+rex.W(XB)? fxsave[ ]+\(%r8,%r8(,1)?\)
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[ ]*[0-9a-f]+:[ ]+4b 0f ae 04 00[ ]+fxsave64[ ]+\(%r8,%r8(,1)?\)
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[ ]*[0-9a-f]+:[ ]+40 c5 f9 28 00[ ]+rex vmovapd \(%rax\),%xmm0
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[ ]*[0-9a-f]+:[ ]+40[ ]+rex
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[ ]*[0-9a-f]+:[ ]+41[ ]+rex.B
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49
gas/testsuite/gas/i386/x86-64-fxsave-intel.d
Normal file
49
gas/testsuite/gas/i386/x86-64-fxsave-intel.d
Normal file
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@ -0,0 +1,49 @@
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#objdump: -dwMintel
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#name: x86-64 fxsave/fxrstor insns (Intel disassembly)
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#source: x86-64-fxsave.s
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.*: +file format .*
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Disassembly of section .text:
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0+ <foo>:
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[ ]*[a-f0-9]+: 0f ae 00 fxsave \[rax\]
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[ ]*[a-f0-9]+: 41 0f ae 00 fxsave \[r8\]
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[ ]*[a-f0-9]+: 41 0f ae 04 00 fxsave \[r8\+rax\*1\]
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[ ]*[a-f0-9]+: 42 0f ae 04 00 fxsave \[rax\+r8\*1\]
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[ ]*[a-f0-9]+: 43 0f ae 04 38 fxsave \[r8\+r15\*1\]
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[ ]*[a-f0-9]+: 48 0f ae 00 fxsave64 \[rax\]
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[ ]*[a-f0-9]+: 49 0f ae 00 fxsave64 \[r8\]
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[ ]*[a-f0-9]+: 49 0f ae 04 00 fxsave64 \[r8\+rax\*1\]
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[ ]*[a-f0-9]+: 4a 0f ae 04 00 fxsave64 \[rax\+r8\*1\]
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[ ]*[a-f0-9]+: 0f ae 08 fxrstor \[rax\]
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[ ]*[a-f0-9]+: 41 0f ae 08 fxrstor \[r8\]
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[ ]*[a-f0-9]+: 41 0f ae 0c 00 fxrstor \[r8\+rax\*1\]
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[ ]*[a-f0-9]+: 42 0f ae 0c 00 fxrstor \[rax\+r8\*1\]
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[ ]*[a-f0-9]+: 43 0f ae 0c 38 fxrstor \[r8\+r15\*1\]
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[ ]*[a-f0-9]+: 48 0f ae 08 fxrstor64 \[rax\]
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[ ]*[a-f0-9]+: 49 0f ae 08 fxrstor64 \[r8\]
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[ ]*[a-f0-9]+: 49 0f ae 0c 00 fxrstor64 \[r8\+rax\*1\]
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[ ]*[a-f0-9]+: 4a 0f ae 0c 00 fxrstor64 \[rax\+r8\*1\]
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[ ]*[a-f0-9]+: 4b 0f ae 0c 38 fxrstor64 \[r8\+r15\*1\]
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[ ]*[a-f0-9]+: 0f ae 00 fxsave \[rax\]
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[ ]*[a-f0-9]+: 41 0f ae 00 fxsave \[r8\]
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[ ]*[a-f0-9]+: 41 0f ae 04 00 fxsave \[r8\+rax\*1\]
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[ ]*[a-f0-9]+: 42 0f ae 04 00 fxsave \[rax\+r8\*1\]
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[ ]*[a-f0-9]+: 43 0f ae 04 38 fxsave \[r8\+r15\*1\]
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[ ]*[a-f0-9]+: 48 0f ae 00 fxsave64 \[rax\]
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[ ]*[a-f0-9]+: 49 0f ae 00 fxsave64 \[r8\]
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[ ]*[a-f0-9]+: 49 0f ae 04 00 fxsave64 \[r8\+rax\*1\]
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[ ]*[a-f0-9]+: 4a 0f ae 04 00 fxsave64 \[rax\+r8\*1\]
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[ ]*[a-f0-9]+: 0f ae 08 fxrstor \[rax\]
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[ ]*[a-f0-9]+: 41 0f ae 08 fxrstor \[r8\]
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[ ]*[a-f0-9]+: 41 0f ae 0c 00 fxrstor \[r8\+rax\*1\]
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[ ]*[a-f0-9]+: 42 0f ae 0c 00 fxrstor \[rax\+r8\*1\]
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[ ]*[a-f0-9]+: 43 0f ae 0c 38 fxrstor \[r8\+r15\*1\]
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[ ]*[a-f0-9]+: 48 0f ae 08 fxrstor64 \[rax\]
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[ ]*[a-f0-9]+: 49 0f ae 08 fxrstor64 \[r8\]
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[ ]*[a-f0-9]+: 49 0f ae 0c 00 fxrstor64 \[r8\+rax\*1\]
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[ ]*[a-f0-9]+: 4a 0f ae 0c 00 fxrstor64 \[rax\+r8\*1\]
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[ ]*[a-f0-9]+: 4b 0f ae 0c 38 fxrstor64 \[r8\+r15\*1\]
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#pass
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48
gas/testsuite/gas/i386/x86-64-fxsave.d
Normal file
48
gas/testsuite/gas/i386/x86-64-fxsave.d
Normal file
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@ -0,0 +1,48 @@
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#objdump: -dw
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#name: x86-64 fxsave/fxrstor insns
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.*: +file format .*
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Disassembly of section .text:
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0+ <foo>:
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[ ]*[a-f0-9]+: 0f ae 00 fxsave \(%rax\)
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[ ]*[a-f0-9]+: 41 0f ae 00 fxsave \(%r8\)
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[ ]*[a-f0-9]+: 41 0f ae 04 00 fxsave \(%r8,%rax,1\)
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[ ]*[a-f0-9]+: 42 0f ae 04 00 fxsave \(%rax,%r8,1\)
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[ ]*[a-f0-9]+: 43 0f ae 04 38 fxsave \(%r8,%r15,1\)
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[ ]*[a-f0-9]+: 48 0f ae 00 fxsave64 \(%rax\)
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[ ]*[a-f0-9]+: 49 0f ae 00 fxsave64 \(%r8\)
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[ ]*[a-f0-9]+: 49 0f ae 04 00 fxsave64 \(%r8,%rax,1\)
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[ ]*[a-f0-9]+: 4a 0f ae 04 00 fxsave64 \(%rax,%r8,1\)
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[ ]*[a-f0-9]+: 0f ae 08 fxrstor \(%rax\)
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[ ]*[a-f0-9]+: 41 0f ae 08 fxrstor \(%r8\)
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[ ]*[a-f0-9]+: 41 0f ae 0c 00 fxrstor \(%r8,%rax,1\)
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[ ]*[a-f0-9]+: 42 0f ae 0c 00 fxrstor \(%rax,%r8,1\)
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[ ]*[a-f0-9]+: 43 0f ae 0c 38 fxrstor \(%r8,%r15,1\)
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[ ]*[a-f0-9]+: 48 0f ae 08 fxrstor64 \(%rax\)
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[ ]*[a-f0-9]+: 49 0f ae 08 fxrstor64 \(%r8\)
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[ ]*[a-f0-9]+: 49 0f ae 0c 00 fxrstor64 \(%r8,%rax,1\)
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[ ]*[a-f0-9]+: 4a 0f ae 0c 00 fxrstor64 \(%rax,%r8,1\)
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[ ]*[a-f0-9]+: 4b 0f ae 0c 38 fxrstor64 \(%r8,%r15,1\)
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[ ]*[a-f0-9]+: 0f ae 00 fxsave \(%rax\)
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[ ]*[a-f0-9]+: 41 0f ae 00 fxsave \(%r8\)
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[ ]*[a-f0-9]+: 41 0f ae 04 00 fxsave \(%r8,%rax,1\)
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[ ]*[a-f0-9]+: 42 0f ae 04 00 fxsave \(%rax,%r8,1\)
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[ ]*[a-f0-9]+: 43 0f ae 04 38 fxsave \(%r8,%r15,1\)
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[ ]*[a-f0-9]+: 48 0f ae 00 fxsave64 \(%rax\)
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[ ]*[a-f0-9]+: 49 0f ae 00 fxsave64 \(%r8\)
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[ ]*[a-f0-9]+: 49 0f ae 04 00 fxsave64 \(%r8,%rax,1\)
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[ ]*[a-f0-9]+: 4a 0f ae 04 00 fxsave64 \(%rax,%r8,1\)
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[ ]*[a-f0-9]+: 0f ae 08 fxrstor \(%rax\)
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[ ]*[a-f0-9]+: 41 0f ae 08 fxrstor \(%r8\)
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[ ]*[a-f0-9]+: 41 0f ae 0c 00 fxrstor \(%r8,%rax,1\)
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[ ]*[a-f0-9]+: 42 0f ae 0c 00 fxrstor \(%rax,%r8,1\)
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[ ]*[a-f0-9]+: 43 0f ae 0c 38 fxrstor \(%r8,%r15,1\)
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[ ]*[a-f0-9]+: 48 0f ae 08 fxrstor64 \(%rax\)
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[ ]*[a-f0-9]+: 49 0f ae 08 fxrstor64 \(%r8\)
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[ ]*[a-f0-9]+: 49 0f ae 0c 00 fxrstor64 \(%r8,%rax,1\)
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[ ]*[a-f0-9]+: 4a 0f ae 0c 00 fxrstor64 \(%rax,%r8,1\)
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[ ]*[a-f0-9]+: 4b 0f ae 0c 38 fxrstor64 \(%r8,%r15,1\)
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#pass
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44
gas/testsuite/gas/i386/x86-64-fxsave.s
Normal file
44
gas/testsuite/gas/i386/x86-64-fxsave.s
Normal file
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@ -0,0 +1,44 @@
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# Check 64bit fxsave/frstor instructions.
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.text
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foo:
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fxsave (%rax)
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fxsave (%r8)
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fxsave (%r8, %rax)
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fxsave (%rax, %r8)
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fxsave (%r8, %r15)
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fxsave64 (%rax)
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fxsave64 (%r8)
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fxsave64 (%r8, %rax)
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fxsave64 (%rax, %r8)
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fxrstor (%rax)
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fxrstor (%r8)
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fxrstor (%r8, %rax)
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fxrstor (%rax, %r8)
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fxrstor (%r8, %r15)
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fxrstor64 (%rax)
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fxrstor64 (%r8)
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fxrstor64 (%r8, %rax)
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fxrstor64 (%rax, %r8)
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fxrstor64 (%r8, %r15)
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.intel_syntax noprefix
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fxsave [rax]
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fxsave [r8]
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fxsave [r8+rax*1]
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fxsave [rax+r8*1]
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fxsave [r8+r15*1]
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fxsave64 [rax]
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fxsave64 [r8]
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fxsave64 [r8+rax*1]
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fxsave64 [rax+r8*1]
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fxrstor [rax]
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fxrstor [r8]
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fxrstor [r8+rax*1]
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fxrstor [rax+r8*1]
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fxrstor [r8+r15*1]
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fxrstor64 [rax]
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fxrstor64 [r8]
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fxrstor64 [r8+rax*1]
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fxrstor64 [rax+r8*1]
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fxrstor64 [r8+r15*1]
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@ -1,3 +1,12 @@
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2009-12-03 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (FXSAVE_Fixup): New.
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(FXSAVE): Likewise.
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(mod_table): Use FXSAVE on fxsave and fxrstor.
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* i386-opc.tbl: Add fxsave64 and fxrstor64.
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* i386-tbl.h: Regenerated.
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2009-12-02 Nick Clifton <nickc@redhat.com>
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Richard Earnshaw <rearnsha@arm.com>
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@ -110,6 +110,7 @@ static void REP_Fixup (int, int);
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static void CMPXCHG8B_Fixup (int, int);
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static void XMM_Fixup (int, int);
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static void CRC32_Fixup (int, int);
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static void FXSAVE_Fixup (int, int);
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static void OP_LWPCB_E (int, int);
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static void OP_LWP_E (int, int);
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static void OP_LWP_I (int, int);
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@ -358,6 +359,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
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#define OPSUF { OP_3DNowSuffix, 0 }
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#define CMP { CMP_Fixup, 0 }
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#define XMM0 { XMM_Fixup, 0 }
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#define FXSAVE { FXSAVE_Fixup, 0 }
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#define Vex_2src_1 { OP_Vex_2src_1, 0 }
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#define Vex_2src_2 { OP_Vex_2src_2, 0 }
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@ -9541,12 +9543,12 @@ static const struct dis386 mod_table[][2] = {
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},
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{
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/* MOD_0FAE_REG_0 */
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{ "fxsave", { M } },
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{ "fxsave", { FXSAVE } },
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{ "(bad)", { XX } },
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},
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{
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/* MOD_0FAE_REG_1 */
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{ "fxrstor", { M } },
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{ "fxrstor", { FXSAVE } },
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{ "(bad)", { XX } },
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},
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{
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@ -13641,6 +13643,22 @@ skip:
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OP_E (bytemode, sizeflag);
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}
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static void
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FXSAVE_Fixup (int bytemode, int sizeflag)
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{
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/* Add proper suffix to "fxsave" and "fxrstor". */
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USED_REX (REX_W);
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if (rex & REX_W)
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{
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char *p = mnemonicendp;
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*p++ = '6';
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*p++ = '4';
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*p = '\0';
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mnemonicendp = p;
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}
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OP_M (bytemode, sizeflag);
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}
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/* Display the destination register operand for instructions with
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VEX. */
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@ -848,7 +848,9 @@ cmpxchg8b, 1, 0xfc7, 0x1, 2, Cpu586, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ld
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sysenter, 0, 0xf34, None, 2, Cpu686, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
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sysexit, 0, 0xf35, None, 2, Cpu686, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
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fxsave, 1, 0xfae, 0x0, 2, Cpu686, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
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fxsave64, 1, 0xfae, 0x0, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|Rex64, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
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fxrstor, 1, 0xfae, 0x1, 2, Cpu686, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
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fxrstor64, 1, 0xfae, 0x1, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|Rex64, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
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rdpmc, 0, 0xf33, None, 2, Cpu686, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
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// official undefined instr.
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ud2, 0, 0xf0b, None, 2, Cpu686, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
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@ -6902,6 +6902,16 @@ const insn_template i386_optab[] =
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{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 1, 0, 0 } } } },
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{ "fxsave64", 1, 0xfae, 0x0, 2,
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 1, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
|
||||
1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 0, 0 } } } },
|
||||
{ "fxrstor", 1, 0xfae, 0x1, 2,
|
||||
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
@ -6912,6 +6922,16 @@ const insn_template i386_optab[] =
|
|||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 0, 0 } } } },
|
||||
{ "fxrstor64", 1, 0xfae, 0x1, 2,
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 1, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
|
||||
1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 0, 0 } } } },
|
||||
{ "rdpmc", 0, 0xf33, None, 2,
|
||||
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
|
|||
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Reference in a new issue