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include/opcode/

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* sparc.h: Document new format codes '4', '5', and '('.
	(OPF_LOW4, RS3): New macros.
opcodes/
	* sparc-dis.c (v9a_ast_reg_names): Add "cps".
	(X_RS3): New macro.
	(print_insn_sparc): Handle '4', '5', and '(' format codes.
	Accept %asr numbers below 28.
	* sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3
	instructions.
gas/
	* config/tc-sparc.c (v9a_asr_table): Add "cps".
	(sparc_ip): Handle '4', '5' and '(' format codes.
gas/testsuite
	* gas/sparc/hpcvis3.d: New test.
	* gas/sparc/hpcvis3.s: New test source.
	* gas/sparc/sparc.exp: Run new test.
This commit is contained in:
David S. Miller 2011-08-05 16:52:50 +00:00
parent d6c10e950e
commit ea783ef3a0
11 changed files with 324 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

5
gas/ChangeLog
View file

@ -1,3 +1,8 @@
2011-08-05 David S. Miller <davem@davemloft.net>
* config/tc-sparc.c (v9a_asr_table): Add "cps".
(sparc_ip): Handle '4', '5' and '(' format codes.
2011-08-04 H.J. Lu <hongjiu.lu@intel.com> 2011-08-04 H.J. Lu <hongjiu.lu@intel.com>
PR gas/13056 PR gas/13056

18
gas/config/tc-sparc.c
View file

@ -773,6 +773,7 @@ struct priv_reg_entry v9a_asr_table[] =
{"pcr", 16}, {"pcr", 16},
{"gsr", 19}, {"gsr", 19},
{"dcr", 18}, {"dcr", 18},
{"cps", 28},
{"clear_softint", 21}, {"clear_softint", 21},
{"", -1}, /* End marker. */ {"", -1}, /* End marker. */
}; };
@ -2136,6 +2137,9 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
case 'B': case 'B':
case 'R': case 'R':
case '4':
case '5':
case 'g': case 'g':
case 'H': case 'H':
case 'J': case 'J':
@ -2153,6 +2157,7 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
if ((*args == 'v' if ((*args == 'v'
|| *args == 'B' || *args == 'B'
|| *args == '5'
|| *args == 'H') || *args == 'H')
&& (mask & 1)) && (mask & 1))
{ {
@ -2214,6 +2219,11 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
opcode |= RS2 (mask); opcode |= RS2 (mask);
continue; continue;
case '4':
case '5':
opcode |= RS3 (mask);
continue;
case 'g': case 'g':
case 'H': case 'H':
case 'J': case 'J':
@ -2233,6 +2243,14 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
} }
break; break;
case '(':
if (strncmp (s, "%efsr", 5) == 0)
{
s += 5;
continue;
}
break;
case '0': /* 64 bit immediate (set, setsw, setx insn) */ case '0': /* 64 bit immediate (set, setsw, setx insn) */
the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */ the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */
goto immediate; goto immediate;

6
gas/testsuite/ChangeLog
View file

@ -1,3 +1,9 @@
2011-08-05 David S. Miller <davem@davemloft.net>
* gas/sparc/hpcvis3.d: New test.
* gas/sparc/hpcvis3.s: New test source.
* gas/sparc/sparc.exp: Run new test.
2011-08-05 H.J. Lu <hongjiu.lu@intel.com> 2011-08-05 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/x86-64-branch.d: Pass -dw to objdump and support * gas/i386/x86-64-branch.d: Pass -dw to objdump and support

89
gas/testsuite/gas/sparc/hpcvis3.d Normal file
View file

@ -0,0 +1,89 @@
#as: -Av9b
#objdump: -dr
#name: sparc HPC+VIS3
.*: +file format .*sparc.*
Disassembly of section .text:
0+ <.text>:
0: 83 47 00 00 rd %cps, %g1
4: b9 80 a0 03 wr %g2, 3, %cps
8: c7 08 c0 00 ldx \[ %g3 \], %efsr
c: 30 50 00 01 chkpt 0x10
10: bd f0 00 00 commit
14: 87 a0 4a 22 fnadds %f1, %f2, %f3
18: 8d a0 8a 44 fnaddd %f2, %f4, %f6
1c: 8f a0 cb 25 fnmuls %f3, %f5, %f7
20: 95 a1 8b 48 fnmuld %f6, %f8, %f10
24: 97 a1 cc 29 fhadds %f7, %f9, %f11
28: 99 a2 0c 4a fhaddd %f8, %f10, %f12
2c: 9b a2 4c ab fhsubs %f9, %f11, %f13
30: 9d a2 8c cc fhsubd %f10, %f12, %f14
34: 9f a2 ce 2d fnhadds %f11, %f13, %f15
38: a1 a3 0e 4e fnhaddd %f12, %f14, %f16
3c: a1 a3 4f 2f fnsmuld %f13, %f15, %f16
40: ab bb e6 31 fmadds %f15, %f17, %f19, %f21
44: a9 bb a4 50 fmaddd %f14, %f16, %f18, %f20
48: af bc 6a b3 fmsubs %f17, %f19, %f21, %f23
4c: ad bc 28 d2 fmsubd %f16, %f18, %f20, %f22
50: b3 bc ef 35 fnmsubs %f19, %f21, %f23, %f25
54: b1 bc ad 54 fnmsubd %f18, %f20, %f22, %f24
58: b7 bd 73 b7 fnmadds %f21, %f23, %f25, %f27
5c: b5 bd 31 d6 fnmaddd %f20, %f22, %f24, %f26
60: bb fd f6 39 fumadds %f23, %f25, %f27, %f29
64: b9 fd b4 58 fumaddd %f22, %f24, %f26, %f28
68: bf fe 7a bb fumsubs %f25, %f27, %f29, %f31
6c: bd fe 38 da fumsubd %f24, %f26, %f28, %f30
70: 8f f8 4b 23 fnumsubs %f1, %f3, %f5, %f7
74: 91 f8 8d 44 fnumsubd %f2, %f4, %f6, %f8
78: 93 f8 cf a5 fnumadds %f3, %f5, %f7, %f9
7c: 95 f9 11 c6 fnumaddd %f4, %f6, %f8, %f10
80: 8f b1 42 26 addxc %g5, %g6, %g7
84: 97 b2 42 6a addxccc %o1, %o2, %o3
88: 99 b0 02 a0 random %o4
8c: 9f b3 42 ce umulxhi %o5, %sp, %o7
90: b5 b0 02 f9 lzd %i1, %i2
94: 81 b0 03 7b cmask8 %i3
98: 81 b0 03 bc cmask16 %i4
9c: 81 b0 03 fd cmask32 %i5
a0: 8b b0 44 23 fsll16 %f32, %f34, %f36
a4: 8f b0 c4 65 fsrl16 %f34, %f36, %f38
a8: 93 b1 44 a7 fsll32 %f36, %f38, %f40
ac: 97 b1 c4 e9 fsrl32 %f38, %f40, %f42
b0: 9b b2 45 2b fslas16 %f40, %f42, %f44
b4: 9f b2 c5 6d fsra16 %f42, %f44, %f46
b8: a3 b3 45 af fslas32 %f44, %f46, %f48
bc: a7 b3 c5 f1 fsra32 %f46, %f48, %f50
c0: ab b4 47 f3 pdistn %f48, %f50, %f52
c4: af b4 c8 15 fmean16 %f50, %f52, %f54
c8: b3 b5 48 57 fpadd64 %f52, %f54, %f56
cc: b7 b5 c8 99 fchksum16 %f54, %f56, %f58
d0: bb b6 48 db fpsub64 %f56, %f58, %f60
d4: bf b6 cb 1d fpadds16 %f58, %f60, %f62
d8: 8d b0 8b 24 fpadds16s %f2, %f4, %f6
dc: 91 b1 0b 46 fpadds32 %f4, %f6, %f8
e0: 95 b1 8b 68 fpadds32s %f6, %f8, %f10
e4: 99 b2 0b 8a fpsubs16 %f8, %f10, %f12
e8: 9d b2 8b ac fpsubs16s %f10, %f12, %f14
ec: a1 b3 0b ce fpsubs32 %f12, %f14, %f16
f0: a5 b3 8b f0 fpsubs32s %f14, %f16, %f18
f4: 83 b0 22 14 movdtox %f20, %g1
f8: 85 b0 22 35 movstouw %f21, %g2
fc: 87 b0 22 77 movstosw %f23, %g3
100: ad b0 23 04 movxtod %g4, %f22
104: af b0 23 25 movwtos %g5, %f23
108: 97 b2 62 aa xmulx %o1, %o2, %o3
10c: 9d b3 22 cd xmulxhi %o4, %o5, %sp
110: 83 b4 24 12 fucmple8 %f16, %f18, %g1
114: 85 b4 a4 54 fucmpne8 %f18, %f20, %g2
118: 87 b5 25 16 fucmpgt8 %f20, %f22, %g3
11c: 89 b5 a5 58 fucmpeq8 %f22, %f24, %g4
120: 81 b0 6a 23 flcmps %fcc0, %f1, %f3
124: 83 b0 ea 25 flcmps %fcc1, %f3, %f5
128: 85 b1 6a 27 flcmps %fcc2, %f5, %f7
12c: 87 b1 ea 29 flcmps %fcc3, %f7, %f9
130: 81 b3 2a 4e flcmpd %fcc0, %f12, %f14
134: 83 b3 aa 50 flcmpd %fcc1, %f14, %f16
138: 85 b4 2a 52 flcmpd %fcc2, %f16, %f18
13c: 87 b4 aa 54 flcmpd %fcc3, %f18, %f20

82
gas/testsuite/gas/sparc/hpcvis3.s Normal file
View file

@ -0,0 +1,82 @@
# Test HPC/VIS3 instructions
.text
rd %cps, %g1
wr %g2, 0x3, %cps
ldx [%g3], %efsr
chkpt 1f
1: commit
fnadds %f1, %f2, %f3
fnaddd %f2, %f4, %f6
fnmuls %f3, %f5, %f7
fnmuld %f6, %f8, %f10
fhadds %f7, %f9, %f11
fhaddd %f8, %f10, %f12
fhsubs %f9, %f11, %f13
fhsubd %f10, %f12, %f14
fnhadds %f11, %f13, %f15
fnhaddd %f12, %f14, %f16
fnsmuld %f13, %f15, %f16
fmadds %f15, %f17, %f19, %f21
fmaddd %f14, %f16, %f18, %f20
fmsubs %f17, %f19, %f21, %f23
fmsubd %f16, %f18, %f20, %f22
fnmsubs %f19, %f21, %f23, %f25
fnmsubd %f18, %f20, %f22, %f24
fnmadds %f21, %f23, %f25, %f27
fnmaddd %f20, %f22, %f24, %f26
fumadds %f23, %f25, %f27, %f29
fumaddd %f22, %f24, %f26, %f28
fumsubs %f25, %f27, %f29, %f31
fumsubd %f24, %f26, %f28, %f30
fnumsubs %f1, %f3, %f5, %f7
fnumsubd %f2, %f4, %f6, %f8
fnumadds %f3, %f5, %f7, %f9
fnumaddd %f4, %f6, %f8, %f10
addxc %g5, %g6, %g7
addxccc %o1, %o2, %o3
random %o4
umulxhi %o5, %o6, %o7
lzd %i1, %i2
cmask8 %i3
cmask16 %i4
cmask32 %i5
fsll16 %f32, %f34, %f36
fsrl16 %f34, %f36, %f38
fsll32 %f36, %f38, %f40
fsrl32 %f38, %f40, %f42
fslas16 %f40, %f42, %f44
fsra16 %f42, %f44, %f46
fslas32 %f44, %f46, %f48
fsra32 %f46, %f48, %f50
pdistn %f48, %f50, %f52
fmean16 %f50, %f52, %f54
fpadd64 %f52, %f54, %f56
fchksum16 %f54, %f56, %f58
fpsub64 %f56, %f58, %f60
fpadds16 %f58, %f60, %f62
fpadds16s %f2, %f4, %f6
fpadds32 %f4, %f6, %f8
fpadds32s %f6, %f8, %f10
fpsubs16 %f8, %f10, %f12
fpsubs16s %f10, %f12, %f14
fpsubs32 %f12, %f14, %f16
fpsubs32s %f14, %f16, %f18
movdtox %f20, %g1
movstouw %f21, %g2
movstosw %f23, %g3
movxtod %g4, %f22
movwtos %g5, %f23
xmulx %o1, %o2, %o3
xmulxhi %o4, %o5, %o6
fucmple8 %f16, %f18, %g1
fucmpne8 %f18, %f20, %g2
fucmpgt8 %f20, %f22, %g3
fucmpeq8 %f22, %f24, %g4
flcmps %fcc0, %f1, %f3
flcmps %fcc1, %f3, %f5
flcmps %fcc2, %f5, %f7
flcmps %fcc3, %f7, %f9
flcmpd %fcc0, %f12, %f14
flcmpd %fcc1, %f14, %f16
flcmpd %fcc2, %f16, %f18
flcmpd %fcc3, %f18, %f20

1
gas/testsuite/gas/sparc/sparc.exp
View file

@ -56,6 +56,7 @@ if [istarget sparc*-*-*] {
run_dump_test "v9branch4" run_dump_test "v9branch4"
run_dump_test "v9branch5" run_dump_test "v9branch5"
run_dump_test "pc2210" run_dump_test "pc2210"
run_dump_test "hpcvis3"
run_list_test "pr4587" "" run_list_test "pr4587" ""
} }

5
include/opcode/ChangeLog
View file

@ -1,3 +1,8 @@
2011-08-05 David S. Miller <davem@davemloft.net>
* sparc.h: Document new format codes '4', '5', and '('.
(OPF_LOW4, RS3): New macros.
2011-08-03 Maciej W. Rozycki <macro@codesourcery.com> 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
* mips.h: Document the use of FP_D in MIPS16 mode. Adjust the * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the

8
include/opcode/sparc.h
View file

@ -131,6 +131,8 @@ typedef struct sparc_opcode
f frs2 floating point register. f frs2 floating point register.
B frs2 floating point register (double/even). B frs2 floating point register (double/even).
R frs2 floating point register (quad/multiple of 4). R frs2 floating point register (quad/multiple of 4).
4 frs3 floating point register.
5 frs3 floating point register (doube/even).
g frsd floating point register. g frsd floating point register.
H frsd floating point register (double/even). H frsd floating point register (double/even).
J frsd floating point register (quad/multiple of 4). J frsd floating point register (quad/multiple of 4).
@ -187,15 +189,14 @@ typedef struct sparc_opcode
0 32/64 bit immediate for set or setx (v9) insns 0 32/64 bit immediate for set or setx (v9) insns
_ Ancillary state register in rd (v9a) _ Ancillary state register in rd (v9a)
/ Ancillary state register in rs1 (v9a) / Ancillary state register in rs1 (v9a)
( entire floating point state register (%efsr). */
The following chars are unused: (note: ,[] are used as punctuation)
[45]. */
#define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */ #define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */
#define OP3(x) (((x) & 0x3f) << 19) /* Op3 field of format3 insns. */ #define OP3(x) (((x) & 0x3f) << 19) /* Op3 field of format3 insns. */
#define OP(x) ((unsigned) ((x) & 0x3) << 30) /* Op field of all insns. */ #define OP(x) ((unsigned) ((x) & 0x3) << 30) /* Op field of all insns. */
#define OPF(x) (((x) & 0x1ff) << 5) /* Opf field of float insns. */ #define OPF(x) (((x) & 0x1ff) << 5) /* Opf field of float insns. */
#define OPF_LOW5(x) OPF ((x) & 0x1f) /* V9. */ #define OPF_LOW5(x) OPF ((x) & 0x1f) /* V9. */
#define OPF_LOW4(x) OPF ((x) & 0xf) /* V9. */
#define F3F(x, y, z) (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns. */ #define F3F(x, y, z) (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns. */
#define F3I(x) (((x) & 0x1) << 13) /* Immediate field of format 3 insns. */ #define F3I(x) (((x) & 0x1) << 13) /* Immediate field of format 3 insns. */
#define F2(x, y) (OP (x) | OP2(y)) /* Format 2 insns. */ #define F2(x, y) (OP (x) | OP2(y)) /* Format 2 insns. */
@ -207,6 +208,7 @@ typedef struct sparc_opcode
#define SIMM13(x) ((x) & 0x1fff) /* Simm13 field. */ #define SIMM13(x) ((x) & 0x1fff) /* Simm13 field. */
#define RD(x) (((x) & 0x1f) << 25) /* Destination register field. */ #define RD(x) (((x) & 0x1f) << 25) /* Destination register field. */
#define RS1(x) (((x) & 0x1f) << 14) /* Rs1 field. */ #define RS1(x) (((x) & 0x1f) << 14) /* Rs1 field. */
#define RS3(x) (((x) & 0x1f) << 9) /* Rs3 field. */
#define ASI_RS2(x) (SIMM13 (x)) #define ASI_RS2(x) (SIMM13 (x))
#define MEMBAR(x) ((x) & 0x7f) #define MEMBAR(x) ((x) & 0x7f)
#define SLCPOP(x) (((x) & 0x7f) << 6) /* Sparclet cpop. */ #define SLCPOP(x) (((x) & 0x7f) << 6) /* Sparclet cpop. */

9
opcodes/ChangeLog
View file

@ -1,3 +1,12 @@
2011-08-05 David S. Miller <davem@davemloft.net>
* sparc-dis.c (v9a_ast_reg_names): Add "cps".
(X_RS3): New macro.
(print_insn_sparc): Handle '4', '5', and '(' format codes.
Accept %asr numbers below 28.
* sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3
instructions.
2011-08-02 Quentin Neill <quentin.neill@amd.com> 2011-08-02 Quentin Neill <quentin.neill@amd.com>
* i386-dis.c (xop_table): Remove spurious bextr insn. * i386-dis.c (xop_table): Remove spurious bextr insn.

19
opcodes/sparc-dis.c
View file

@ -108,7 +108,8 @@ static char *v9_hpriv_reg_names[] =
static char *v9a_asr_reg_names[] = static char *v9a_asr_reg_names[] =
{ {
"pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint", "pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint",
"softint", "tick_cmpr", "stick", "stick_cmpr" "softint", "tick_cmpr", "stick", "stick_cmpr", "resv26",
"resv27", "cps"
}; };
/* Macros used to extract instruction fields. Not all fields have /* Macros used to extract instruction fields. Not all fields have
@ -119,6 +120,7 @@ static char *v9a_asr_reg_names[] =
#define X_LDST_I(i) (((i) >> 13) & 1) #define X_LDST_I(i) (((i) >> 13) & 1)
#define X_ASI(i) (((i) >> 5) & 0xff) #define X_ASI(i) (((i) >> 5) & 0xff)
#define X_RS2(i) (((i) >> 0) & 0x1f) #define X_RS2(i) (((i) >> 0) & 0x1f)
#define X_RS3(i) (((i) >> 9) & 0x1f)
#define X_IMM(i,n) (((i) >> 0) & ((1 << (n)) - 1)) #define X_IMM(i,n) (((i) >> 0) & ((1 << (n)) - 1))
#define X_SIMM(i,n) SEX (X_IMM ((i), (n)), (n)) #define X_SIMM(i,n) SEX (X_IMM ((i), (n)), (n))
#define X_DISP22(i) (((i) >> 0) & 0x3fffff) #define X_DISP22(i) (((i) >> 0) & 0x3fffff)
@ -634,6 +636,13 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
fregx (X_RS2 (insn)); fregx (X_RS2 (insn));
break; break;
case '4':
freg (X_RS3 (insn));
break;
case '5': /* Double/even. */
fregx (X_RS3 (insn));
break;
case 'g': case 'g':
freg (X_RD (insn)); freg (X_RD (insn));
break; break;
@ -814,7 +823,7 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
break; break;
case '/': case '/':
if (X_RS1 (insn) < 16 || X_RS1 (insn) > 25) if (X_RS1 (insn) < 16 || X_RS1 (insn) > 28)
(*info->fprintf_func) (stream, "%%reserved"); (*info->fprintf_func) (stream, "%%reserved");
else else
(*info->fprintf_func) (stream, "%%%s", (*info->fprintf_func) (stream, "%%%s",
@ -822,7 +831,7 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
break; break;
case '_': case '_':
if (X_RD (insn) < 16 || X_RD (insn) > 25) if (X_RD (insn) < 16 || X_RD (insn) > 28)
(*info->fprintf_func) (stream, "%%reserved"); (*info->fprintf_func) (stream, "%%reserved");
else else
(*info->fprintf_func) (stream, "%%%s", (*info->fprintf_func) (stream, "%%%s",
@ -882,6 +891,10 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
(*info->fprintf_func) (stream, "%%fsr"); (*info->fprintf_func) (stream, "%%fsr");
break; break;
case '(':
(*info->fprintf_func) (stream, "%%efsr");
break;
case 'p': case 'p':
(*info->fprintf_func) (stream, "%%psr"); (*info->fprintf_func) (stream, "%%psr");
break; break;

88
opcodes/sparc-opc.c
View file

@ -298,6 +298,13 @@ const struct sparc_opcode sparc_opcodes[] = {
{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~1), "[i],F", 0, v9 }, { "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~1), "[i],F", 0, v9 },
{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~1),"[1],F", 0, v9 }, /* ld [rs1+0],d */ { "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~1),"[1],F", 0, v9 }, /* ld [rs1+0],d */
{ "ldx", F3(3, 0x21, 0)|RD(3), F3(~3, ~0x21, ~0)|RD(~3), "[1+2],(", 0, v9b },
{ "ldx", F3(3, 0x21, 0)|RD(3), F3(~3, ~0x21, ~0)|RS2_G0|RD(~3),"[1],(", 0, v9b },
{ "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|RD(~3), "[1+i],(", 0, v9b },
{ "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|RD(~3), "[i+1],(", 0, v9b },
{ "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|RS1_G0|RD(~3),"[i],(", 0, v9b },
{ "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~3),"[1],(", 0, v9b },
{ "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", 0, v6 }, { "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", 0, v6 },
{ "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lda [rs1+%g0],d */ { "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lda [rs1+%g0],d */
{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", 0, v9 }, { "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", 0, v9 },
@ -854,6 +861,8 @@ const struct sparc_opcode sparc_opcodes[] = {
{ "wr", F3(2, 0x30, 1)|RD(24), F3(~2, ~0x30, ~1)|RD(~24), "1,i,_", 0, v9b }, /* wr r,i,%sys_tick */ { "wr", F3(2, 0x30, 1)|RD(24), F3(~2, ~0x30, ~1)|RD(~24), "1,i,_", 0, v9b }, /* wr r,i,%sys_tick */
{ "wr", F3(2, 0x30, 0)|RD(25), F3(~2, ~0x30, ~0)|RD(~25)|ASI(~0), "1,2,_", 0, v9b }, /* wr r,r,%sys_tick_cmpr */ { "wr", F3(2, 0x30, 0)|RD(25), F3(~2, ~0x30, ~0)|RD(~25)|ASI(~0), "1,2,_", 0, v9b }, /* wr r,r,%sys_tick_cmpr */
{ "wr", F3(2, 0x30, 1)|RD(25), F3(~2, ~0x30, ~1)|RD(~25), "1,i,_", 0, v9b }, /* wr r,i,%sys_tick_cmpr */ { "wr", F3(2, 0x30, 1)|RD(25), F3(~2, ~0x30, ~1)|RD(~25), "1,i,_", 0, v9b }, /* wr r,i,%sys_tick_cmpr */
{ "wr", F3(2, 0x30, 0)|RD(28), F3(~2, ~0x30, ~0)|RD(~28)|ASI(~0), "1,2,_", 0, v9b }, /* wr r,r,%cps */
{ "wr", F3(2, 0x30, 1)|RD(28), F3(~2, ~0x30, ~1)|RD(~28), "1,i,_", 0, v9b }, /* wr r,i,%cps */
{ "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", 0, v8 }, /* rd %asrX,r */ { "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", 0, v8 }, /* rd %asrX,r */
{ "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", 0, v6 }, /* rd %y,r */ { "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", 0, v6 }, /* rd %y,r */
@ -875,6 +884,7 @@ const struct sparc_opcode sparc_opcodes[] = {
{ "rd", F3(2, 0x28, 0)|RS1(23), F3(~2, ~0x28, ~0)|RS1(~23)|SIMM13(~0), "/,d", 0, v9a }, /* rd %tick_cmpr,r */ { "rd", F3(2, 0x28, 0)|RS1(23), F3(~2, ~0x28, ~0)|RS1(~23)|SIMM13(~0), "/,d", 0, v9a }, /* rd %tick_cmpr,r */
{ "rd", F3(2, 0x28, 0)|RS1(24), F3(~2, ~0x28, ~0)|RS1(~24)|SIMM13(~0), "/,d", 0, v9b }, /* rd %sys_tick,r */ { "rd", F3(2, 0x28, 0)|RS1(24), F3(~2, ~0x28, ~0)|RS1(~24)|SIMM13(~0), "/,d", 0, v9b }, /* rd %sys_tick,r */
{ "rd", F3(2, 0x28, 0)|RS1(25), F3(~2, ~0x28, ~0)|RS1(~25)|SIMM13(~0), "/,d", 0, v9b }, /* rd %sys_tick_cmpr,r */ { "rd", F3(2, 0x28, 0)|RS1(25), F3(~2, ~0x28, ~0)|RS1(~25)|SIMM13(~0), "/,d", 0, v9b }, /* rd %sys_tick_cmpr,r */
{ "rd", F3(2, 0x28, 0)|RS1(28), F3(~2, ~0x28, ~0)|RS1(~28)|SIMM13(~0), "/,d", 0, v9b }, /* rd %cps,r */
{ "rdpr", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|SIMM13(~0), "?,d", 0, v9 }, /* rdpr %priv,r */ { "rdpr", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|SIMM13(~0), "?,d", 0, v9 }, /* rdpr %priv,r */
{ "wrpr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0), "1,2,!", 0, v9 }, /* wrpr r1,r2,%priv */ { "wrpr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0), "1,2,!", 0, v9 }, /* wrpr r1,r2,%priv */
@ -1058,6 +1068,7 @@ const struct sparc_opcode sparc_opcodes[] = {
{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+0,%o7 */ { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+0,%o7 */
{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1,#", F_JSR|F_DELAYED, v6 }, { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1,#", F_JSR|F_DELAYED, v6 },
{ "chkpt", F2(0, 1)|CONDA|ANNUL|(1<<20), F2(~0, ~1)|((~CONDA)&COND(~0)), "G", 0, v9b },
/* Conditional instructions. /* Conditional instructions.
@ -1809,6 +1820,83 @@ SLCBCC("cbnefr", 15),
{ "siam", F3F(2, 0x36, 0x081), F3F(~2, ~0x36, ~0x081)|RD_G0|RS1_G0|RS2(~7), "3", 0, v9b }, { "siam", F3F(2, 0x36, 0x081), F3F(~2, ~0x36, ~0x081)|RD_G0|RS1_G0|RS2(~7), "3", 0, v9b },
{ "commit", F3(2, 0x3e, 0)|RD(30), F3(~2, ~0x3e, ~0)|RD(~30)|RS1_G0|SIMM13(~0), "", 0, v9b },
{ "fnadds", F3F(2, 0x34, 0x051), F3F(~2, ~0x34, ~0x051), "e,f,g", F_FLOAT, v9b },
{ "fnaddd", F3F(2, 0x34, 0x052), F3F(~2, ~0x34, ~0x052), "v,B,H", F_FLOAT, v9b },
{ "fnmuls", F3F(2, 0x34, 0x059), F3F(~2, ~0x34, ~0x059), "e,f,g", F_FLOAT, v9b },
{ "fnmuld", F3F(2, 0x34, 0x05a), F3F(~2, ~0x34, ~0x05a), "v,B,H", F_FLOAT, v9b },
{ "fhadds", F3F(2, 0x34, 0x061), F3F(~2, ~0x34, ~0x061), "e,f,g", F_FLOAT, v9b },
{ "fhaddd", F3F(2, 0x34, 0x062), F3F(~2, ~0x34, ~0x062), "v,B,H", F_FLOAT, v9b },
{ "fhsubs", F3F(2, 0x34, 0x065), F3F(~2, ~0x34, ~0x065), "e,f,g", F_FLOAT, v9b },
{ "fhsubd", F3F(2, 0x34, 0x066), F3F(~2, ~0x34, ~0x066), "v,B,H", F_FLOAT, v9b },
{ "fnhadds", F3F(2, 0x34, 0x071), F3F(~2, ~0x34, ~0x071), "e,f,g", F_FLOAT, v9b },
{ "fnhaddd", F3F(2, 0x34, 0x072), F3F(~2, ~0x34, ~0x072), "v,B,H", F_FLOAT, v9b },
{ "fnsmuld", F3F(2, 0x34, 0x079), F3F(~2, ~0x34, ~0x079), "e,f,H", F_FLOAT, v9b },
{ "fmadds", F3(2, 0x37, 0)|OPF_LOW4(1), F3(~2, ~0x37, 0)|OPF_LOW4(~1), "e,f,4,g", F_FLOAT, v9b },
{ "fmaddd", F3(2, 0x37, 0)|OPF_LOW4(2), F3(~2, ~0x37, 0)|OPF_LOW4(~2), "v,B,5,H", F_FLOAT, v9b },
{ "fmsubs", F3(2, 0x37, 0)|OPF_LOW4(5), F3(~2, ~0x37, 0)|OPF_LOW4(~5), "e,f,4,g", F_FLOAT, v9b },
{ "fmsubd", F3(2, 0x37, 0)|OPF_LOW4(6), F3(~2, ~0x37, 0)|OPF_LOW4(~6), "v,B,5,H", F_FLOAT, v9b },
{ "fnmsubs", F3(2, 0x37, 0)|OPF_LOW4(9), F3(~2, ~0x37, 0)|OPF_LOW4(~9), "e,f,4,g", F_FLOAT, v9b },
{ "fnmsubd", F3(2, 0x37, 0)|OPF_LOW4(10), F3(~2, ~0x37, 0)|OPF_LOW4(~10), "v,B,5,H", F_FLOAT, v9b },
{ "fnmadds", F3(2, 0x37, 0)|OPF_LOW4(13), F3(~2, ~0x37, 0)|OPF_LOW4(~13), "e,f,4,g", F_FLOAT, v9b },
{ "fnmaddd", F3(2, 0x37, 0)|OPF_LOW4(14), F3(~2, ~0x37, 0)|OPF_LOW4(~14), "v,B,5,H", F_FLOAT, v9b },
{ "fumadds", F3(2, 0x3f, 0)|OPF_LOW4(1), F3(~2, ~0x3f, 0)|OPF_LOW4(~1), "e,f,4,g", F_FLOAT, v9b },
{ "fumaddd", F3(2, 0x3f, 0)|OPF_LOW4(2), F3(~2, ~0x3f, 0)|OPF_LOW4(~2), "v,B,5,H", F_FLOAT, v9b },
{ "fumsubs", F3(2, 0x3f, 0)|OPF_LOW4(5), F3(~2, ~0x3f, 0)|OPF_LOW4(~5), "e,f,4,g", F_FLOAT, v9b },
{ "fumsubd", F3(2, 0x3f, 0)|OPF_LOW4(6), F3(~2, ~0x3f, 0)|OPF_LOW4(~6), "v,B,5,H", F_FLOAT, v9b },
{ "fnumsubs", F3(2, 0x3f, 0)|OPF_LOW4(9), F3(~2, ~0x3f, 0)|OPF_LOW4(~9), "e,f,4,g", F_FLOAT, v9b },
{ "fnumsubd", F3(2, 0x3f, 0)|OPF_LOW4(10), F3(~2, ~0x3f, 0)|OPF_LOW4(~10), "v,B,5,H", F_FLOAT, v9b },
{ "fnumadds", F3(2, 0x3f, 0)|OPF_LOW4(13), F3(~2, ~0x3f, 0)|OPF_LOW4(~13), "e,f,4,g", F_FLOAT, v9b },
{ "fnumaddd", F3(2, 0x3f, 0)|OPF_LOW4(14), F3(~2, ~0x3f, 0)|OPF_LOW4(~14), "v,B,5,H", F_FLOAT, v9b },
{ "addxc", F3F(2, 0x36, 0x011), F3F(~2, ~0x36, ~0x011), "1,2,d", 0, v9b },
{ "addxccc", F3F(2, 0x36, 0x013), F3F(~2, ~0x36, ~0x013), "1,2,d", 0, v9b },
{ "random", F3F(2, 0x36, 0x015), F3F(~2, ~0x36, ~0x015), "d", 0, v9b },
{ "umulxhi", F3F(2, 0x36, 0x016), F3F(~2, ~0x36, ~0x016), "1,2,d", 0, v9b },
{ "lzd", F3F(2, 0x36, 0x017), F3F(~2, ~0x36, ~0x017), "2,d", 0, v9b },
{ "cmask8", F3F(2, 0x36, 0x01b), F3F(~2, ~0x36, ~0x01b), "2", 0, v9b },
{ "cmask16", F3F(2, 0x36, 0x01d), F3F(~2, ~0x36, ~0x01d), "2", 0, v9b },
{ "cmask32", F3F(2, 0x36, 0x01f), F3F(~2, ~0x36, ~0x01f), "2", 0, v9b },
{ "fsll16", F3F(2, 0x36, 0x021), F3F(~2, ~0x36, ~0x021), "v,B,H", 0, v9b },
{ "fsrl16", F3F(2, 0x36, 0x023), F3F(~2, ~0x36, ~0x023), "v,B,H", 0, v9b },
{ "fsll32", F3F(2, 0x36, 0x025), F3F(~2, ~0x36, ~0x025), "v,B,H", 0, v9b },
{ "fsrl32", F3F(2, 0x36, 0x027), F3F(~2, ~0x36, ~0x027), "v,B,H", 0, v9b },
{ "fslas16", F3F(2, 0x36, 0x029), F3F(~2, ~0x36, ~0x029), "v,B,H", 0, v9b },
{ "fsra16", F3F(2, 0x36, 0x02b), F3F(~2, ~0x36, ~0x02b), "v,B,H", 0, v9b },
{ "fslas32", F3F(2, 0x36, 0x02d), F3F(~2, ~0x36, ~0x02d), "v,B,H", 0, v9b },
{ "fsra32", F3F(2, 0x36, 0x02f), F3F(~2, ~0x36, ~0x02f), "v,B,H", 0, v9b },
{ "pdistn", F3F(2, 0x36, 0x03f), F3F(~2, ~0x36, ~0x03f), "v,B,H", 0, v9b },
{ "fmean16", F3F(2, 0x36, 0x040), F3F(~2, ~0x36, ~0x040), "v,B,H", 0, v9b },
{ "fpadd64", F3F(2, 0x36, 0x042), F3F(~2, ~0x36, ~0x042), "v,B,H", 0, v9b },
{ "fchksum16", F3F(2, 0x36, 0x044), F3F(~2, ~0x36, ~0x044), "v,B,H", 0, v9b },
{ "fpsub64", F3F(2, 0x36, 0x046), F3F(~2, ~0x36, ~0x046), "v,B,H", 0, v9b },
{ "fpadds16", F3F(2, 0x36, 0x058), F3F(~2, ~0x36, ~0x058), "v,B,H", 0, v9b },
{ "fpadds16s", F3F(2, 0x36, 0x059), F3F(~2, ~0x36, ~0x059), "e,f,g", 0, v9b },
{ "fpadds32", F3F(2, 0x36, 0x05a), F3F(~2, ~0x36, ~0x05a), "v,B,H", 0, v9b },
{ "fpadds32s", F3F(2, 0x36, 0x05b), F3F(~2, ~0x36, ~0x05b), "e,f,g", 0, v9b },
{ "fpsubs16", F3F(2, 0x36, 0x05c), F3F(~2, ~0x36, ~0x05c), "v,B,H", 0, v9b },
{ "fpsubs16s", F3F(2, 0x36, 0x05d), F3F(~2, ~0x36, ~0x05d), "e,f,g", 0, v9b },
{ "fpsubs32", F3F(2, 0x36, 0x05e), F3F(~2, ~0x36, ~0x05e), "v,B,H", 0, v9b },
{ "fpsubs32s", F3F(2, 0x36, 0x05f), F3F(~2, ~0x36, ~0x05f), "e,f,g", 0, v9b },
{ "movdtox", F3F(2, 0x36, 0x110), F3F(~2, ~0x36, ~0x110), "B,d", F_FLOAT, v9b },
{ "movstouw", F3F(2, 0x36, 0x111), F3F(~2, ~0x36, ~0x111), "f,d", F_FLOAT, v9b },
{ "movstosw", F3F(2, 0x36, 0x113), F3F(~2, ~0x36, ~0x113), "f,d", F_FLOAT, v9b },
{ "movxtod", F3F(2, 0x36, 0x118), F3F(~2, ~0x36, ~0x118), "2,H", F_FLOAT, v9b },
{ "movwtos", F3F(2, 0x36, 0x119), F3F(~2, ~0x36, ~0x119), "2,g", F_FLOAT, v9b },
{ "xmulx", F3F(2, 0x36, 0x115), F3F(~2, ~0x36, ~0x115), "1,2,d", 0, v9b },
{ "xmulxhi", F3F(2, 0x36, 0x116), F3F(~2, ~0x36, ~0x116), "1,2,d", 0, v9b },
{ "fucmple8", F3F(2, 0x36, 0x120), F3F(~2, ~0x36, ~0x120), "v,B,d", 0, v9b },
{ "fucmpne8", F3F(2, 0x36, 0x122), F3F(~2, ~0x36, ~0x122), "v,B,d", 0, v9b },
{ "fucmpgt8", F3F(2, 0x36, 0x128), F3F(~2, ~0x36, ~0x128), "v,B,d", 0, v9b },
{ "fucmpeq8", F3F(2, 0x36, 0x12a), F3F(~2, ~0x36, ~0x12a), "v,B,d", 0, v9b },
{ "flcmps", CMPFCC(0)|F3F(2, 0x36, 0x151), CMPFCC(~0)|F3F(~2, ~0x36, ~0x151), "6,e,f", F_FLOAT, v9b },
{ "flcmps", CMPFCC(1)|F3F(2, 0x36, 0x151), CMPFCC(~1)|F3F(~2, ~0x36, ~0x151), "7,e,f", F_FLOAT, v9b },
{ "flcmps", CMPFCC(2)|F3F(2, 0x36, 0x151), CMPFCC(~2)|F3F(~2, ~0x36, ~0x151), "8,e,f", F_FLOAT, v9b },
{ "flcmps", CMPFCC(3)|F3F(2, 0x36, 0x151), CMPFCC(~3)|F3F(~2, ~0x36, ~0x151), "9,e,f", F_FLOAT, v9b },
{ "flcmpd", CMPFCC(0)|F3F(2, 0x36, 0x152), CMPFCC(~0)|F3F(~2, ~0x36, ~0x152), "6,v,B", F_FLOAT, v9b },
{ "flcmpd", CMPFCC(1)|F3F(2, 0x36, 0x152), CMPFCC(~1)|F3F(~2, ~0x36, ~0x152), "7,v,B", F_FLOAT, v9b },
{ "flcmpd", CMPFCC(2)|F3F(2, 0x36, 0x152), CMPFCC(~2)|F3F(~2, ~0x36, ~0x152), "8,v,B", F_FLOAT, v9b },
{ "flcmpd", CMPFCC(3)|F3F(2, 0x36, 0x152), CMPFCC(~3)|F3F(~2, ~0x36, ~0x152), "9,v,B", F_FLOAT, v9b },
/* More v9 specific insns, these need to come last so they do not clash /* More v9 specific insns, these need to come last so they do not clash
with v9a instructions such as "edge8" which looks like impdep1. */ with v9a instructions such as "edge8" which looks like impdep1. */