sim: mcore: drop watchpoint/dumpmem/clearstats support
In preparation for converting to the common memory framework, the custom commands get in our way. But when we realize that gdb support has been dropped for mcore, it makes things a bit easier: the main runner does not let you run arbitrary commands once simulation starts. So lets disable watchpoint support until it can be converted to the common watchpoint logic. There's already an ifdef to let us do that. We straight up drop support for the dumpmem command (no other sim supports this, and if it's a feature people want, we can add a common func) and the clearstats command (not a big deal -- just restart your simulation). We leave in place the verbose check points as a follow up commit will cut that over to common logic.
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2 changed files with 12 additions and 73 deletions
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@ -1,3 +1,9 @@
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2015-04-21 Mike Frysinger <vapier@gentoo.org>
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* interp.c (WATCHFUNCTIONS): Undef it.
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(sim_resume): Move WLhash behind WATCHFUNCTIONS.
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(sim_do_command): Delete.
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2015-04-21 Mike Frysinger <vapier@gentoo.org>
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* Makefile.in (NL_TARGET): Define.
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@ -561,7 +561,8 @@ iu_carry (unsigned long a, unsigned long b, int cin)
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return (x != 0);
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}
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#define WATCHFUNCTIONS 1
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/* TODO: Convert to common watchpoints. */
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#undef WATCHFUNCTIONS
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#ifdef WATCHFUNCTIONS
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#define MAXWL 80
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@ -600,7 +601,9 @@ sim_resume (SIM_DESC sd, int step, int siggnal)
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int insts;
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int w;
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int cycs;
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#ifdef WATCHFUNCTIONS
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word WLhash;
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#endif
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cpu.asregs.exception = step ? SIGTRAP: 0;
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pc = CPU_PC_GET (scpu);
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@ -619,11 +622,13 @@ sim_resume (SIM_DESC sd, int step, int siggnal)
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else
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cpu.asregs.active_gregs = & cpu.asregs.gregs[0];
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#ifdef WATCHFUNCTIONS
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/* make a hash to speed exec loop, hope it's nonzero */
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WLhash = 0xFFFFFFFF;
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for (w = 1; w <= ENDWL; w++)
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WLhash = WLhash & WL[w];
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#endif
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do
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{
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@ -1889,75 +1894,3 @@ sim_create_inferior (SIM_DESC sd, struct bfd *prog_bfd, char **argv, char **env)
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return SIM_RC_OK;
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}
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void
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sim_do_command (SIM_DESC sd, const char *cmd)
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{
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/* Nothing there yet; it's all an error. */
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if (cmd != NULL)
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{
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char ** simargv = buildargv (cmd);
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if (strcmp (simargv[0], "watch") == 0)
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{
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if ((simargv[1] == NULL) || (simargv[2] == NULL))
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{
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fprintf (stderr, "Error: missing argument to watch cmd.\n");
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freeargv (simargv);
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return;
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}
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ENDWL++;
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WL[ENDWL] = strtol (simargv[2], NULL, 0);
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WLstr[ENDWL] = strdup (simargv[1]);
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fprintf (stderr, "Added %s (%x) to watchlist, #%d\n",WLstr[ENDWL],
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WL[ENDWL], ENDWL);
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}
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else if (strcmp (simargv[0], "dumpmem") == 0)
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{
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unsigned char * p;
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FILE * dumpfile;
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if (simargv[1] == NULL)
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fprintf (stderr, "Error: missing argument to dumpmem cmd.\n");
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fprintf (stderr, "Writing dumpfile %s...",simargv[1]);
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dumpfile = fopen (simargv[1], "w");
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p = cpu.mem;
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fwrite (p, cpu.asregs.msize-1, 1, dumpfile);
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fclose (dumpfile);
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fprintf (stderr, "done.\n");
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}
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else if (strcmp (simargv[0], "clearstats") == 0)
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{
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cpu.asregs.cycles = 0;
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cpu.asregs.insts = 0;
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cpu.asregs.stalls = 0;
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ENDWL = 0;
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}
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else if (strcmp (simargv[0], "verbose") == 0)
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{
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issue_messages = 2;
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}
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else
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{
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fprintf (stderr,"Error: \"%s\" is not a valid M.CORE simulator command.\n",
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cmd);
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}
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freeargv (simargv);
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}
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else
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{
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fprintf (stderr, "M.CORE sim commands: \n");
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fprintf (stderr, " watch <funcname> <addr>\n");
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fprintf (stderr, " dumpmem <filename>\n");
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fprintf (stderr, " clearstats\n");
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fprintf (stderr, " verbose\n");
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}
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}
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