FreeChainXenon/binutils-gdb
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Fix disassembly of RX zero-offset register indirect instructions.

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opcode	* rx.h (enum RX_Operand_Type): Add RX_Operand_Zero_Indirect.

opcodes	* rx-decode.opc (rx_disp): If the displacement is zero, set the
	type to RX_Operand_Zero_Indirect.
	* rx-decode.c: Regenerate.
	* rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.

gas	* config/rx-parse.y: Allow zero value for 5-bit displacements.

tests	* gas/rx/mov.sm: Add tests for zero offset indirect moves.
	* gas/rx/mov.d: Update expected output.
This commit is contained in:
Nick Clifton 2015-11-02 14:14:22 +00:00
parent a62e598977
commit e292aa7a95
11 changed files with 560 additions and 480 deletions
Download patch file Download diff file Expand all files Collapse all files

10
opcodes/rx-dis.c
View file

@ -168,7 +168,7 @@ print_insn_rx (bfd_vma addr, disassemble_info * dis)
oper = opcode.op + *s - '0';
if (do_size)
{
if (oper->type == RX_Operand_Indirect)
if (oper->type == RX_Operand_Indirect || oper->type == RX_Operand_Zero_Indirect)
PR (PS, "%s", size_names[oper->size]);
}
else
@ -189,10 +189,10 @@ print_insn_rx (bfd_vma addr, disassemble_info * dis)
PR (PS, "%s", register_names[oper->reg]);
break;
case RX_Operand_Indirect:
if (oper->addend)
PR (PS, "%d[%s]", oper->addend, register_names[oper->reg]);
else
PR (PS, "[%s]", register_names[oper->reg]);
PR (PS, "%d[%s]", oper->addend, register_names[oper->reg]);
break;
case RX_Operand_Zero_Indirect:
PR (PS, "[%s]", register_names[oper->reg]);
break;
case RX_Operand_Postinc:
PR (PS, "[%s+]", register_names[oper->reg]);