Add PDP-11 support

bfd/ChangeLog

@@ -1,3 +1,24 @@
+2001-02-18  lars brinkhoff  <lars@nocrew.org>
+
+	* Makefile.am: Add PDP-11 a.out target.
+	* config.bfd: Likewise.
+	* configure.in: Likewise.
+	* targets.c: Likewise.
+	* archures.c: Likewise.
+	* bfd-in2.h: Likewise.  Add PDP-11 relocations.
+	* libbfd.h: Add PDP-11 relocations.
+	* reloc.c: Likewise.
+	* cpu-pdp11.c: New file.
+	* pdp11.c: New file.
+
+	* libaout.h (GET_WORD) [ARCH_SIZE==16]: Define.
+	(GET_SWORD) [ARCH_SIZE==16]: Likewise.
+	(GET_SWORD) [ARCH_SIZE==16]: Likewise.
+	(PUT_WORD) [ARCH_SIZE==16]: Likewise.
+	(GET_MAGIC): New macro.
+	(PUT_MAGIC): Likewise.
+	* aout-target.h (MY(object_p)): Use GET_MAGIC to read magic word.
+
 2001-02-18  Jim Kingdon  <jkingdon@engr.sgi.com>
 
 	* irix-core.c (irix_core_core_file_p): Set the architecture (GDB

bfd/Makefile.am

@@ -69,6 +69,7 @@ ALL_MACHINES = \
 	cpu-mcore.lo \
 	cpu-mips.lo \
 	cpu-ns32k.lo \
+	cpu-pdp11.lo \
 	cpu-pj.lo \
 	cpu-powerpc.lo \
 	cpu-rs6000.lo \
@@ -112,6 +113,7 @@ ALL_MACHINES_CFILES = \
 	cpu-mcore.c \
 	cpu-mips.c \
 	cpu-ns32k.c \
+	cpu-pdp11.c \
 	cpu-pj.c \
 	cpu-powerpc.c \
 	cpu-rs6000.c \
@@ -239,6 +241,7 @@ BFD32_BACKENDS = \
 	ns32knetbsd.lo \
 	oasys.lo \
 	pc532-mach.lo \
+	pdp11.lo \
 	pe-arm.lo \
 	pei-arm.lo \
 	pe-i386.lo \
@@ -377,6 +380,7 @@ BFD32_BACKENDS_CFILES = \
 	ns32knetbsd.c \
 	oasys.c \
 	pc532-mach.c \
+	pdp11.c \
 	pe-arm.c \
 	pei-arm.c \
 	pe-i386.c \
@@ -781,6 +785,7 @@ cpu-m10300.lo: cpu-m10300.c $(INCDIR)/filenames.h
 cpu-mcore.lo: cpu-mcore.c $(INCDIR)/filenames.h
 cpu-mips.lo: cpu-mips.c $(INCDIR)/filenames.h
 cpu-ns32k.lo: cpu-ns32k.c $(INCDIR)/filenames.h ns32k.h
+cpu-pdp11.lo: cpu-pdp11.c $(INCDIR)/filenames.h
 cpu-pj.lo: cpu-pj.c $(INCDIR)/filenames.h
 cpu-powerpc.lo: cpu-powerpc.c $(INCDIR)/filenames.h
 cpu-rs6000.lo: cpu-rs6000.c $(INCDIR)/filenames.h
@@ -1161,6 +1166,9 @@ oasys.lo: oasys.c $(INCDIR)/filenames.h $(INCDIR)/oasys.h \
 pc532-mach.lo: pc532-mach.c $(INCDIR)/filenames.h libaout.h \
   $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h aout-target.h \
   $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def $(INCDIR)/aout/ar.h
+pdp11.lo: pdp11.c libaout.h $(INCDIR)/bfdlink.h \
+  aout-target.h $(INCDIR)/aout/aout64.h $(INCDIR)/aout/stab_gnu.h \
+  $(INCDIR)/aout/stab.def $(INCDIR)/aout/ar.h
 pe-arm.lo: pe-arm.c $(INCDIR)/filenames.h coff-arm.c \
   $(INCDIR)/coff/arm.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/pe.h \
   libcoff.h $(INCDIR)/bfdlink.h coffcode.h peicode.h \

bfd/Makefile.in

@@ -190,6 +190,7 @@ ALL_MACHINES = \
 	cpu-mcore.lo \
 	cpu-mips.lo \
 	cpu-ns32k.lo \
+	cpu-pdp11.lo \
 	cpu-pj.lo \
 	cpu-powerpc.lo \
 	cpu-rs6000.lo \
@@ -234,6 +235,7 @@ ALL_MACHINES_CFILES = \
 	cpu-mcore.c \
 	cpu-mips.c \
 	cpu-ns32k.c \
+	cpu-pdp11.c \
 	cpu-pj.c \
 	cpu-powerpc.c \
 	cpu-rs6000.c \
@@ -362,6 +364,7 @@ BFD32_BACKENDS = \
 	ns32knetbsd.lo \
 	oasys.lo \
 	pc532-mach.lo \
+	pdp11.lo \
 	pe-arm.lo \
 	pei-arm.lo \
 	pe-i386.lo \
@@ -501,6 +504,7 @@ BFD32_BACKENDS_CFILES = \
 	ns32knetbsd.c \
 	oasys.c \
 	pc532-mach.c \
+	pdp11.c \
 	pe-arm.c \
 	pei-arm.c \
 	pe-i386.c \
@@ -1320,6 +1324,7 @@ cpu-m10300.lo: cpu-m10300.c $(INCDIR)/filenames.h
 cpu-mcore.lo: cpu-mcore.c $(INCDIR)/filenames.h
 cpu-mips.lo: cpu-mips.c $(INCDIR)/filenames.h
 cpu-ns32k.lo: cpu-ns32k.c $(INCDIR)/filenames.h ns32k.h
+cpu-pdp11.lo: cpu-pdp11.c $(INCDIR)/filenames.h
 cpu-pj.lo: cpu-pj.c $(INCDIR)/filenames.h
 cpu-powerpc.lo: cpu-powerpc.c $(INCDIR)/filenames.h
 cpu-rs6000.lo: cpu-rs6000.c $(INCDIR)/filenames.h
@@ -1700,6 +1705,9 @@ oasys.lo: oasys.c $(INCDIR)/filenames.h $(INCDIR)/oasys.h \
 pc532-mach.lo: pc532-mach.c $(INCDIR)/filenames.h libaout.h \
   $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h aout-target.h \
   $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def $(INCDIR)/aout/ar.h
+pdp11.lo: pdp11.c libaout.h $(INCDIR)/bfdlink.h \
+  aout-target.h $(INCDIR)/aout/aout64.h $(INCDIR)/aout/stab_gnu.h \
+  $(INCDIR)/aout/stab.def $(INCDIR)/aout/ar.h
 pe-arm.lo: pe-arm.c $(INCDIR)/filenames.h coff-arm.c \
   $(INCDIR)/coff/arm.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/pe.h \
   libcoff.h $(INCDIR)/bfdlink.h coffcode.h peicode.h \

bfd/aout-target.h

@@ -156,7 +156,7 @@ MY(object_p) (abfd)
 #ifdef SWAP_MAGIC
   exec.a_info = SWAP_MAGIC (exec_bytes.e_info);
 #else
-  exec.a_info = bfd_h_get_32 (abfd, exec_bytes.e_info);
+  exec.a_info = GET_MAGIC (abfd, exec_bytes.e_info);
 #endif /* SWAP_MAGIC */
 
   if (N_BADMAG (exec)) return 0;

bfd/archures.c

@@ -155,6 +155,7 @@ DESCRIPTION
 .#define bfd_mach_h8300   1
 .#define bfd_mach_h8300h  2
 .#define bfd_mach_h8300s  3
+.  bfd_arch_pdp11,     {* DEC PDP-11 *}
 .  bfd_arch_powerpc,   {* PowerPC *}
 .#define bfd_mach_ppc		0
 .#define bfd_mach_ppc_403	403
@@ -308,6 +309,7 @@ extern const bfd_arch_info_type bfd_m88k_arch;
 extern const bfd_arch_info_type bfd_mips_arch;
 extern const bfd_arch_info_type bfd_mn10200_arch;
 extern const bfd_arch_info_type bfd_mn10300_arch;
+extern const bfd_arch_info_type bfd_pdp11_arch;
 extern const bfd_arch_info_type bfd_powerpc_arch;
 extern const bfd_arch_info_type bfd_rs6000_arch;
 extern const bfd_arch_info_type bfd_pj_arch;
@@ -354,6 +356,7 @@ static const bfd_arch_info_type * const bfd_archures_list[] = {
   &bfd_mips_arch,
   &bfd_mn10200_arch,
   &bfd_mn10300_arch,
+  &bfd_pdp11_arch,
   &bfd_powerpc_arch,
   &bfd_rs6000_arch,
   &bfd_sh_arch,

bfd/bfd-in2.h

@@ -1424,6 +1424,7 @@ enum bfd_architecture
 #define bfd_mach_h8300   1
 #define bfd_mach_h8300h  2
 #define bfd_mach_h8300s  3
+  bfd_arch_pdp11,     /* DEC PDP-11 */
   bfd_arch_powerpc,   /* PowerPC */
 #define bfd_mach_ppc           0
 #define bfd_mach_ppc_403       403
@@ -2088,6 +2089,10 @@ to compensate for the borrow when the low bits are added. */
   BFD_RELOC_NS32K_DISP_16_PCREL,
   BFD_RELOC_NS32K_DISP_32_PCREL,
 
+/* PDP11 relocations */
+  BFD_RELOC_PDP11_DISP_8_PCREL,
+  BFD_RELOC_PDP11_DISP_6_PCREL,
+
 /* Picojava relocs.  Not all of these appear in object files. */
   BFD_RELOC_PJ_CODE_HI16,
   BFD_RELOC_PJ_CODE_LO16,

bfd/config.bfd

@@ -44,6 +44,7 @@ m6812*|m68hc12*) targ_archs="bfd_m68hc12_arch bfd_m68hc11_arch" ;;
 m68*)	targ_archs=bfd_m68k_arch ;;
 m88*)	targ_archs=bfd_m88k_arch ;;
 mips*)	targ_archs=bfd_mips_arch ;;
+pdp11*)	targ_archs=bfd_pdp11_arch ;;
 pj*)	targ_archs="bfd_pj_arch bfd_i386_arch";;
 powerpc*) targ_archs="bfd_rs6000_arch bfd_powerpc_arch" ;;
 s390*)  targ_archs=bfd_s390_arch ;;
@@ -680,6 +681,11 @@ case "${targ}" in
     targ_underscore=yes
     ;;
 
+  pdp11-*-*)
+    targ_defvec=pdp11_aout_vec
+    targ_underscore=yes
+    ;;
+
   pj-*-*)
     targ_defvec=bfd_elf32_pj_vec
     targ_selvecs="bfd_elf32_pj_vec bfd_elf32_pjl_vec"

bfd/configure

@@ -6061,6 +6061,7 @@ do
     nlm32_powerpc_vec)		tb="$tb nlm32-ppc.lo nlm32.lo nlm.lo" ;;
     pc532netbsd_vec)		tb="$tb ns32knetbsd.lo aout-ns32k.lo" ;;
     pc532machaout_vec)		tb="$tb pc532-mach.lo aout-ns32k.lo" ;;
+    pdp11_aout_vec)		tb="$tb pdp11.lo" ;;
     pmac_xcoff_vec)		tb="$tb coff-pmac.lo xcofflink.lo" ;;
     rs6000coff_vec)		tb="$tb coff-rs6000.lo xcofflink.lo" ;;
     bfd_powerpc_pe_vec)         tb="$tb pe-ppc.lo peigen.lo cofflink.lo" ;;  
@@ -6182,17 +6183,17 @@ for ac_hdr in unistd.h
 do
 ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
 echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
-echo "configure:6186: checking for $ac_hdr" >&5
+echo "configure:6187: checking for $ac_hdr" >&5
 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 6191 "configure"
+#line 6192 "configure"
 #include "confdefs.h"
 #include <$ac_hdr>
 EOF
 ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
-{ (eval echo configure:6196: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+{ (eval echo configure:6197: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
 ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
 if test -z "$ac_err"; then
   rm -rf conftest*
@@ -6221,12 +6222,12 @@ done
 for ac_func in getpagesize
 do
 echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
-echo "configure:6225: checking for $ac_func" >&5
+echo "configure:6226: checking for $ac_func" >&5
 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 6230 "configure"
+#line 6231 "configure"
 #include "confdefs.h"
 /* System header to define __stub macros and hopefully few prototypes,
     which can conflict with char $ac_func(); below.  */
@@ -6249,7 +6250,7 @@ $ac_func();
 
 ; return 0; }
 EOF
-if { (eval echo configure:6253: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:6254: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
   rm -rf conftest*
   eval "ac_cv_func_$ac_func=yes"
 else
@@ -6274,7 +6275,7 @@ fi
 done
 
 echo $ac_n "checking for working mmap""... $ac_c" 1>&6
-echo "configure:6278: checking for working mmap" >&5
+echo "configure:6279: checking for working mmap" >&5
 if eval "test \"`echo '$''{'ac_cv_func_mmap_fixed_mapped'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
@@ -6282,7 +6283,7 @@ else
   ac_cv_func_mmap_fixed_mapped=no
 else
   cat > conftest.$ac_ext <<EOF
-#line 6286 "configure"
+#line 6287 "configure"
 #include "confdefs.h"
 
 /* Thanks to Mike Haertel and Jim Avera for this test.
@@ -6422,7 +6423,7 @@ main()
 }
 
 EOF
-if { (eval echo configure:6426: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
+if { (eval echo configure:6427: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
 then
   ac_cv_func_mmap_fixed_mapped=yes
 else
@@ -6447,12 +6448,12 @@ fi
 for ac_func in madvise mprotect
 do
 echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
-echo "configure:6451: checking for $ac_func" >&5
+echo "configure:6452: checking for $ac_func" >&5
 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
   echo $ac_n "(cached) $ac_c" 1>&6
 else
   cat > conftest.$ac_ext <<EOF
-#line 6456 "configure"
+#line 6457 "configure"
 #include "confdefs.h"
 /* System header to define __stub macros and hopefully few prototypes,
     which can conflict with char $ac_func(); below.  */
@@ -6475,7 +6476,7 @@ $ac_func();
 
 ; return 0; }
 EOF
-if { (eval echo configure:6479: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+if { (eval echo configure:6480: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
   rm -rf conftest*
   eval "ac_cv_func_$ac_func=yes"
 else

bfd/configure.in

@@ -610,6 +610,7 @@ do
     nlm32_powerpc_vec)		tb="$tb nlm32-ppc.lo nlm32.lo nlm.lo" ;;
     pc532netbsd_vec)		tb="$tb ns32knetbsd.lo aout-ns32k.lo" ;;
     pc532machaout_vec)		tb="$tb pc532-mach.lo aout-ns32k.lo" ;;
+    pdp11_aout_vec)		tb="$tb pdp11.lo" ;;
     pmac_xcoff_vec)		tb="$tb coff-pmac.lo xcofflink.lo" ;;
     rs6000coff_vec)		tb="$tb coff-rs6000.lo xcofflink.lo" ;;
     bfd_powerpc_pe_vec)         tb="$tb pe-ppc.lo peigen.lo cofflink.lo" ;;  

bfd/cpu-pdp11.c

@@ -0,0 +1,39 @@
+/* BFD back-end for PDP-11 support.
+   Copyright (C) 2001 Free Software Foundation, Inc.
+
+This file is part of BFD, the Binary File Descriptor library.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#include "bfd.h"
+#include "sysdep.h"
+#include "libbfd.h"
+
+const bfd_arch_info_type bfd_pdp11_arch =
+  {
+    16,	/* 16 bits in a word */
+    16,	/* 16 bits in an address */
+    8,	/* 8 bits in a byte */
+    bfd_arch_pdp11,
+    0,	/* only 1 machine */
+    "pdp11",
+    "pdp11",
+    1,		/* aligment = 16 bit */
+    true, /* the one and only */
+    bfd_default_compatible, 
+    bfd_default_scan ,
+    0,
+  };
+

bfd/libaout.h

@@ -33,22 +33,39 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 #if ARCH_SIZE==64
 #define GET_WORD bfd_h_get_64
 #define GET_SWORD bfd_h_get_signed_64
+#define GET_MAGIC bfd_h_get_32
 #define PUT_WORD bfd_h_put_64
+#define PUT_MAGIC bfd_h_put_32
 #ifndef NAME
 #define NAME(x,y) CAT3(x,_64_,y)
 #endif
 #define JNAME(x) CAT(x,_64)
 #define BYTES_IN_WORD 8
+#else
+#if ARCH_SIZE==16
+#define GET_WORD bfd_h_get_16
+#define GET_SWORD bfd_h_get_signed_16
+#define GET_MAGIC bfd_h_get_16
+#define PUT_WORD bfd_h_put_16
+#define PUT_MAGIC bfd_h_put_16
+#ifndef NAME
+#define NAME(x,y) CAT3(x,_16_,y)
+#endif
+#define JNAME(x) CAT(x,_16)
+#define BYTES_IN_WORD 2
 #else /* ARCH_SIZE == 32 */
 #define GET_WORD bfd_h_get_32
 #define GET_SWORD bfd_h_get_signed_32
+#define GET_MAGIC bfd_h_get_32
 #define PUT_WORD bfd_h_put_32
+#define PUT_MAGIC bfd_h_put_32
 #ifndef NAME
 #define NAME(x,y) CAT3(x,_32_,y)
 #endif
 #define JNAME(x) CAT(x,_32)
 #define BYTES_IN_WORD 4
 #endif /* ARCH_SIZE==32 */
+#endif /* ARCH_SIZE==64 */
 
 /* Declare at file level, since used in parameter lists, which have
    weird scope.  */
@@ -567,6 +584,8 @@ NAME(aout,bfd_free_cached_info) PARAMS ((bfd *));
 
 /* A.out uses the generic versions of these routines... */
 
+#define	aout_16_get_section_contents	_bfd_generic_get_section_contents
+
 #define	aout_32_get_section_contents	_bfd_generic_get_section_contents
 
 #define	aout_64_get_section_contents	_bfd_generic_get_section_contents

bfd/libbfd.h

@@ -735,6 +735,8 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
   "BFD_RELOC_NS32K_DISP_8_PCREL",
   "BFD_RELOC_NS32K_DISP_16_PCREL",
   "BFD_RELOC_NS32K_DISP_32_PCREL",
+  "BFD_RELOC_PDP11_DISP_8_PCREL",
+  "BFD_RELOC_PDP11_DISP_6_PCREL",
   "BFD_RELOC_PJ_CODE_HI16",
   "BFD_RELOC_PJ_CODE_LO16",
   "BFD_RELOC_PJ_CODE_DIR16",

bfd/po/POTFILES.in

@@ -82,6 +82,7 @@ cpu-m88k.c
 cpu-mcore.c
 cpu-mips.c
 cpu-ns32k.c
+cpu-pdp11.c
 cpu-pj.c
 cpu-powerpc.c
 cpu-rs6000.c
@@ -213,6 +214,7 @@ oasys.c
 opncls.c
 osf-core.c
 pc532-mach.c
+pdp11.c
 pe-arm.c
 pe-i386.c
 pei-arm.c

bfd/po/bfd.pot

@@ -6,7 +6,7 @@
 msgid ""
 msgstr ""
 "Project-Id-Version: PACKAGE VERSION\n"
-"POT-Creation-Date: 2001-02-18 14:28-0800\n"
+"POT-Creation-Date: 2001-02-18 15:14-0800\n"
 "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
 "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
 "Language-Team: LANGUAGE <LL@li.org>\n"
@@ -1337,6 +1337,11 @@ msgstr ""
 msgid "%s: could not find output section %s for input section %s"
 msgstr ""
 
+#: elflink.h:5559
+#, c-format
+msgid "%s: invalid section symbol index 0x%x (%s) ingored"
+msgstr ""
+
 #: i386linux.c:450 m68klinux.c:454 sparclinux.c:452
 #, c-format
 msgid "Output file requires shared library `%s'\n"
@@ -1614,29 +1619,29 @@ msgstr ""
 msgid "Object module NOT error-free !\n"
 msgstr ""
 
-#: vms-misc.c:540
+#: vms-misc.c:536
 #, c-format
 msgid "Stack overflow (%d) in _bfd_vms_push"
 msgstr ""
 
-#: vms-misc.c:558
+#: vms-misc.c:554
 msgid "Stack underflow in _bfd_vms_pop"
 msgstr ""
 
-#: vms-misc.c:916
+#: vms-misc.c:910
 msgid "_bfd_vms_output_counted called with zero bytes"
 msgstr ""
 
-#: vms-misc.c:921
+#: vms-misc.c:915
 msgid "_bfd_vms_output_counted called with too many bytes"
 msgstr ""
 
-#: vms-misc.c:1052
+#: vms-misc.c:1046
 #, c-format
 msgid "Symbol %s replaced by %s\n"
 msgstr ""
 
-#: vms-misc.c:1114
+#: vms-misc.c:1108
 #, c-format
 msgid "failed to enter %s"
 msgstr ""

bfd/reloc.c

@@ -2107,6 +2107,13 @@ ENUMX
 ENUMDOC
   ns32k relocations
 
+ENUM
+  BFD_RELOC_PDP11_DISP_8_PCREL
+ENUMX
+  BFD_RELOC_PDP11_DISP_6_PCREL
+ENUMDOC
+  PDP11 relocations
+
 ENUM
   BFD_RELOC_PJ_CODE_HI16
 ENUMX

bfd/targets.c

@@ -624,6 +624,7 @@ extern const bfd_target nlm32_sparc_vec;
 extern const bfd_target oasys_vec;
 extern const bfd_target pc532machaout_vec;
 extern const bfd_target pc532netbsd_vec;
+extern const bfd_target pdp11_aout_vec;
 extern const bfd_target pmac_xcoff_vec;
 extern const bfd_target ppcboot_vec;
 extern const bfd_target riscix_vec;
@@ -884,6 +885,7 @@ static const bfd_target * const _bfd_target_vector[] = {
 	&oasys_vec,
 #endif
 	&pc532machaout_vec,
+	&pdp11_aout_vec,
 #if 0
 	/* We have no way of distinguishing these from other a.out variants */
 	&aout_arm_big_vec,

binutils/NEWS

@@ -1,5 +1,7 @@
 -*- text -*-
 
+* Support for PDP-11 by Lars Brinkhoff.
+
 * Add support for ARM v5t and v5te architectures and Intel's XScale ARM
   extenstions.
 

binutils/testsuite/binutils-all/readelf.wi

@@ -1,6 +1,6 @@
 The section .debug_info contains:
 
-  Compilation Unit:
+  Compilation Unit @ .*:
    Length:        .*
    Version:       2
    Abbrev Offset: 0

gas/ChangeLog

@@ -1,3 +1,14 @@
+2001-02-18  lars brinkhoff  <lars@nocrew.org>
+
+	* Makefile.am: Add PDP-11 target.
+	* configure.in: Likewise.
+	* config/tc-pdp11.c: New file.
+	* config/tc-pdp11.h: New file.
+	* doc/Makefile.am: Add PDP-11 documentation.
+	* doc/all.texi: Likewise.
+	* doc/as.texinfo: Likewise.
+	* doc/c-pdp11.texi: New file.
+
 2001-02-16  matthew green  <mrg@redhat.com>
 
  	* gas/cgen.c (gas_cgen_md_apply_fix3): Support BFD_RELOC_64.

gas/Makefile.am

@@ -63,6 +63,7 @@ CPU_TYPES = \
 	mn10200 \
 	mn10300 \
 	ns32k \
+	pdp11 \
 	pj \
 	ppc \
 	s390 \
@@ -78,7 +79,7 @@ CPU_TYPES = \
 	z8k
 
 # Object format types.  This is only used for dependency information.
-# We deliberately omit som, since it does not work as a cross assembler.
+# We deliberately omit some, since it does not work as a cross assembler.
 
 OBJ_FORMATS = \
 	aout \
@@ -101,7 +102,7 @@ CPU_OBJ_VALID = \
 	case $$o in \
 	aout) \
 	  case $$c in \
-	  a29k | arm | cris | i386 | m68k | mips | ns32k | sparc | tahoe | tic30 | vax) \
+	  a29k | arm | cris | i386 | m68k | mips | ns32k | pdp11 | sparc | tahoe | tic30 | vax) \
 	    valid=yes ;; \
 	  esac ;; \
 	bout) \
@@ -245,6 +246,7 @@ TARGET_CPU_CFILES = \
 	config/tc-mn10200.c \
 	config/tc-mn10300.c \
 	config/tc-ns32k.c \
+	config/tc-pdp11.c \
 	config/tc-pj.c \
 	config/tc-ppc.c \
 	config/tc-s390.c \
@@ -286,6 +288,7 @@ TARGET_CPU_HFILES = \
 	config/tc-mn10200.h \
 	config/tc-mn10300.h \
 	config/tc-ns32k.h \
+	config/tc-pdp11.h \
 	config/tc-pj.h \
 	config/tc-ppc.h \
 	config/tc-s390.h \
@@ -1169,6 +1172,9 @@ DEPTC_ns32k_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
   $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
   $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ns32k.h $(INCDIR)/opcode/ns32k.h \
   $(INCDIR)/obstack.h
+DEPTC_pdp11_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-pdp11.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
+  $(INCDIR)/opcode/pdp11.h
 DEPTC_pj_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-pj.h \
   $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
   $(INCDIR)/opcode/pj.h
@@ -1500,6 +1506,9 @@ DEPOBJ_ns32k_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
   $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
   $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ns32k.h subsegs.h \
   $(INCDIR)/obstack.h $(INCDIR)/aout/aout64.h
+DEPOBJ_pdp11_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-pdp11.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
+  $(INCDIR)/obstack.h
 DEPOBJ_pj_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-pj.h \
   $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
   $(INCDIR)/obstack.h subsegs.h
@@ -1773,6 +1782,8 @@ DEP_ns32k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-ns32k.h \
 DEP_ns32k_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
   $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
   $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ns32k.h
+DEP_pdp11_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-pdp11.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
 DEP_pj_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-pj.h \
   $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 DEP_pj_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \

gas/Makefile.in

@@ -174,6 +174,7 @@ CPU_TYPES = \
 	mn10200 \
 	mn10300 \
 	ns32k \
+	pdp11 \
 	pj \
 	ppc \
 	s390 \
@@ -190,7 +191,7 @@ CPU_TYPES = \
 
 
 # Object format types.  This is only used for dependency information.
-# We deliberately omit som, since it does not work as a cross assembler.
+# We deliberately omit some, since it does not work as a cross assembler.
 
 OBJ_FORMATS = \
 	aout \
@@ -214,7 +215,7 @@ CPU_OBJ_VALID = \
 	case $$o in \
 	aout) \
 	  case $$c in \
-	  a29k | arm | cris | i386 | m68k | mips | ns32k | sparc | tahoe | tic30 | vax) \
+	  a29k | arm | cris | i386 | m68k | mips | ns32k | pdp11 | sparc | tahoe | tic30 | vax) \
 	    valid=yes ;; \
 	  esac ;; \
 	bout) \
@@ -362,6 +363,7 @@ TARGET_CPU_CFILES = \
 	config/tc-mn10200.c \
 	config/tc-mn10300.c \
 	config/tc-ns32k.c \
+	config/tc-pdp11.c \
 	config/tc-pj.c \
 	config/tc-ppc.c \
 	config/tc-s390.c \
@@ -404,6 +406,7 @@ TARGET_CPU_HFILES = \
 	config/tc-mn10200.h \
 	config/tc-mn10300.h \
 	config/tc-ns32k.h \
+	config/tc-pdp11.h \
 	config/tc-pj.h \
 	config/tc-ppc.h \
 	config/tc-s390.h \
@@ -938,6 +941,10 @@ DEPTC_ns32k_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
   $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ns32k.h $(INCDIR)/opcode/ns32k.h \
   $(INCDIR)/obstack.h
 
+DEPTC_pdp11_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-pdp11.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
+  $(INCDIR)/opcode/pdp11.h
+
 DEPTC_pj_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-pj.h \
   $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
   $(INCDIR)/opcode/pj.h
@@ -1363,6 +1370,10 @@ DEPOBJ_ns32k_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
   $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ns32k.h subsegs.h \
   $(INCDIR)/obstack.h $(INCDIR)/aout/aout64.h
 
+DEPOBJ_pdp11_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-pdp11.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
+  $(INCDIR)/obstack.h
+
 DEPOBJ_pj_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-pj.h \
   $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
   $(INCDIR)/obstack.h subsegs.h
@@ -1729,6 +1740,9 @@ DEP_ns32k_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
   $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
   $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ns32k.h
 
+DEP_pdp11_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-pdp11.h \
+  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
+
 DEP_pj_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-pj.h \
   $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 

gas/config/tc-pdp11.h

@@ -0,0 +1,33 @@
+/* tc-pdp11.h -- Header file for tc-pdp11.c.
+   Copyright (C) 2001 Free Software Foundation, Inc.
+
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to the Free
+   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+   02111-1307, USA. */
+
+#define TC_PDP11 1
+
+#define TARGET_FORMAT "a.out-pdp11"
+#define TARGET_ARCH bfd_arch_pdp11
+#define TARGET_BYTES_BIG_ENDIAN 0
+
+#define LEX_TILDE (LEX_BEGIN_NAME | LEX_NAME)
+
+#define md_operand(x)
+
+long md_chars_to_number PARAMS ((unsigned char *, int));
+
+/* end of tc-pdp11.h */

gas/configure.in

@@ -384,10 +384,10 @@ changequote([,])dnl
 
       sh-*-linux*)	    fmt=elf em=linux ;;
       sh-*-elf*)	    fmt=elf ;;
-      sh-*-coff*)           fmt=coff ;;
+      sh-*-coff*)           fmt=coff bfd_gas=yes;;
       sh-*-pe*)             fmt=coff em=pe bfd_gas=yes;;
       sh-*-rtemself*)       fmt=elf ;;
-      sh-*-rtems*)	    fmt=coff ;;
+      sh-*-rtems*)	    fmt=coff bfd_gas=yes;;
 
       ns32k-pc532-mach* | ns32k-pc532-ux*)    fmt=aout em=pc532mach ;;
       ns32k-pc532-netbsd* | ns32k-pc532-lites*)  fmt=aout em=nbsd532 ;;
@@ -479,6 +479,7 @@ changequote([,])dnl
       ia64*-*)	bfd_gas=yes ;;
       mips-*)	bfd_gas=yes ;;
       ns32k-*)	bfd_gas=yes ;;
+      pdp11-*)	bfd_gas=yes ;;
       ppc-*)	bfd_gas=yes ;;
       sparc-*)	bfd_gas=yes ;;
       strongarm-*)	bfd_gas=yes ;;
@@ -648,6 +649,7 @@ fi
 # is emulated.
 case ${target_cpu} in
   vax | tahoe )	atof=${target_cpu} ;;
+  pdp11)	atof=vax ;;
   *)		atof=ieee ;;
 esac
 

gas/doc/Makefile.am

@@ -32,6 +32,7 @@ CPU_DOCS = \
 	c-m68k.texi \
 	c-mips.texi \
 	c-ns32k.texi \
+	c-pdp11.texi \
 	c-pj.texi \
 	c-sh.texi \
 	c-sparc.texi \

gas/doc/Makefile.in

@@ -142,6 +142,7 @@ CPU_DOCS = \
 	c-m68k.texi \
 	c-mips.texi \
 	c-ns32k.texi \
+	c-pdp11.texi \
 	c-pj.texi \
 	c-sh.texi \
 	c-sparc.texi \

gas/doc/all.texi

@@ -42,6 +42,7 @@
 @set M680X0
 @set MCORE
 @set MIPS
+@set PDP11
 @set PJ
 @set SH
 @set SPARC

gas/doc/as.texinfo

@@ -546,6 +546,37 @@ unit coprocessor.  The default is to assume an MMU for 68020 and up.
 @end table
 @end ifset
 
+@ifset PDP11
+
+For details about the PDP-11 machine dependent features options,
+see @ref{PDP-11-Options}.
+
+@table @code
+@item -mpic | -mno-pic
+Generate position-independent (or position-dependent) code.  The
+default is @code{-mpic}.
+
+@item -mall
+@itemx -mall-extensions
+Enable all instruction set extensions.  This is the default.
+
+@item -mno-extensions
+Disable all instruction set extensions.
+
+@item -m@var{extension} | -mno-@var{extension}
+Enable (or disable) a particular instruction set extension.
+
+@item -m@var{cpu}
+Enable the instruction set extensions supported by a particular CPU, and
+disable all other extensions.
+
+@item -m@var{machine}
+Enable the instruction set extensions supported by a particular machine
+model, and disable all other extensions.
+@end table
+
+@end ifset
+
 @ifset PJ
 The following options are available when @value{AS} is configured for
 a picoJava processor.
@@ -1667,6 +1698,9 @@ is considered a comment and is ignored.  The line comment character is
 @ifset I960
 @samp{#} on the i960;
 @end ifset
+@ifset PDP11
+@samp{;} for the PDP-11;
+@end ifset
 @ifset PJ
 @samp{;} for picoJava;
 @end ifset
@@ -5271,6 +5305,9 @@ subject, see the hardware manufacturer's manual.
 @ifset SH
 * SH-Dependent::                Hitachi SH Dependent Features
 @end ifset
+@ifset PDP11
+* PDP-11-Dependent::            PDP-11 Dependent Features
+@end ifset
 @ifset PJ
 * PJ-Dependent::                picoJava Dependent Features
 @end ifset
@@ -5389,6 +5426,10 @@ family.
 @include c-ns32k.texi
 @end ifset
 
+@ifset PDP11
+@include c-pdp11.texi
+@end ifset
+
 @ifset PJ
 @include c-pj.texi
 @end ifset

gas/doc/c-pdp11.texi

@@ -0,0 +1,354 @@
+@c Copyright (C) 2001 Free Software Foundation, Inc.
+@c This is part of the GAS manual.
+@c For copying conditions, see the file as.texinfo.
+@ifset GENERIC
+@page
+@node PDP-11-Dependent
+@chapter PDP-11 Dependent Features
+@end ifset
+@ifclear GENERIC
+@node Machine Dependencies
+@chapter PDP-11 Dependent Features
+@end ifclear
+
+@cindex PDP-11 support
+
+@menu
+* PDP-11-Options::		Options
+* PDP-11-Pseudos::		Assembler Directives
+* PDP-11-Syntax::		DEC Syntax versus BSD Syntax
+* PDP-11-Mnemonics::		Instruction Naming
+* PDP-11-Synthetic::		Synthetic Instructions
+@end menu
+
+@node PDP-11-Options
+@section Options
+
+@cindex options for PDP-11
+
+The PDP-11 version of @code{@value{AS}} has a rich set of machine
+dependent options.
+
+@subsection Code Generation Options
+
+@table @code
+@cindex -mpic
+@cindex -mno-pic
+@item -mpic | -mno-pic
+Generate position-independent (or position-dependent) code.
+
+The default is to generate position-independent code.
+@end table
+
+@subsection Instruction Set Extention Options
+
+These options enables or disables the use of extensions over the base
+line instruction set as introduced by the first PDP-11 CPU: the KA11.
+Most options come in two variants: a @code{-m}@var{extension} that
+enables @var{extension}, and a @code{-mno-}@var{extension} that disables
+@var{extension}.
+
+The default is to enable all extensions.
+
+@table @code
+@cindex -mall
+@cindex -mall-extensions
+@item -mall | -mall-extensions
+Enable all instruction set extensions.
+
+@cindex -mno-extensions
+@item -mno-extensions
+Disable all instruction set extensions.
+
+@cindex -mcis
+@cindex -mno-cis
+@item -mcis | -mno-cis
+Enable (or disable) the use of the commersial instruction set, which
+consists of these instructions: @code{ADDNI}, @code{ADDN}, @code{ADDPI},
+@code{ADDP}, @code{ASHNI}, @code{ASHN}, @code{ASHPI}, @code{ASHP},
+@code{CMPCI}, @code{CMPC}, @code{CMPNI}, @code{CMPN}, @code{CMPPI},
+@code{CMPP}, @code{CVTLNI}, @code{CVTLN}, @code{CVTLPI}, @code{CVTLP},
+@code{CVTNLI}, @code{CVTNL}, @code{CVTNPI}, @code{CVTNP}, @code{CVTPLI},
+@code{CVTPL}, @code{CVTPNI}, @code{CVTPN}, @code{DIVPI}, @code{DIVP},
+@code{L2DR}, @code{L3DR}, @code{LOCCI}, @code{LOCC}, @code{MATCI},
+@code{MATC}, @code{MOVCI}, @code{MOVC}, @code{MOVRCI}, @code{MOVRC},
+@code{MOVTCI}, @code{MOVTC}, @code{MULPI}, @code{MULP}, @code{SCANCI},
+@code{SCANC}, @code{SKPCI}, @code{SKPC}, @code{SPANCI}, @code{SPANC},
+@code{SUBNI}, @code{SUBN}, @code{SUBPI}, and @code{SUBP}.
+
+@cindex -mcsm
+@cindex -mno-csm
+@item -mcsm | -mno-csm
+Enable (or disable) the use of the @code{CSM} instruction.
+
+@cindex -meis
+@cindex -mno-eis
+@item -meis | -mno-eis
+Enable (or disable) the use of the extended instruction set, which
+consists of these instructions: @code{ASHC}, @code{ASH}, @code{DIV},
+@code{MARK}, @code{MUL}, @code{RTT}, @code{SOB} @code{SXT}, and
+@code{XOR}.
+
+@cindex -mfis
+@cindex -mno-fis
+@cindex -mkev11
+@cindex -mkev11
+@cindex -mno-kev11
+@item -mfis | -mkev11
+@itemx -mno-fis | -mno-kev11
+Enable (or diasble) the use of the KEV11 floating-point instructions:
+@code{FADD}, @code{FDIV}, @code{FMUL}, and @code{FSUB}.
+
+@cindex -mfpp
+@cindex -mno-fpp
+@cindex -mfpu
+@cindex -mno-fpu
+@cindex -mfp-11
+@cindex -mno-fp-11
+@item -mfpp | -mfpu | -mfp-11
+@itemx -mno-fpp | -mno-fpu | -mno-fp-11
+Enable (or disable) the use of FP-11 floating-point instructions:
+@code{ABSF}, @code{ADDF}, @code{CFCC}, @code{CLRF}, @code{CMPF},
+@code{DIVF}, @code{LDCFF}, @code{LDCIF}, @code{LDEXP}, @code{LDF},
+@code{LDFPS}, @code{MODF}, @code{MULF}, @code{NEGF}, @code{SETD},
+@code{SETF}, @code{SETI}, @code{SETL}, @code{STCFF}, @code{STCFI},
+@code{STEXP}, @code{STF}, @code{STFPS}, @code{STST}, @code{SUBF}, and
+@code{TSTF}.
+
+@cindex -mlimited-eis
+@cindex -mno-limited-eis
+@item -mlimited-eis | -mno-limited-eis
+Enable (or disable) the use of the limited extended instruction set:
+@code{MARK}, @code{RTT}, @code{SOB}, @code{SXT}, and @code{XOR}.
+
+The -mno-limited-eis options also implies -mno-eis.
+
+@cindex -mmfpt
+@cindex -mno-mfpt
+@item -mmfpt | -mno-mfpt
+Enable (or disable) the use of the @code{MFPT} instruction.
+
+@cindex -mmutiproc
+@cindex -mno-mutiproc
+@item -mmultiproc | -mno-multiproc
+Enable (or disable) the use of multiprocessor instructions: @code{TSTSET} and
+@code{WRTLCK}.
+
+@cindex -mmxps
+@cindex -mno-mxps
+@item -mmxps | -mno-mxps
+Enable (or disable) the use of the @code{MFPS} and @code{MTPS} instructions.
+
+@cindex -mspl
+@cindex -mno-spl
+@item -mspl | -mno-spl
+Enable (or disable) the use of the @code{SPL} instruction.
+
+@cindex -mmicrocode
+@cindex -mno-microcode
+Enable (or disable) the use of the microcode instructions: @code{LDUB},
+@code{MED}, and @code{XFC}.
+@end table
+
+@subsection CPU Model Options
+
+These options enable the instruction set extensions supported by a
+particular CPU, and disables all other extensions.
+
+@table @code
+@cindex -mka11
+@item -mka11
+KA11 CPU.  Base line instruction set only.
+
+@cindex -mkb11
+@item -mkb11
+KB11 CPU.  Enable extended instruction set and @code{SPL}.
+
+@cindex -mkd11a
+@item -mkd11a
+KD11-A CPU.  Enable limited extended instruction set.
+
+@cindex -mkd11b
+@item -mkd11b
+KD11-B CPU.  Base line instruction set only.
+
+@cindex -mkd11d
+@item -mkd11d
+KD11-D CPU.  Base line instruction set only.
+
+@cindex -mkd11e
+@item -mkd11e
+KD11-E CPU.  Enable extended instruction set, @code{MFPS}, and @code{MTPS}.
+
+@cindex -mkd11f
+@cindex -mkd11h
+@cindex -mkd11q
+@item -mkd11f | -mkd11h | -mkd11q
+KD11-F, KD11-H, or KD11-Q CPU.  Enable limited extended instruction set,
+@code{MFPS}, and @code{MTPS}.
+
+@cindex -mkd11k
+@item -mkd11k
+KD11-K CPU.  Enable extended instruction set, @code{LDUB}, @code{MED},
+@code{MFPS}, @code{MFPT}, @code{MTPS}, and @code{XFC}.
+
+@cindex -mkd11z
+@item -mkd11z
+KD11-Z CPU.  Enable extended instruction set, @code{CSM}, @code{MFPS},
+@code{MFPT}, @code{MTPS}, and @code{SPL}.
+
+@cindex -mf11
+@item -mf11
+F11 CPU.  Enable extended instruction set, @code{MFPS}, @code{MFPT}, and
+@code{MTPS}.
+
+@cindex -mj11
+@item -mj11
+J11 CPU.  Enable extended instruction set, @code{CSM}, @code{MFPS},
+@code{MFPT}, @code{MTPS}, @code{SPL}, @code{TSTSET}, and @code{WRTLCK}.
+
+@cindex -mt11
+@item -mt11
+T11 CPU.  Enable limited extended instruction set, @code{MFPS}, and
+@code{MTPS}.
+@end table
+
+@subsection Machine Model Options
+
+These options enable the instruction set extensions supported by a
+particular machine model, and disables all other extensions.
+
+@table @code
+@cindex -m11/03
+@item -m11/03
+Same as @code{-mkd11f}.
+
+@cindex -m11/04
+@item -m11/04
+Same as @code{-mkd11d}.
+
+@cindex -m11/05
+@cindex -m11/10
+@item -m11/05 | -m11/10
+Same as @code{-mkd11b}.
+
+@cindex -m11/15
+@cindex -m11/20
+@item -m11/15 | -m11/20
+Same as @code{-mka11}.
+
+@cindex -m11/21
+@item -m11/21
+Same as @code{-mt11}.
+
+@cindex -m11/23
+@cindex -m11/24
+@item -m11/23 | -m11/24
+Same as @code{-mf11}.
+
+@cindex -m11/34
+@item -m11/34
+Same as @code{-mkd11e}.
+
+@cindex -m11/34a
+@item -m11/34a
+Ame as @code{-mkd11e} @code{-mfpp}.
+
+@cindex -m11/35
+@cindex -m11/40
+@item -m11/35 | -m11/40
+Same as @code{-mkd11a}.
+
+@cindex -m11/44
+@item -m11/44
+Same as @code{-mkd11z}.
+
+@cindex -m11/45
+@cindex -m11/50
+@cindex -m11/55
+@cindex -m11/70
+@item -m11/45 | -m11/50 | -m11/55 | -m11/70
+Same as @code{-mkb11}.
+
+@cindex -m11/53
+@cindex -m11/73
+@cindex -m11/83
+@cindex -m11/84
+@cindex -m11/93
+@cindex -m11/94
+@item -m11/53 | -m11/73 | -m11/83 | -m11/84 | -m11/93 | -m11/94
+Same as @code{-mj11}.
+
+@cindex -m11/60
+@item -m11/60
+Same as @code{-mkd11k}.
+@end table
+
+@node PDP-11-Pseudos
+@section Assembler Directives
+
+The PDP-11 version of @code{@value{AS}} has a few machine
+dependent assembler directives.
+
+@table @code
+@item .bss
+Switch to the @code{bss} section.
+
+@item .even
+Align the location counter to an even number.
+@end table
+
+@node PDP-11-Syntax
+@section PDP-11 Assembly Language Syntax
+
+@cindex PDP-11 syntax
+
+@cindex DEC syntax
+@cindex BSD syntax
+@code{@value{AS}} supports both DEC syntax and BSD syntax.  The only
+difference is that in DEC syntax, a @code{#} character is used to denote
+an immediate constants, while in BSD syntax the character for this
+purpose is @code{$}.
+
+@cindex PDP-11 general-purpose register syntax
+eneral-purpose registers are named @code{r0} through @code{r7}.
+Mnemonic alternatives for @code{r6} and @code{r7} are @code{sp} and
+@code{pc}, respectively.
+
+@cindex PDP-11 floating-point register syntax
+Floating-point registers are named @code{ac0} through @code{ac3}, or
+alternatively @code{fr0} through @code{fr3}.
+
+@cindex PDP-11 comments
+Comments are started with a @code{#} or a @code{/} character, and extend
+to the end of the line.  (FIXME: clash with immediates?)
+
+@node PDP-11-Mnemonics
+@section Instruction Naming
+
+@cindex PDP-11 instruction naming
+
+Some instructions have alternative names.
+
+@table @code
+@item BCC
+@code{BHIS}
+
+@item BCS
+@code{BLO}
+
+@item L2DR
+@code{L2D}
+
+@item L3DR
+@code{L3D}
+
+@item SYS
+@code{TRAP}
+@end table
+
+@node PDP-11-Synthetic
+@section Synthetic Instructions
+
+The @code{JBR} and @code{J}@var{CC} synthetic instructions are not
+supported yet.

gas/po/POTFILES.in

@@ -92,6 +92,8 @@ config/tc-mn10300.c
 config/tc-mn10300.h
 config/tc-ns32k.c
 config/tc-ns32k.h
+config/tc-pdp11.c
+config/tc-pdp11.h
 config/tc-pj.c
 config/tc-pj.h
 config/tc-ppc.c

gprof/po/gprof.pot

@@ -6,7 +6,7 @@
 msgid ""
 msgstr ""
 "Project-Id-Version: PACKAGE VERSION\n"
-"POT-Creation-Date: 2000-07-27 16:32-0700\n"
+"POT-Creation-Date: 2001-02-06 18:02-0800\n"
 "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
 "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
 "Language-Team: LANGUAGE <LL@li.org>\n"
@@ -33,27 +33,27 @@ msgstr ""
 msgid "[find_call] 0x%lx: bsr"
 msgstr ""
 
-#: basic_blocks.c:123 call_graph.c:86 hist.c:122
+#: basic_blocks.c:125 call_graph.c:86 hist.c:122
 #, c-format
 msgid "%s: %s: unexpected end of file\n"
 msgstr ""
 
-#: basic_blocks.c:198
+#: basic_blocks.c:200
 #, c-format
 msgid "%s: warning: ignoring basic-block exec counts (use -l or --line)\n"
 msgstr ""
 
 #. FIXME: This only works if bfd_vma is unsigned long.
-#: basic_blocks.c:296 basic_blocks.c:306
+#: basic_blocks.c:298 basic_blocks.c:308
 #, c-format
 msgid "%s:%d: (%s:0x%lx) %lu executions\n"
 msgstr ""
 
-#: basic_blocks.c:297 basic_blocks.c:307
+#: basic_blocks.c:299 basic_blocks.c:309
 msgid "<unknown>"
 msgstr ""
 
-#: basic_blocks.c:551
+#: basic_blocks.c:553
 #, c-format
 msgid ""
 "\n"
@@ -64,36 +64,36 @@ msgid ""
 "\n"
 msgstr ""
 
-#: basic_blocks.c:575
+#: basic_blocks.c:577
 msgid ""
 "\n"
 "Execution Summary:\n"
 "\n"
 msgstr ""
 
-#: basic_blocks.c:576
+#: basic_blocks.c:578
 #, c-format
 msgid "%9ld   Executable lines in this file\n"
 msgstr ""
 
-#: basic_blocks.c:578
+#: basic_blocks.c:580
 #, c-format
 msgid "%9ld   Lines executed\n"
 msgstr ""
 
-#: basic_blocks.c:579
+#: basic_blocks.c:581
 #, c-format
 msgid "%9.2f   Percent of the file executed\n"
 msgstr ""
 
-#: basic_blocks.c:583
+#: basic_blocks.c:585
 #, c-format
 msgid ""
 "\n"
 "%9lu   Total number of line executions\n"
 msgstr ""
 
-#: basic_blocks.c:585
+#: basic_blocks.c:587
 #, c-format
 msgid "%9.2f   Average executions per line\n"
 msgstr ""

include/ChangeLog

@@ -1,3 +1,7 @@
+2001-02-18  lars brinkhoff  <lars@nocrew.org>
+
+	* dis-asm.h: Add PDP-11 target.
+
 2001-02-09  Martin Schwidefsky  <schwidefsky@de.ibm.com>
 
 	* dis-asm.h: Add linux target for S/390.

include/dis-asm.h

@@ -192,6 +192,7 @@ extern int print_insn_mcore		PARAMS ((bfd_vma, disassemble_info*));
 extern int print_insn_mn10200		PARAMS ((bfd_vma, disassemble_info*));
 extern int print_insn_mn10300		PARAMS ((bfd_vma, disassemble_info*));
 extern int print_insn_ns32k		PARAMS ((bfd_vma, disassemble_info*));
+extern int print_insn_pdp11		PARAMS ((bfd_vma, disassemble_info*));
 extern int print_insn_big_powerpc	PARAMS ((bfd_vma, disassemble_info*));
 extern int print_insn_little_powerpc	PARAMS ((bfd_vma, disassemble_info*));
 extern int print_insn_rs6000		PARAMS ((bfd_vma, disassemble_info*));

include/opcode/ChangeLog

@@ -1,4 +1,8 @@
-Mon Feb 12 17:40:54 CET 2001  Jan Hubicka  <jh@suse.cz>
+2001-02-18  lars brinkhoff  <lars@nocrew.org>
+
+	* pdp11.h: New file.
+
+2001-02-12  Jan Hubicka  <jh@suse.cz>
 
 	* i386.h (i386_optab): SSE integer converison instructions have
 	64bit versions on x86-64.
@@ -29,7 +33,7 @@ Mon Feb 12 17:40:54 CET 2001  Jan Hubicka  <jh@suse.cz>
 	(pa_opcodes): Add entries for missing wide mode ldi,ldo,ldw,stw.
 	Remove duplicate "ldw j(s,b),x".  Sort some entries.
 
-Sat Jan 13 09:56:32 MET 2001  Jan Hubicka  <jh@suse.cz>
+2001-01-13  Jan Hubicka  <jh@suse.cz>
 
 	* i386.h (i386_optab): Fix pusha and ret templates.
 
@@ -676,7 +680,7 @@ Mon Feb  1 21:09:14 1999  Catherine Moore  <clm@cygnus.com>
 	* cgen.h (enum cgen_mode): Add CGEN_MODE_TARGET_MAX, CGEN_MODE_INT,
 	CGEN_MODE_UINT.
 
-Sat Jan 16 01:29:25 1999  Jeffrey A Law  (law@cygnus.com)
+1999-01-16  Jeffrey A Law  (law@cygnus.com)
 
 	* hppa.h (bv): Fix mask.
 
@@ -1027,7 +1031,7 @@ Mon Feb  2 17:10:38 1998  Steve Haworth  <steve@pm.cse.rmit.EDU.AU>
 
 	* tic30.h: New file.
 
-Thu Jan 22 17:54:56 1998  Nick Clifton  <nickc@cygnus.com>
+Jan 22 17:54:56 1998  Nick Clifton  <nickc@cygnus.com>
 
 	* cgen.h: Add prototypes for cgen_save_fixups(),
 	cgen_restore_fixups(), and cgen_swap_fixups().  Change prototype

include/opcode/pdp11.h

@@ -0,0 +1,78 @@
+/* PDP-11 opcde list.
+   Copyright (C) 2001 Free Software Foundation, Inc.
+
+This file is part of GDB and GAS.
+
+GDB and GAS are free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 1, or (at your option)
+any later version.
+
+GDB and GAS are distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GDB or GAS; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+/*
+ * PDP-11 opcode types.
+ */
+
+#define PDP11_OPCODE_NO_OPS	 0
+#define PDP11_OPCODE_REG	 1	/* register */
+#define PDP11_OPCODE_OP		 2	/* generic operand */
+#define PDP11_OPCODE_REG_OP	 3	/* register and generic operand */
+#define PDP11_OPCODE_REG_OP_REV	 4	/* register and generic operand,
+					   reversed syntax */
+#define PDP11_OPCODE_AC_OP	 5	/* fpu accumulator and generic
+					   operand */
+#define PDP11_OPCODE_OP_OP	 6	/* two generic operands */
+#define PDP11_OPCODE_DISPL	 7	/* pc-relative displacement */
+#define PDP11_OPCODE_REG_DISPL	 8	/* redister and pc-relative
+					   displacement */
+#define PDP11_OPCODE_IMM8	 9	/* 8-bit immediate */
+#define PDP11_OPCODE_IMM6	10	/* 6-bit immediate */
+#define PDP11_OPCODE_IMM3	11	/* 3-bit immediate */
+#define PDP11_OPCODE_ILLEGAL	12	/* illegal instruction */
+
+/*
+ * PDP-11 instruction set extensions.
+ *
+ * Please keep the numbers low, as they are used as indices into
+ * an array.
+ */
+
+#define PDP11_NONE	 0	/* not in instruction set */
+#define PDP11_BASIC	 1	/* basic instruction set (11/20 etc) */
+#define PDP11_CSM	 2	/* commercial instruction set */
+#define PDP11_CIS	 3	/* commercial instruction set */
+#define PDP11_EIS	 4	/* extended instruction set (11/45 etc) */
+#define PDP11_FIS	 5	/* KEV11 floating-point instructions */
+#define PDP11_FPP	 6	/* FP-11 floating-point instructions */
+#define PDP11_LEIS	 7	/* limited extended instruction set
+				   (11/40 etc) */
+#define PDP11_MFPT	 8	/* move from processor type */
+#define PDP11_MPROC	 9	/* multiprocessor instructions: tstset,
+				   wrtlck */
+#define PDP11_MXPS	10	/* move from/to processor status */
+#define PDP11_SPL	11	/* set priority level */
+#define PDP11_UCODE	12	/* microcode instructions: ldub, med, xfc */
+#define PDP11_EXT_NUM	13	/* total number of extension types */
+
+struct pdp11_opcode
+{
+  const char *name;
+  int opcode;
+  int mask;
+  int type;
+  int extension;
+};
+
+extern const struct pdp11_opcode pdp11_opcodes[];
+extern const struct pdp11_opcode pdp11_aliases[];
+extern const int pdp11_num_opcodes, pdp11_num_aliases;
+
+/* end of pdp11.h */

ld/ChangeLog

@@ -1,3 +1,9 @@
+2001-02-18  lars brinkhoff  <lars@nocrew.org>
+
+	* Makefile.am: Add PDP-11 target.
+	* configure.tgt: Likewise.
+	* emulparams/pdp11.sh: New file.
+
 2001-02-17  David O'Brien  <obrien@FreeBSD.org>
 
 	* configure.host: Add a generic FreeBSD configuration entry such that

ld/Makefile.am

@@ -208,6 +208,7 @@ ALL_EMULATIONS = \
 	enews.o \
 	ens32knbsd.o \
 	epc532macha.o \
+	epdp11.o \
 	epjelf.o \
 	epjlelf.o \
 	eppcmacos.o \
@@ -683,6 +684,9 @@ ens32knbsd.c:	$(srcdir)/emulparams/ns32knbsd.sh \
 epc532macha.c: $(srcdir)/emulparams/pc532macha.sh \
   $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS}
 	${GENSCRIPTS} pc532macha "$(tdir_pc532macha)"
+epdp11.c: $(srcdir)/emulparams/pdp11.sh \
+  $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS}
+	${GENSCRIPTS} pdp11 "$(tdir_pdp11)"
 epjelf.c: $(srcdir)/emulparams/pjelf.sh \
   $(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
 	${GENSCRIPTS} pjelf "$(tdir_pjelf)"

ld/Makefile.in

@@ -316,6 +316,7 @@ ALL_EMULATIONS = \
 	enews.o \
 	ens32knbsd.o \
 	epc532macha.o \
+	epdp11.o \
 	epjelf.o \
 	epjlelf.o \
 	eppcmacos.o \
@@ -1397,6 +1398,9 @@ ens32knbsd.c:	$(srcdir)/emulparams/ns32knbsd.sh \
 epc532macha.c: $(srcdir)/emulparams/pc532macha.sh \
   $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS}
 	${GENSCRIPTS} pc532macha "$(tdir_pc532macha)"
+epdp11.c: $(srcdir)/emulparams/pdp11.sh \
+  $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS}
+	${GENSCRIPTS} pdp11 "$(tdir_pdp11)"
 epjelf.c: $(srcdir)/emulparams/pjelf.sh \
   $(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
 	${GENSCRIPTS} pjelf "$(tdir_pjelf)"

ld/configure.tgt

@@ -286,6 +286,7 @@ ns32k-pc532-netbsd* | ns32k-pc532-lites*) targ_emul=ns32knbsd ;;
 powerpc-*-linux-gnu*)	targ_emul=elf32ppclinux;
 			targ_extra_emuls="elf32ppc elf32ppcsim";
 			targ_extra_libpath=elf32ppc ;;
+pdp11-*-*)		targ_emul=pdp11 ;;
 pjl*-*-*)	        targ_emul=pjlelf ; targ_extra_emuls="elf_i386" ;;
 pj*-*-*)	        targ_emul=pjelf ;;
 powerpc-*-elf* | powerpc-*-eabi* | powerpc-*-sysv* \

ld/emulparams/pdp11.sh

@@ -0,0 +1,5 @@
+SCRIPT_NAME=aout
+OUTPUT_FORMAT="a.out-pdp11"
+TEXT_START_ADDR=0
+TARGET_PAGE_SIZE=256
+ARCH=pdp11

ld/po/ld.pot

@@ -6,7 +6,7 @@
 msgid ""
 msgstr ""
 "Project-Id-Version: PACKAGE VERSION\n"
-"POT-Creation-Date: 2001-02-06 18:03-0800\n"
+"POT-Creation-Date: 2001-02-18 11:47-0800\n"
 "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
 "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
 "Language-Team: LANGUAGE <LL@li.org>\n"
@@ -373,31 +373,31 @@ msgstr ""
 msgid "%F%S: undefined symbol `%s' referenced in expression\n"
 msgstr ""
 
-#: ldexp.c:600
+#: ldexp.c:601
 msgid "%F%S can not PROVIDE assignment to location counter\n"
 msgstr ""
 
-#: ldexp.c:610
+#: ldexp.c:611
 msgid "%F%S invalid assignment to location counter\n"
 msgstr ""
 
-#: ldexp.c:614
+#: ldexp.c:615
 msgid "%F%S assignment to location counter invalid outside of SECTION\n"
 msgstr ""
 
-#: ldexp.c:624
+#: ldexp.c:625
 msgid "%F%S cannot move location counter backwards (from %V to %V)\n"
 msgstr ""
 
-#: ldexp.c:652
+#: ldexp.c:653
 msgid "%P%F:%s: hash creation failed\n"
 msgstr ""
 
-#: ldexp.c:951
+#: ldexp.c:955
 msgid "%F%S nonconstant expression for %s\n"
 msgstr ""
 
-#: ldexp.c:984
+#: ldexp.c:988
 msgid "%F%S non constant expression for %s\n"
 msgstr ""
 

opcodes/ChangeLog

@@ -1,3 +1,11 @@
+2001-02-18  lars brinkhoff  <lars@nocrew.org>
+
+        * Makefile.am: Add PDP-11 target.
+        * configure.in: Likewise.
+        * disassemble.c: Likewise.
+        * pdp11-dis.c: New file.
+        * pdp11-opc.c: New file.
+
 2001-02-14  Jim Wilson  <wilson@redhat.com>
 
 	* ia64-ic.tbl: Update from Intel.  Add setf to fr-writers.

opcodes/Makefile.am

@@ -97,6 +97,8 @@ CFILES = \
 	m10300-dis.c \
 	m10300-opc.c \
 	ns32k-dis.c \
+	pdp11-dis.c \
+	pdp11-opc.c \
 	pj-dis.c \
 	pj-opc.c \
 	ppc-dis.c \
@@ -170,11 +172,13 @@ ALL_MACHINES = \
 	mips-dis.lo \
 	mips-opc.lo \
 	mips16-opc.lo \
+	ns32k-dis.lo \
+	pdp11-dis.lo \
+	pdp11-opc.lo \
 	pj-dis.lo \
 	pj-opc.lo \
 	ppc-dis.lo \
 	ppc-opc.lo \
-	ns32k-dis.lo \
 	s390-dis.lo \
 	s390-opc.lo \
 	sh-dis.lo \
@@ -486,6 +490,8 @@ m10300-opc.lo: m10300-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
 ns32k-dis.lo: ns32k-dis.c $(BFD_H) $(INCDIR)/ansidecl.h \
   sysdep.h config.h $(INCDIR)/dis-asm.h $(INCDIR)/opcode/ns32k.h \
   opintl.h
+pdp11-dis.lo: pdp11-dis.c $(INCDIR)/dis-asm.h $(INCDIR)/opcode/pdp11.h
+pdp11-opc.lo: pdp11-opc.c $(INCDIR)/opcode/pdp11.h
 pj-dis.lo: pj-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/pj.h $(INCDIR)/dis-asm.h $(BFD_H)
 pj-opc.lo: pj-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \

opcodes/Makefile.in

@@ -208,6 +208,8 @@ CFILES = \
 	m10300-dis.c \
 	m10300-opc.c \
 	ns32k-dis.c \
+	pdp11-dis.c \
+	pdp11-opc.c \
 	pj-dis.c \
 	pj-opc.c \
 	ppc-dis.c \
@@ -282,11 +284,13 @@ ALL_MACHINES = \
 	mips-dis.lo \
 	mips-opc.lo \
 	mips16-opc.lo \
+	ns32k-dis.lo \
+	pdp11-dis.lo \
+	pdp11-opc.lo \
 	pj-dis.lo \
 	pj-opc.lo \
 	ppc-dis.lo \
 	ppc-opc.lo \
-	ns32k-dis.lo \
 	s390-dis.lo \
 	s390-opc.lo \
 	sh-dis.lo \
@@ -370,7 +374,7 @@ acinclude.m4 aclocal.m4 config.in configure configure.in
 
 DISTFILES = $(DIST_COMMON) $(SOURCES) $(HEADERS) $(TEXINFOS) $(EXTRA_DIST)
 
-TAR = tar
+TAR = gtar
 GZIP_ENV = --best
 SOURCES = libopcodes.a.c $(libopcodes_la_SOURCES)
 OBJECTS = libopcodes.a.$(OBJEXT) $(libopcodes_la_OBJECTS)
@@ -996,6 +1000,8 @@ m10300-opc.lo: m10300-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
 ns32k-dis.lo: ns32k-dis.c $(BFD_H) $(INCDIR)/ansidecl.h \
   sysdep.h config.h $(INCDIR)/dis-asm.h $(INCDIR)/opcode/ns32k.h \
   opintl.h
+pdp11-dis.lo: pdp11-dis.c $(INCDIR)/dis-asm.h $(INCDIR)/opcode/pdp11.h
+pdp11-opc.lo: pdp11-opc.c $(INCDIR)/opcode/pdp11.h
 pj-dis.lo: pj-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/opcode/pj.h $(INCDIR)/dis-asm.h $(BFD_H)
 pj-opc.lo: pj-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \

opcodes/configure

@@ -4542,6 +4542,7 @@ if test x${all_targets} = xfalse ; then
 	bfd_mn10200_arch)	ta="$ta m10200-dis.lo m10200-opc.lo" ;;
 	bfd_mn10300_arch)	ta="$ta m10300-dis.lo m10300-opc.lo" ;;
 	bfd_ns32k_arch)		ta="$ta ns32k-dis.lo" ;;
+	bfd_pdp11_arch)		ta="$ta pdp11-dis.lo pdp11-opc.lo" ;;
 	bfd_pj_arch)	        ta="$ta pj-dis.lo pj-opc.lo" ;;
 	bfd_powerpc_arch)	ta="$ta ppc-dis.lo ppc-opc.lo" ;;
 	bfd_pyramid_arch)	;;

opcodes/configure.in

@@ -196,6 +196,7 @@ if test x${all_targets} = xfalse ; then
 	bfd_mn10200_arch)	ta="$ta m10200-dis.lo m10200-opc.lo" ;;
 	bfd_mn10300_arch)	ta="$ta m10300-dis.lo m10300-opc.lo" ;;
 	bfd_ns32k_arch)		ta="$ta ns32k-dis.lo" ;;
+	bfd_pdp11_arch)		ta="$ta pdp11-dis.lo pdp11-opc.lo" ;;
 	bfd_pj_arch)	        ta="$ta pj-dis.lo pj-opc.lo" ;;
 	bfd_powerpc_arch)	ta="$ta ppc-dis.lo ppc-opc.lo" ;;
 	bfd_pyramid_arch)	;;

opcodes/disassemble.c

@@ -47,6 +47,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 #define ARCH_mn10200
 #define ARCH_mn10300
 #define ARCH_ns32k
+#define ARCH_pdp11
 #define ARCH_pj
 #define ARCH_powerpc
 #define ARCH_rs6000
@@ -225,6 +226,11 @@ disassembler (abfd)
       disassemble = print_insn_mn10300;
       break;
 #endif
+#ifdef ARCH_pdp11
+    case bfd_arch_pdp11:
+      disassemble = print_insn_pdp11;
+      break;
+#endif
 #ifdef ARCH_pj
     case bfd_arch_pj:
       disassemble = print_insn_pj;

opcodes/pdp11-dis.c

@@ -0,0 +1,323 @@
+/* Print DEC PDP-11 instructions.
+   Copyright 2001 Free Software Foundation, Inc.
+
+This file is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#include "dis-asm.h"
+#include "opcode/pdp11.h"
+
+#define AFTER_INSTRUCTION	"\t"
+#define OPERAND_SEPARATOR	", "
+
+#define JUMP	0x1000	/* flag that this operand is used in a jump */
+
+#define FPRINTF	(*info->fprintf_func)
+#define F	info->stream
+
+/* sign-extend a 16-bit number in an int */
+#define SIGN_BITS	(8 * sizeof (int) - 16)
+#define sign_extend(x) (((x) << SIGN_BITS) >> SIGN_BITS)
+
+static int read_word PARAMS ((bfd_vma memaddr, int *word,
+			      disassemble_info *info));
+static void print_signed_octal PARAMS ((int n, disassemble_info *info));
+static void print_reg PARAMS ((int reg, disassemble_info *info));
+static void print_freg PARAMS ((int freg, disassemble_info *info));
+static int print_operand PARAMS ((bfd_vma *memaddr, int code,
+				  disassemble_info *info));
+int print_insn_pdp11 PARAMS ((bfd_vma memaddr, disassemble_info *info));
+
+static int
+read_word (memaddr, word, info)
+     bfd_vma memaddr;
+     int *word;
+     disassemble_info *info;
+{
+  int status;
+  bfd_byte x[2];
+
+  status = (*info->read_memory_func) (memaddr, x, 2, info);
+  if (status != 0)
+    return -1;
+
+  *word = x[1] << 8 | x[0];
+  return 0;
+}
+
+static void
+print_signed_octal (n, info)
+     int n;
+     disassemble_info *info;
+{
+  if (n < 0)
+    FPRINTF (F, "-%o", -n);
+  else
+    FPRINTF (F, "%o", n);
+}
+
+static void
+print_reg (reg, info)
+     int reg;
+     disassemble_info *info;
+{
+  /* mask off the addressing mode, if any */
+  reg &= 7;
+
+  switch (reg)
+    {
+    case 0: case 1: case 2: case 3: case 4: case 5:
+		FPRINTF (F, "r%d", reg); break;
+    case 6:	FPRINTF (F, "sp"); break;
+    case 7:	FPRINTF (F, "pc"); break;
+    default:	/* error */
+    }
+}
+
+static void
+print_freg (freg, info)
+     int freg;
+     disassemble_info *info;
+{
+  FPRINTF (F, "fr%d", freg);
+}
+
+static int
+print_operand (memaddr, code, info)
+     bfd_vma *memaddr;
+     int code;
+     disassemble_info *info;
+{
+  int mode = (code >> 3) & 7;
+  int reg = code & 7;
+  int disp;
+
+  switch (mode)
+    {
+    case 0:
+      print_reg (reg, info);
+      break;
+    case 1:
+      FPRINTF (F, "(");
+      print_reg (reg, info);
+      FPRINTF (F, ")");
+      break;
+    case 2:
+      if (reg == 7)
+	{
+	  int data;
+	  if (read_word (*memaddr, &data, info) < 0)
+	    return -1;
+	  FPRINTF (F, "$");
+	  print_signed_octal (sign_extend (data), info);
+	  *memaddr += 2;
+	}
+      else
+	{
+	  FPRINTF (F, "(");
+	  print_reg (reg, info);
+	  FPRINTF (F, ")+");
+	}
+	break;
+    case 3:
+      if (reg == 7)
+	{
+	  int address;
+	  if (read_word (*memaddr, &address, info) < 0)
+	    return -1;
+	  FPRINTF (F, "*$%o", address);
+	  *memaddr += 2;
+	}
+      else
+	{
+	  FPRINTF (F, "*(");
+	  print_reg (reg, info);
+	  FPRINTF (F, ")+");
+	}
+	break;
+    case 4:
+      FPRINTF (F, "-(");
+      print_reg (reg, info);
+      FPRINTF (F, ")");
+      break;
+    case 5:
+      FPRINTF (F, "*-(");
+      print_reg (reg, info);
+      FPRINTF (F, ")");
+      break;
+    case 6:
+    case 7:
+      if (read_word (*memaddr, &disp, info) < 0)
+	return -1;
+      *memaddr += 2;
+      if (reg == 7)
+	{
+	  bfd_vma address = *memaddr + sign_extend (disp);
+	  if (!(code & JUMP))
+	    FPRINTF (F, "*$");
+	  (*info->print_address_func) (address, info);
+	}
+      else
+	{
+	  if (mode == 7)
+	    FPRINTF (F, "*");
+	  print_signed_octal (sign_extend (disp), info);
+	  FPRINTF (F, "(");
+	  print_reg (reg, info);
+	  FPRINTF (F, ")");
+	}
+      break;
+    }
+
+  return 0;
+}
+
+/* Print the PDP-11 instruction at address MEMADDR in debugged memory,
+   on INFO->STREAM.  Returns length of the instruction, in bytes.  */
+
+int
+print_insn_pdp11 (memaddr, info)
+     bfd_vma memaddr;
+     disassemble_info *info;
+{
+  bfd_vma start_memaddr = memaddr;
+  int opcode;
+  int src, dst;
+  int i;
+
+  info->bytes_per_line = 6;
+  info->bytes_per_chunk = 2;
+  info->display_endian = BFD_ENDIAN_LITTLE;
+
+  if (read_word (memaddr, &opcode, info) != 0)
+    return -1;
+  memaddr += 2;
+
+  src = (opcode >> 6) & 0x3f;
+  dst = opcode & 0x3f;
+
+  for (i = 0; i < pdp11_num_opcodes; i++)
+    {
+#define OP pdp11_opcodes[i]
+      if ((opcode & OP.mask) == OP.opcode)
+	switch (OP.type)
+	  {
+	  case PDP11_OPCODE_NO_OPS:
+	    FPRINTF (F, OP.name);
+	    break;
+	  case PDP11_OPCODE_REG:
+	    FPRINTF (F, OP.name);
+	    FPRINTF (F, AFTER_INSTRUCTION);
+	    print_reg (dst, info);
+	    break;
+	  case PDP11_OPCODE_OP:
+	    FPRINTF (F, OP.name);
+	    FPRINTF (F, AFTER_INSTRUCTION);
+	    if (strcmp (OP.name, "jmp") == 0)
+	      dst |= JUMP;
+	    if (print_operand (&memaddr, dst, info) < 0)
+	      return -1;
+	    break;
+	  case PDP11_OPCODE_REG_OP:
+	    FPRINTF (F, OP.name);
+	    FPRINTF (F, AFTER_INSTRUCTION);
+	    print_reg (src, info);
+	    FPRINTF (F, OPERAND_SEPARATOR);
+	    if (strcmp (OP.name, "jsr") == 0)
+	      dst |= JUMP;
+	    if (print_operand (&memaddr, dst, info) < 0)
+	      return -1;
+	    break;
+	  case PDP11_OPCODE_REG_OP_REV:
+	    FPRINTF (F, OP.name);
+	    FPRINTF (F, AFTER_INSTRUCTION);
+	    if (print_operand (&memaddr, dst, info) < 0)
+	      return -1;
+	    FPRINTF (F, OPERAND_SEPARATOR);
+	    print_reg (src, info);
+	    break;
+	  case PDP11_OPCODE_AC_OP:
+	    {
+	      int ac = (opcode & 0xe0) >> 6;
+	      FPRINTF (F, OP.name);
+	      FPRINTF (F, AFTER_INSTRUCTION);
+	      print_freg (ac, info);
+	      FPRINTF (F, OPERAND_SEPARATOR);
+	      if (print_operand (&memaddr, dst, info) < 0)
+		return -1;
+	      break;
+	    }
+	  case PDP11_OPCODE_OP_OP:
+	    FPRINTF (F, OP.name);
+	    FPRINTF (F, AFTER_INSTRUCTION);
+	    if (print_operand (&memaddr, src, info) < 0)
+	      return -1;
+	    FPRINTF (F, OPERAND_SEPARATOR);
+	    if (print_operand (&memaddr, dst, info) < 0)
+	      return -1;
+	    break;
+	  case PDP11_OPCODE_DISPL:
+	    {
+	      int displ = (opcode & 0xff) << 8;
+	      bfd_vma address = memaddr + (sign_extend (displ) >> 7);
+	      FPRINTF (F, OP.name);
+	      FPRINTF (F, AFTER_INSTRUCTION);
+	      (*info->print_address_func) (address, info);
+	      break;
+	    }
+	  case PDP11_OPCODE_REG_DISPL:
+	    {
+	      int displ = (opcode & 0x3f) << 10;
+	      bfd_vma address = memaddr + (sign_extend (displ) >> 9);
+	      FPRINTF (F, OP.name);
+	      FPRINTF (F, AFTER_INSTRUCTION);
+	      print_reg (src, info);
+	      FPRINTF (F, OPERAND_SEPARATOR);
+	      (*info->print_address_func) (address, info);
+	      break;
+	    }
+	  case PDP11_OPCODE_IMM8:
+	    {
+	      int code = opcode & 0xff;
+	      FPRINTF (F, OP.name);
+	      FPRINTF (F, AFTER_INSTRUCTION);
+	      FPRINTF (F, "%o", code);
+	      break;
+	    }
+	  case PDP11_OPCODE_IMM6:
+	    {
+	      int code = opcode & 0x3f;
+	      FPRINTF (F, OP.name);
+	      FPRINTF (F, AFTER_INSTRUCTION);
+	      FPRINTF (F, "%o", code);
+	      break;
+	    }
+	  case PDP11_OPCODE_IMM3:
+	    {
+	      int code = opcode & 7;
+	      FPRINTF (F, OP.name);
+	      FPRINTF (F, AFTER_INSTRUCTION);
+	      FPRINTF (F, "%o", code);
+	      break;
+	    }
+	  default:
+	    /* TODO: is this a proper way of signalling an error? */
+	    FPRINTF (F, "<internal error: unrecognized instruction type>");
+	    return -1;
+	  }
+#undef OP
+    }
+
+  return memaddr - start_memaddr;
+}

opcodes/pdp11-opc.c

@@ -0,0 +1,245 @@
+/* Opcode table for PDP-11.
+   Copyright 2001 Free Software Foundation, Inc.
+
+This file is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#include "opcode/pdp11.h"
+
+const struct pdp11_opcode pdp11_opcodes[] =
+{
+  /* name,	pattern, mask,	opcode type,		insn type,    alias */
+  { "halt",	0x0000,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "wait",	0x0001,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "rti",	0x0002,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "bpt",	0x0003,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "iot",	0x0004,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "reset",	0x0005,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "rtt",	0x0006,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_LEIS },
+  { "mfpt",	0x0007,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_MFPT },
+  { "jmp",	0x0040,	0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "rts",	0x0080,	0xfff8, PDP11_OPCODE_REG,	PDP11_BASIC },
+  { "",		0x0088, 0xfff8, PDP11_OPCODE_ILLEGAL,	PDP11_NONE },
+  { "",		0x0090, 0xfff8, PDP11_OPCODE_ILLEGAL,	PDP11_NONE },
+  { "spl",	0x0098,	0xfff8, PDP11_OPCODE_IMM3,	PDP11_SPL },
+  { "nop",	0x00a0,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "clc",	0x00a1,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "clv",	0x00a2,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "cl_3",	0x00a3,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "clz",	0x00a4,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "cl_5",	0x00a5,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "cl_6",	0x00a6,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "cl_7",	0x00a7,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "cln",	0x00a8,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "cl_9",	0x00a9,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "cl_a",	0x00aa,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "cl_b",	0x00ab,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "cl_c",	0x00ac,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "cl_d",	0x00ad,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "cl_e",	0x00ae,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "ccc",	0x00af,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "se_0",	0x00b0,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "sec",	0x00a1,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "sev",	0x00b2,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "se_3",	0x00b3,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "sez",	0x00b4,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "se_5",	0x00b5,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "se_6",	0x00b6,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "se_7",	0x00b7,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "sen",	0x00b8,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "se_9",	0x00b9,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "se_a",	0x00ba,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "se_b",	0x00bb,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "se_c",	0x00bc,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "se_d",	0x00bd,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "se_e",	0x00be,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "scc",	0x00bf,	0xffff, PDP11_OPCODE_NO_OPS,	PDP11_BASIC },
+  { "swab",	0x00c0,	0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "br",	0x0100, 0xff00, PDP11_OPCODE_DISPL,	PDP11_BASIC },
+  { "bne",	0x0200, 0xff00, PDP11_OPCODE_DISPL,	PDP11_BASIC },
+  { "beq",	0x0300, 0xff00, PDP11_OPCODE_DISPL,	PDP11_BASIC },
+  { "bge",	0x0400, 0xff00, PDP11_OPCODE_DISPL,	PDP11_BASIC },
+  { "blt",	0x0500, 0xff00, PDP11_OPCODE_DISPL,	PDP11_BASIC },
+  { "bgt",	0x0600, 0xff00, PDP11_OPCODE_DISPL,	PDP11_BASIC },
+  { "ble",	0x0700, 0xff00, PDP11_OPCODE_DISPL,	PDP11_BASIC },
+  { "jsr",	0x0800, 0xfe00, PDP11_OPCODE_REG_OP,	PDP11_BASIC },
+  { "clr",	0x0a00, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "com",	0x0a40, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "inc",	0x0a80, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "dec",	0x0ac0, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "neg",	0x0b00, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "adc",	0x0b40, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "sbc",	0x0b80, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "tst",	0x0bc0, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "ror",	0x0c00, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "rol",	0x0c40, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "asr",	0x0c80, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "asl",	0x0cc0, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "mark",	0x0d00, 0xffc0, PDP11_OPCODE_OP,	PDP11_LEIS },
+  { "mfpi",	0x0d40, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "mtpi",	0x0d80, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "sxt",	0x0dc0, 0xffc0, PDP11_OPCODE_OP,	PDP11_LEIS },
+  { "csm",	0x0e00, 0xffc0, PDP11_OPCODE_OP,	PDP11_CSM },
+  { "tstset",	0x0e40, 0xffc0, PDP11_OPCODE_OP,	PDP11_MPROC },
+  { "wrtlck",	0x0e80, 0xffc0, PDP11_OPCODE_OP,	PDP11_MPROC },
+/*{ "",		0x0ec0, 0xffe0, PDP11_OPCODE_ILLEGAL,	PDP11_NONE },*/
+  { "mov",	0x1000, 0xf000, PDP11_OPCODE_OP_OP,	PDP11_BASIC },
+  { "cmp",	0x2000, 0xf000, PDP11_OPCODE_OP_OP,	PDP11_BASIC },
+  { "bit",	0x3000, 0xf000, PDP11_OPCODE_OP_OP,	PDP11_BASIC },
+  { "bic",	0x4000, 0xf000, PDP11_OPCODE_OP_OP,	PDP11_BASIC },
+  { "bis",	0x5000, 0xf000, PDP11_OPCODE_OP_OP,	PDP11_BASIC },
+  { "add",	0x6000, 0xf000, PDP11_OPCODE_OP_OP,	PDP11_BASIC },
+  { "mul",	0x7000, 0xfe00, PDP11_OPCODE_REG_OP_REV,PDP11_EIS },
+  { "div",	0x7200, 0xfe00, PDP11_OPCODE_REG_OP_REV,PDP11_EIS },
+  { "ash",	0x7400, 0xfe00, PDP11_OPCODE_REG_OP_REV,PDP11_EIS },
+  { "ashc",	0x7600, 0xfe00, PDP11_OPCODE_REG_OP_REV,PDP11_EIS },
+  { "xor",	0x7800, 0xfe00, PDP11_OPCODE_REG_OP,	PDP11_LEIS },
+  { "fadd",	0x7a00, 0xfff8, PDP11_OPCODE_REG,	PDP11_FIS },
+  { "fsub",	0x7a08, 0xfff8, PDP11_OPCODE_REG,	PDP11_FIS },
+  { "fmul",	0x7a10, 0xfff8, PDP11_OPCODE_REG,	PDP11_FIS },
+  { "fdiv",	0x7a18, 0xfff8, PDP11_OPCODE_REG,	PDP11_FIS },
+/*{ "",		0x7a20, 0xffe0, PDP11_OPCODE_ILLEGAL,	PDP11_NONE },*/
+/*{ "",		0x7a40, 0xffc0, PDP11_OPCODE_ILLEGAL,	PDP11_NONE },*/
+/*{ "",		0x7a80, 0xff80, PDP11_OPCODE_ILLEGAL,	PDP11_NONE },*/
+/*{ "",		0x7b00, 0xffe0, PDP11_OPCODE_ILLEGAL,	PDP11_NONE },*/
+  { "l2dr",	0x7c10, 0xfff8, PDP11_OPCODE_REG,	PDP11_CIS },/*l2d*/
+  { "movc",	0x7c18, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "movrc",	0x7c19, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "movtc",	0x7c1a, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "locc",	0x7c20, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "skpc",	0x7c21, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "scanc",	0x7c22, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "spanc",	0x7c23, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "cmpc",	0x7c24, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "matc",	0x7c25, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "addn",	0x7c28, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "subn",	0x7c29, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "cmpn",	0x7c2a, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "cvtnl",	0x7c2b, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "cvtpn",	0x7c2c, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "cvtnp",	0x7c2d, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "ashn",	0x7c2e, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "cvtln",	0x7c2f, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "l3dr",	0x7c30, 0xfff8, PDP11_OPCODE_REG,	PDP11_CIS },/*l3d*/
+  { "addp",	0x7c38, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "subp",	0x7c39, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "cmpp",	0x7c3a, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "cvtpl",	0x7c3b, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "mulp",	0x7c3c, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "divp",	0x7c3d, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "ashp",	0x7c3e, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "cvtlp",	0x7c3f, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "movci",	0x7c58, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "movrci",	0x7c59, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "movtci",	0x7c5a, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "locci",	0x7c60, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "skpci",	0x7c61, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "scanci",	0x7c62, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "spanci",	0x7c63, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "cmpci",	0x7c64, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "matci",	0x7c65, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "addni",	0x7c68, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "subni",	0x7c69, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "cmpni",	0x7c6a, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "cvtnli",	0x7c6b, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "cvtpni",	0x7c6c, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "cvtnpi",	0x7c6d, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "ashni",	0x7c6e, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "cvtlni",	0x7c6f, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "addpi",	0x7c78, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "subpi",	0x7c79, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "cmppi",	0x7c7a, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "cvtpli",	0x7c7b, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "mulpi",	0x7c7c, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "divpi",	0x7c7d, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "ashpi",	0x7c7e, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "cvtlpi",	0x7c7f, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_CIS },
+  { "med",	0x7d80, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_UCODE },
+  { "xfc",	0x7dc0, 0xffc0, PDP11_OPCODE_IMM6,	PDP11_UCODE },
+  { "sob",	0x7e00, 0xfe00, PDP11_OPCODE_REG_DISPL,	PDP11_LEIS },
+  { "bpl",	0x8000, 0xff00, PDP11_OPCODE_DISPL,	PDP11_BASIC },
+  { "bmi",	0x8100, 0xff00, PDP11_OPCODE_DISPL,	PDP11_BASIC },
+  { "bhi",	0x8200, 0xff00, PDP11_OPCODE_DISPL,	PDP11_BASIC },
+  { "blos",	0x8300, 0xff00, PDP11_OPCODE_DISPL,	PDP11_BASIC },
+  { "bvc",	0x8400, 0xff00, PDP11_OPCODE_DISPL,	PDP11_BASIC },
+  { "bvs",	0x8500, 0xff00, PDP11_OPCODE_DISPL,	PDP11_BASIC },
+  { "bcc",	0x8600, 0xff00, PDP11_OPCODE_DISPL,	PDP11_BASIC },/*bhis*/
+  { "bcs",	0x8700, 0xff00, PDP11_OPCODE_DISPL,	PDP11_BASIC },/*blo*/
+  { "emt",	0x8800, 0xff00, PDP11_OPCODE_IMM8,	PDP11_BASIC },
+  { "sys",	0x8900, 0xff00, PDP11_OPCODE_IMM8,	PDP11_BASIC },/*trap*/
+  { "clrb",	0x8a00, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "comb",	0x8a40, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "incb",	0x8a80, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "decb",	0x8ac0, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "negb",	0x8b00, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "adcb",	0x8b40, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "sbcb",	0x8b80, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "tstb",	0x8bc0, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "rorb",	0x8c00, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "rolb",	0x8c40, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "asrb",	0x8c80, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "aslb",	0x8cc0, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "mtps",	0x8d00, 0xffc0, PDP11_OPCODE_OP,	PDP11_MXPS },
+  { "mfpd",	0x8d40, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "mtpd",	0x8d80, 0xffc0, PDP11_OPCODE_OP,	PDP11_BASIC },
+  { "mfps",	0x8dc0, 0xffc0, PDP11_OPCODE_OP,	PDP11_MXPS },
+  { "movb",	0x9000, 0xf000, PDP11_OPCODE_OP_OP,	PDP11_BASIC },
+  { "cmpb",	0xa000, 0xf000, PDP11_OPCODE_OP_OP,	PDP11_BASIC },
+  { "bitb",	0xb000, 0xf000, PDP11_OPCODE_OP_OP,	PDP11_BASIC },
+  { "bicb",	0xc000, 0xf000, PDP11_OPCODE_OP_OP,	PDP11_BASIC },
+  { "bisb",	0xd000, 0xf000, PDP11_OPCODE_OP_OP,	PDP11_BASIC },
+  { "sub",	0xe000, 0xf000, PDP11_OPCODE_OP_OP,	PDP11_BASIC },
+  { "cfcc",	0xf000, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_FPP },
+  { "setf",	0xf001, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_FPP },
+  { "seti",	0xf002, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_FPP },
+  { "ldub",	0xf003, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_UCODE },
+  /* fpp trap	0xf004..0xf008 */
+  { "setd",	0xf009, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_FPP },
+  { "setl",	0xf00a, 0xffff, PDP11_OPCODE_NO_OPS,	PDP11_FPP },
+  /* fpp trap	0xf00b..0xf03f */
+  { "ldfps",	0xf040, 0xffc0, PDP11_OPCODE_OP,	PDP11_FPP },
+  { "stfps",	0xf080, 0xffc0, PDP11_OPCODE_OP,	PDP11_FPP },
+  { "stst",	0xf0c0, 0xffc0, PDP11_OPCODE_OP,	PDP11_FPP },
+  { "clrf",	0xf100, 0xffc0, PDP11_OPCODE_OP,	PDP11_FPP },
+  { "tstf",	0xf140, 0xffc0, PDP11_OPCODE_OP,	PDP11_FPP },
+  { "absf",	0xf180, 0xffc0, PDP11_OPCODE_OP,	PDP11_FPP },
+  { "negf",	0xf1c0, 0xffc0, PDP11_OPCODE_OP,	PDP11_FPP },
+  { "mulf",	0xf200, 0xff00, PDP11_OPCODE_AC_OP,	PDP11_FPP },
+  { "modf",	0xf300, 0xff00, PDP11_OPCODE_AC_OP,	PDP11_FPP },
+  { "addf",	0xf400, 0xff00, PDP11_OPCODE_AC_OP,	PDP11_FPP },
+  { "ldf",	0xf500, 0xff00, PDP11_OPCODE_AC_OP,	PDP11_FPP },/*movif*/
+  { "subf",	0xf600, 0xff00, PDP11_OPCODE_AC_OP,	PDP11_FPP },
+  { "cmpf",	0xf700, 0xff00, PDP11_OPCODE_AC_OP,	PDP11_FPP },
+  { "stf",	0xf800, 0xff00, PDP11_OPCODE_AC_OP,	PDP11_FPP },/*movfi*/
+  { "divf",	0xf900, 0xff00, PDP11_OPCODE_AC_OP,	PDP11_FPP },
+  { "stexp",	0xfa00, 0xff00, PDP11_OPCODE_AC_OP,	PDP11_FPP },
+  { "stcfi",	0xfb00, 0xff00, PDP11_OPCODE_AC_OP,	PDP11_FPP },
+  { "stcff",	0xfc00, 0xff00, PDP11_OPCODE_AC_OP,	PDP11_FPP },/* ? */
+  { "ldexp",	0xfd00, 0xff00, PDP11_OPCODE_AC_OP,	PDP11_FPP },
+  { "ldcif",	0xfe00, 0xff00, PDP11_OPCODE_AC_OP,	PDP11_FPP },
+  { "ldcff",	0xff00, 0xff00, PDP11_OPCODE_AC_OP,	PDP11_FPP },/* ? */
+};
+
+const struct pdp11_opcode pdp11_aliases[] =
+{
+  /* name,	pattern, mask,	opcode type,		insn type */
+  { "l2d",	0x7c10, 0xfff8, PDP11_OPCODE_REG,	PDP11_CIS },
+  { "l3d",	0x7c30, 0xfff8, PDP11_OPCODE_REG,	PDP11_CIS },
+  { "bhis",	0x8600, 0xff00, PDP11_OPCODE_DISPL,	PDP11_BASIC },
+  { "blo",	0x8700, 0xff00, PDP11_OPCODE_DISPL,	PDP11_BASIC },
+  { "trap",	0x8900, 0xff00, PDP11_OPCODE_IMM8,	PDP11_BASIC },
+};
+
+const int pdp11_num_opcodes = sizeof pdp11_opcodes / sizeof pdp11_opcodes[0];
+const int pdp11_num_aliases = sizeof pdp11_aliases / sizeof pdp11_aliases[0];

opcodes/po/POTFILES.in

@@ -69,6 +69,8 @@ mips16-opc.c
 mips-dis.c
 mips-opc.c
 ns32k-dis.c
+pdp11-dis.c
+pdp11-opc.c
 pj-dis.c
 pj-opc.c
 ppc-dis.c

opcodes/po/opcodes.pot

@@ -6,7 +6,7 @@
 msgid ""
 msgstr ""
 "Project-Id-Version: PACKAGE VERSION\n"
-"POT-Creation-Date: 2001-02-09 16:04-0800\n"
+"POT-Creation-Date: 2001-02-18 14:44-0800\n"
 "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
 "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
 "Language-Team: LANGUAGE <LL@li.org>\n"
@@ -186,7 +186,7 @@ msgstr ""
 msgid "%02x\t\t*unknown*"
 msgstr ""
 
-#: i386-dis.c:2741
+#: i386-dis.c:2742
 msgid "<internal disassembler error>"
 msgstr ""