Johns release
This commit is contained in:
K. Richard Pixley
parent
bd5635a1e2
commit
dd3b648e8b
246 changed files with 59132 additions and 0 deletions
465
gdb/sparc-pinsn.c
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465
gdb/sparc-pinsn.c
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/* Disassembler for the sparc.
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Copyright (C) 1989 Free Software Foundation, Inc.
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This file is part of GDB, the GNU disassembler.
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GDB is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 1, or (at your option)
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any later version.
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GDB is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GDB; see the file COPYING. If not, write to
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the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
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#include <stdio.h>
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#include "defs.h"
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#include "param.h"
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#include "symtab.h"
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#include "sparc-opcode.h"
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#include "gdbcore.h"
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#include "string.h"
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#include "target.h"
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extern void qsort ();
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extern char *reg_names[];
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#define freg_names (®_names[4 * 8])
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union sparc_insn
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{
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unsigned long int code;
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struct
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{
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unsigned int OP:2;
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#define op ldst.OP
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unsigned int RD:5;
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#define rd ldst.RD
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unsigned int op3:6;
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unsigned int RS1:5;
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#define rs1 ldst.RS1
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unsigned int i:1;
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unsigned int ASI:8;
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#define asi ldst.ASI
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unsigned int RS2:5;
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#define rs2 ldst.RS2
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#define shcnt rs2
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} ldst;
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struct
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{
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unsigned int OP:2, RD:5, op3:6, RS1:5, i:1;
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unsigned int IMM13:13;
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#define imm13 IMM13.IMM13
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} IMM13;
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struct
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{
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unsigned int OP:2;
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unsigned int a:1;
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unsigned int cond:4;
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unsigned int op2:3;
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unsigned int DISP22:22;
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#define disp22 branch.DISP22
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} branch;
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#define imm22 disp22
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struct
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{
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unsigned int OP:2;
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unsigned int DISP30:30;
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#define disp30 call.DISP30
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} call;
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};
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/* Nonzero if INSN is the opcode for a delayed branch. */
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static int
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is_delayed_branch (insn)
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union sparc_insn insn;
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{
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unsigned int i;
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for (i = 0; i < NUMOPCODES; ++i)
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{
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const struct sparc_opcode *opcode = &sparc_opcodes[i];
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if ((opcode->match & insn.code) == opcode->match
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&& (opcode->lose & insn.code) == 0)
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return (opcode->flags & F_DELAYED);
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}
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return 0;
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}
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static int opcodes_sorted = 0;
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/* Print one instruction from MEMADDR on STREAM. */
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int
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print_insn (memaddr, stream)
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CORE_ADDR memaddr;
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FILE *stream;
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{
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union sparc_insn insn;
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register unsigned int i;
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if (!opcodes_sorted)
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{
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static int compare_opcodes ();
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qsort ((char *) sparc_opcodes, NUMOPCODES,
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sizeof (sparc_opcodes[0]), compare_opcodes);
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opcodes_sorted = 1;
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}
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read_memory (memaddr, &insn, sizeof (insn));
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for (i = 0; i < NUMOPCODES; ++i)
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{
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const struct sparc_opcode *opcode = &sparc_opcodes[i];
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if ((opcode->match & insn.code) == opcode->match
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&& (opcode->lose & insn.code) == 0)
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{
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/* Nonzero means that we have found an instruction which has
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the effect of adding or or'ing the imm13 field to rs1. */
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int imm_added_to_rs1 = 0;
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/* Nonzero means that we have found a plus sign in the args
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field of the opcode table. */
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int found_plus = 0;
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/* Do we have an 'or' instruction where rs1 is the same
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as rsd, and which has the i bit set? */
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if (opcode->match == 0x80102000
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&& insn.rs1 == insn.rd)
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imm_added_to_rs1 = 1;
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if (insn.rs1 != insn.rd
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&& strchr (opcode->args, 'r') != 0)
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/* Can't do simple format if source and dest are different. */
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continue;
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fputs_filtered (opcode->name, stream);
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{
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register const char *s;
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if (opcode->args[0] != ',')
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fputs_filtered (" ", stream);
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for (s = opcode->args; *s != '\0'; ++s)
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{
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if (*s == ',')
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{
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fputs_filtered (",", stream);
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++s;
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if (*s == 'a')
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{
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fputs_filtered ("a", stream);
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++s;
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}
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fputs_filtered (" ", stream);
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}
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switch (*s)
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{
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case '+':
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found_plus = 1;
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/* note fall-through */
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default:
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fprintf_filtered (stream, "%c", *s);
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break;
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case '#':
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fputs_filtered ("0", stream);
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break;
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#define reg(n) fprintf_filtered (stream, "%%%s", reg_names[n])
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case '1':
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case 'r':
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reg (insn.rs1);
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break;
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case '2':
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reg (insn.rs2);
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break;
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case 'd':
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reg (insn.rd);
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break;
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#undef reg
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#define freg(n) fprintf_filtered (stream, "%%%s", freg_names[n])
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case 'e':
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freg (insn.rs1);
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break;
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case 'f':
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freg (insn.rs2);
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break;
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case 'g':
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freg (insn.rd);
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break;
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#undef freg
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#define creg(n) fprintf_filtered (stream, "%%c%u", (unsigned int) (n))
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case 'b':
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creg (insn.rs1);
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break;
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case 'c':
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creg (insn.rs2);
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break;
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case 'D':
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creg (insn.rd);
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break;
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#undef creg
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case 'h':
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fprintf_filtered (stream, "%%hi(%#x)",
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(int) insn.imm22 << 10);
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break;
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case 'i':
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{
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/* We cannot trust the compiler to sign-extend
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when extracting the bitfield, hence the shifts. */
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int imm = ((int) insn.imm13 << 19) >> 19;
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/* Check to see whether we have a 1+i, and take
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note of that fact.
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Note: because of the way we sort the table,
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we will be matching 1+i rather than i+1,
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so it is OK to assume that i is after +,
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not before it. */
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if (found_plus)
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imm_added_to_rs1 = 1;
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if (imm <= 9)
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fprintf_filtered (stream, "%d", imm);
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else
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fprintf_filtered (stream, "%#x", imm);
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}
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break;
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case 'L':
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print_address ((CORE_ADDR) memaddr + insn.disp30 * 4,
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stream);
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break;
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case 'l':
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if ((insn.code >> 22) == 0)
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/* Special case for `unimp'. Don't try to turn
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it's operand into a function offset. */
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fprintf_filtered (stream, "%#x",
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(int) (((int) insn.disp22 << 10) >> 10));
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else
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/* We cannot trust the compiler to sign-extend
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when extracting the bitfield, hence the shifts. */
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print_address ((CORE_ADDR)
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(memaddr
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+ (((int) insn.disp22 << 10) >> 10) * 4),
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stream);
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break;
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case 'A':
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fprintf_filtered (stream, "(%d)", (int) insn.asi);
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break;
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case 'C':
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fputs_filtered ("%csr", stream);
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break;
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case 'F':
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fputs_filtered ("%fsr", stream);
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break;
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case 'p':
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fputs_filtered ("%psr", stream);
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break;
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case 'q':
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fputs_filtered ("%fq", stream);
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break;
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case 'Q':
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fputs_filtered ("%cq", stream);
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break;
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case 't':
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fputs_filtered ("%tbr", stream);
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break;
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case 'w':
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fputs_filtered ("%wim", stream);
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break;
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case 'y':
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fputs_filtered ("%y", stream);
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break;
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}
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}
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}
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/* If we are adding or or'ing something to rs1, then
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check to see whether the previous instruction was
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a sethi to the same register as in the sethi.
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If so, attempt to print the result of the add or
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or (in this context add and or do the same thing)
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and its symbolic value. */
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if (imm_added_to_rs1)
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{
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union sparc_insn prev_insn;
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int errcode;
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errcode = target_read_memory (memaddr - 4,
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(char *)&prev_insn, sizeof (prev_insn));
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if (errcode == 0)
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{
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/* If it is a delayed branch, we need to look at the
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instruction before the delayed branch. This handles
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sequences such as
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sethi %o1, %hi(_foo), %o1
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call _printf
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or %o1, %lo(_foo), %o1
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*/
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if (is_delayed_branch (prev_insn))
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errcode = target_read_memory
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(memaddr - 8, (char *)&prev_insn, sizeof (prev_insn));
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}
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/* If there was a problem reading memory, then assume
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the previous instruction was not sethi. */
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if (errcode == 0)
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{
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/* Is it sethi to the same register? */
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if ((prev_insn.code & 0xc1c00000) == 0x01000000
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&& prev_insn.rd == insn.rs1)
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{
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fprintf_filtered (stream, "\t! ");
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/* We cannot trust the compiler to sign-extend
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when extracting the bitfield, hence the shifts. */
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print_address (((int) prev_insn.imm22 << 10)
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}
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}
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}
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return sizeof (insn);
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}
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}
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printf_filtered ("%#8x", insn.code);
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return sizeof (insn);
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}
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/* Compare opcodes A and B. */
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static int
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compare_opcodes (a, b)
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char *a, *b;
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{
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struct sparc_opcode *op0 = (struct sparc_opcode *) a;
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struct sparc_opcode *op1 = (struct sparc_opcode *) b;
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unsigned long int match0 = op0->match, match1 = op1->match;
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unsigned long int lose0 = op0->lose, lose1 = op1->lose;
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register unsigned int i;
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/* If a bit is set in both match and lose, there is something
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wrong with the opcode table. */
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if (match0 & lose0)
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{
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fprintf (stderr, "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n",
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op0->name, match0, lose0);
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op0->lose &= ~op0->match;
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lose0 = op0->lose;
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}
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if (match1 & lose1)
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{
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fprintf (stderr, "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n",
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op1->name, match1, lose1);
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op1->lose &= ~op1->match;
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lose1 = op1->lose;
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}
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/* Because the bits that are variable in one opcode are constant in
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another, it is important to order the opcodes in the right order. */
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for (i = 0; i < 32; ++i)
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{
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unsigned long int x = 1 << i;
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int x0 = (match0 & x) != 0;
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int x1 = (match1 & x) != 0;
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if (x0 != x1)
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return x1 - x0;
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}
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for (i = 0; i < 32; ++i)
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{
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unsigned long int x = 1 << i;
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int x0 = (lose0 & x) != 0;
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int x1 = (lose1 & x) != 0;
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if (x0 != x1)
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return x1 - x0;
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}
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/* They are functionally equal. So as long as the opcode table is
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valid, we can put whichever one first we want, on aesthetic grounds. */
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/* Our first aesthetic ground is that aliases defer to real insns. */
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{
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int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS);
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if (alias_diff != 0)
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/* Put the one that isn't an alias first. */
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return alias_diff;
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}
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/* Except for the above aliases, two "identical" instructions had
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better have the same opcode. This is a sanity check on the table. */
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if (0 != strcmp (op0->name, op1->name))
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fprintf (stderr, "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n",
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op0->name, op1->name);
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/* Fewer arguments are preferred. */
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{
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int length_diff = strlen (op0->args) - strlen (op1->args);
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if (length_diff != 0)
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/* Put the one with fewer arguments first. */
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return length_diff;
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}
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/* Put 1+i before i+1. */
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{
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char *p0 = (char *) strchr(op0->args, '+');
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char *p1 = (char *) strchr(op1->args, '+');
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if (p0 && p1)
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{
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/* There is a plus in both operands. Note that a plus
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sign cannot be the first character in args,
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so the following [-1]'s are valid. */
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if (p0[-1] == 'i' && p1[1] == 'i')
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/* op0 is i+1 and op1 is 1+i, so op1 goes first. */
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return 1;
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if (p0[1] == 'i' && p1[-1] == 'i')
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/* op0 is 1+i and op1 is i+1, so op0 goes first. */
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return -1;
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}
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}
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/* They are, as far as we can tell, identical.
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Since qsort may have rearranged the table partially, there is
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no way to tell which one was first in the opcode table as
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written, so just say there are equal. */
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return 0;
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}
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