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bfd/binutils: add support for RISC-V CSRs in core files

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Adds support for including RISC-V control and status registers into
core files.

The value for the define NT_RISCV_CSR is set to 0x900, this
corresponds to a patch I have proposed for the Linux kernel here:

  http://lists.infradead.org/pipermail/linux-riscv/2020-December/003910.html

As I have not yet heard if the above patch will be accepted into the
kernel or not I have set the note name string to "GDB", and the note
type to NT_RISCV_CSR.

This means that if the above patch is rejected from the kernel, and
the note type number 0x900 is assigned to some other note type, we
will still be able to distinguish between the GDB produced
NT_RISCV_CSR, and the kernel produced notes, where the name would be
set to "CORE".

bfd/ChangeLog:

	* elf-bfd.h (elfcore_write_riscv_csr): Declare.
	* elf.c (elfcore_grok_riscv_csr): New function.
	(elfcore_grok_note): Handle NT_RISCV_CSR.
	(elfcore_write_riscv_csr): New function.
	(elfcore_write_register_note): Handle '.reg-riscv-csr'.

binutils/ChangeLog:

	* readelf.c (get_note_type): Handle NT_RISCV_CSR.

include/ChangeLog:

	* elf/common.h (NT_RISCV_CSR): Define.
This commit is contained in:
Andrew Burgess 2020-11-27 14:04:16 +00:00
parent fb8f3fc0c3
commit db6092f3ae
7 changed files with 60 additions and 0 deletions
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5
binutils/ChangeLog
View file

@ -1,3 +1,8 @@
2021-03-05 Craig Blackmore <craig.blackmore@embecosm.com>
Andrew Burgess <andrew.burgess@embecosm.com>
* readelf.c (get_note_type): Handle NT_RISCV_CSR.
2021-03-05 Craig Blackmore <craig.blackmore@embecosm.com>
Andrew Burgess <andrew.burgess@embecosm.com>

2
binutils/readelf.c
View file

@ -18577,6 +18577,8 @@ get_note_type (Filedata * filedata, unsigned e_type)
return _("NT_ARM_HW_WATCH (AArch hardware watchpoint registers)");
case NT_ARC_V2:
return _("NT_ARC_V2 (ARC HS accumulator/extra registers)");
case NT_RISCV_CSR:
return _("NT_RISCV_CSR (RISC-V control and status registers)");
case NT_PSTATUS:
return _("NT_PSTATUS (pstatus structure)");
case NT_FPREGS: