RISC-V: Add vector permutation instructions for T-Head VECTOR vendor extension
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds permutation instructions for the "XTheadVector" extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu> gas/ChangeLog: * testsuite/gas/riscv/x-thead-vector.d: Add tests for permutation instructions. * testsuite/gas/riscv/x-thead-vector.s: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_VMVXS): New. opcodes/ChangeLog: * riscv-opc.c: Likewise.
This commit is contained in:
Jin Ma
Nelson Chu
parent
832cdeeccb
commit
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4 changed files with 93 additions and 0 deletions
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@ -1618,3 +1618,33 @@ Disassembly of section .text:
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[ ]+[0-9a-f]+:[ ]+58812257[ ]+th.vmsof.m[ ]+v4,v8,v0.t
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[ ]+[0-9a-f]+:[ ]+58882257[ ]+th.viota.m[ ]+v4,v8,v0.t
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[ ]+[0-9a-f]+:[ ]+5808a257[ ]+th.vid.v[ ]+v4,v0.t
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[ ]+[0-9a-f]+:[ ]+32c02557[ ]+th.vmv.x.s[ ]+a0,v12
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[ ]+[0-9a-f]+:[ ]+32c62557[ ]+th.vext.x.v[ ]+a0,v12,a2
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[ ]+[0-9a-f]+:[ ]+36056257[ ]+th.vmv.s.x[ ]+v4,a0
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[ ]+[0-9a-f]+:[ ]+32801557[ ]+th.vfmv.f.s[ ]+fa0,v8
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[ ]+[0-9a-f]+:[ ]+3605d257[ ]+th.vfmv.s.f[ ]+v4,fa1
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[ ]+[0-9a-f]+:[ ]+3a85c257[ ]+th.vslideup.vx[ ]+v4,v8,a1
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[ ]+[0-9a-f]+:[ ]+3a803257[ ]+th.vslideup.vi[ ]+v4,v8,0
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[ ]+[0-9a-f]+:[ ]+3a8fb257[ ]+th.vslideup.vi[ ]+v4,v8,31
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[ ]+[0-9a-f]+:[ ]+3e85c257[ ]+th.vslidedown.vx[ ]+v4,v8,a1
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[ ]+[0-9a-f]+:[ ]+3e803257[ ]+th.vslidedown.vi[ ]+v4,v8,0
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[ ]+[0-9a-f]+:[ ]+3e8fb257[ ]+th.vslidedown.vi[ ]+v4,v8,31
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[ ]+[0-9a-f]+:[ ]+3885c257[ ]+th.vslideup.vx[ ]+v4,v8,a1,v0.t
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[ ]+[0-9a-f]+:[ ]+38803257[ ]+th.vslideup.vi[ ]+v4,v8,0,v0.t
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[ ]+[0-9a-f]+:[ ]+388fb257[ ]+th.vslideup.vi[ ]+v4,v8,31,v0.t
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[ ]+[0-9a-f]+:[ ]+3c85c257[ ]+th.vslidedown.vx[ ]+v4,v8,a1,v0.t
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[ ]+[0-9a-f]+:[ ]+3c803257[ ]+th.vslidedown.vi[ ]+v4,v8,0,v0.t
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[ ]+[0-9a-f]+:[ ]+3c8fb257[ ]+th.vslidedown.vi[ ]+v4,v8,31,v0.t
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[ ]+[0-9a-f]+:[ ]+3a85e257[ ]+th.vslide1up.vx[ ]+v4,v8,a1
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[ ]+[0-9a-f]+:[ ]+3e85e257[ ]+th.vslide1down.vx[ ]+v4,v8,a1
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[ ]+[0-9a-f]+:[ ]+3885e257[ ]+th.vslide1up.vx[ ]+v4,v8,a1,v0.t
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[ ]+[0-9a-f]+:[ ]+3c85e257[ ]+th.vslide1down.vx[ ]+v4,v8,a1,v0.t
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[ ]+[0-9a-f]+:[ ]+32860257[ ]+th.vrgather.vv[ ]+v4,v8,v12
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[ ]+[0-9a-f]+:[ ]+3285c257[ ]+th.vrgather.vx[ ]+v4,v8,a1
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[ ]+[0-9a-f]+:[ ]+32803257[ ]+th.vrgather.vi[ ]+v4,v8,0
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[ ]+[0-9a-f]+:[ ]+328fb257[ ]+th.vrgather.vi[ ]+v4,v8,31
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[ ]+[0-9a-f]+:[ ]+30860257[ ]+th.vrgather.vv[ ]+v4,v8,v12,v0.t
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[ ]+[0-9a-f]+:[ ]+3085c257[ ]+th.vrgather.vx[ ]+v4,v8,a1,v0.t
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[ ]+[0-9a-f]+:[ ]+30803257[ ]+th.vrgather.vi[ ]+v4,v8,0,v0.t
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[ ]+[0-9a-f]+:[ ]+308fb257[ ]+th.vrgather.vi[ ]+v4,v8,31,v0.t
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[ ]+[0-9a-f]+:[ ]+5e862257[ ]+th.vcompress.vm[ ]+v4,v8,v12
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@ -1686,3 +1686,41 @@
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th.vmsof.m v4, v8, v0.t
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th.viota.m v4, v8, v0.t
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th.vid.v v4, v0.t
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# Alias
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th.vmv.x.s a0, v12
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th.vext.x.v a0, v12, a2
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th.vmv.s.x v4, a0
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th.vfmv.f.s fa0, v8
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th.vfmv.s.f v4, fa1
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th.vslideup.vx v4, v8, a1
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th.vslideup.vi v4, v8, 0
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th.vslideup.vi v4, v8, 31
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th.vslidedown.vx v4, v8, a1
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th.vslidedown.vi v4, v8, 0
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th.vslidedown.vi v4, v8, 31
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th.vslideup.vx v4, v8, a1, v0.t
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th.vslideup.vi v4, v8, 0, v0.t
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th.vslideup.vi v4, v8, 31, v0.t
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th.vslidedown.vx v4, v8, a1, v0.t
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th.vslidedown.vi v4, v8, 0, v0.t
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th.vslidedown.vi v4, v8, 31, v0.t
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th.vslide1up.vx v4, v8, a1
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th.vslide1down.vx v4, v8, a1
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th.vslide1up.vx v4, v8, a1, v0.t
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th.vslide1down.vx v4, v8, a1, v0.t
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th.vrgather.vv v4, v8, v12
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th.vrgather.vx v4, v8, a1
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th.vrgather.vi v4, v8, 0
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th.vrgather.vi v4, v8, 31
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th.vrgather.vv v4, v8, v12, v0.t
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th.vrgather.vx v4, v8, a1, v0.t
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th.vrgather.vi v4, v8, 0, v0.t
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th.vrgather.vi v4, v8, 31, v0.t
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th.vcompress.vm v4, v8, v12
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@ -2959,6 +2959,16 @@
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#define MASK_TH_VIOTAM 0xfc0ff07f
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#define MATCH_TH_VIDV 0x5808a057
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#define MASK_TH_VIDV 0xfdfff07f
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#define MATCH_TH_VMVXS 0x32002057
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#define MASK_TH_VMVXS 0xfe0ff07f
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#define MATCH_TH_VEXTXV 0x32002057
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#define MASK_TH_VEXTXV 0xfe00707f
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#define MATCH_TH_VMVSX 0x36006057
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#define MASK_TH_VMVSX 0xfff0707f
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#define MATCH_TH_VFMVFS 0x32001057
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#define MASK_TH_VFMVFS 0xfe0ff07f
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#define MATCH_TH_VFMVSF 0x36005057
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#define MASK_TH_VFMVSF 0xfff0707f
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/* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
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#define MATCH_VT_MASKC 0x607b
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#define MASK_VT_MASKC 0xfe00707f
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@ -2879,6 +2879,21 @@ const struct riscv_opcode riscv_opcodes[] =
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{"th.vmsof.m", 0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VMSOFM, MASK_TH_VMSOFM, match_opcode, 0},
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{"th.viota.m", 0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VIOTAM, MASK_TH_VIOTAM, match_opcode, 0},
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{"th.vid.v", 0, INSN_CLASS_XTHEADVECTOR, "VdVm", MATCH_TH_VIDV, MASK_TH_VIDV, match_opcode, 0},
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{"th.vmv.x.s", 0, INSN_CLASS_XTHEADVECTOR, "d,Vt", MATCH_TH_VMVXS, MASK_TH_VMVXS, match_opcode, INSN_ALIAS},
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{"th.vext.x.v", 0, INSN_CLASS_XTHEADVECTOR, "d,Vt,s", MATCH_TH_VEXTXV, MASK_TH_VEXTXV, match_opcode, 0},
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{"th.vmv.s.x", 0, INSN_CLASS_XTHEADVECTOR, "Vd,s", MATCH_TH_VMVSX, MASK_TH_VMVSX, match_opcode, 0},
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{"th.vfmv.f.s", 0, INSN_CLASS_XTHEADVECTOR, "D,Vt", MATCH_TH_VFMVFS, MASK_TH_VFMVFS, match_opcode, 0},
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{"th.vfmv.s.f", 0, INSN_CLASS_XTHEADVECTOR, "Vd,S", MATCH_TH_VFMVSF, MASK_TH_VFMVSF, match_opcode, 0},
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{"th.vslideup.vx",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VSLIDEUPVX, MASK_VSLIDEUPVX, match_opcode, 0},
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{"th.vslideup.vi",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_VSLIDEUPVI, MASK_VSLIDEUPVI, match_opcode, 0},
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{"th.vslidedown.vx",0,INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VSLIDEDOWNVX, MASK_VSLIDEDOWNVX, match_opcode, 0},
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{"th.vslidedown.vi",0,INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_VSLIDEDOWNVI, MASK_VSLIDEDOWNVI, match_opcode, 0},
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{"th.vslide1up.vx",0 ,INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VSLIDE1UPVX, MASK_VSLIDE1UPVX, match_opcode, 0},
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{"th.vslide1down.vx",0,INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VSLIDE1DOWNVX, MASK_VSLIDE1DOWNVX, match_opcode, 0},
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{"th.vrgather.vv",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_VRGATHERVV, MASK_VRGATHERVV, match_opcode, 0},
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{"th.vrgather.vx",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_VRGATHERVX, MASK_VRGATHERVX, match_opcode, 0},
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{"th.vrgather.vi",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_VRGATHERVI, MASK_VRGATHERVI, match_opcode, 0},
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{"th.vcompress.vm",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,Vs", MATCH_VCOMPRESSVM, MASK_VCOMPRESSVM, match_opcode, 0},
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/* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
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{"vt.maskc", 64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 },
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