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aarch64: Add the SME2 MOVA instructions

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SME2 defines new MOVA instructions for moving multiple registers
to and from ZA.  As with SME, the instructions are also available
through MOV aliases.

One notable feature of these instructions (and many other SME2
instructions) is that some register lists must start at a multiple
of the list's size.  The patch uses the general error "start register
out of range" when this constraint isn't met, rather than an error
specifically about multiples.  This ensures that the error is
consistent between these simple consecutive lists and later
strided lists, for which the requirements aren't a simple multiple.
This commit is contained in:
Richard Sandiford 2023-03-30 11:09:12 +01:00
parent 503fae1299
commit d8773a8a5f
21 changed files with 2282 additions and 314 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

8
gas/config/tc-aarch64.c
View file

@ -6712,6 +6712,10 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_SVE_ZnxN:
case AARCH64_OPND_SVE_ZtxN:
case AARCH64_OPND_SME_Zdnx2:
case AARCH64_OPND_SME_Zdnx4:
case AARCH64_OPND_SME_Znx2:
case AARCH64_OPND_SME_Znx4:
reg_type = REG_TYPE_Z;
goto vector_reg_list;
@ -7708,7 +7712,9 @@ parse_operands (char *str, const aarch64_opcode *opcode)
break;
case AARCH64_OPND_SME_ZA_HV_idx_src:
case AARCH64_OPND_SME_ZA_HV_idx_srcxN:
case AARCH64_OPND_SME_ZA_HV_idx_dest:
case AARCH64_OPND_SME_ZA_HV_idx_destxN:
case AARCH64_OPND_SME_ZA_HV_idx_ldstr:
if (operands[i] == AARCH64_OPND_SME_ZA_HV_idx_ldstr
? !parse_sme_za_hv_tiles_operand_with_braces (&str,
@ -7727,6 +7733,8 @@ parse_operands (char *str, const aarch64_opcode *opcode)
info->imm.value = val;
break;
case AARCH64_OPND_SME_ZA_array_off3_0:
case AARCH64_OPND_SME_ZA_array_off3_5:
case AARCH64_OPND_SME_ZA_array_off4:
if (!parse_dual_indexed_reg (&str, REG_TYPE_ZA,
&info->indexed_za, &qualifier, 0))

2
gas/testsuite/gas/aarch64/legacy_reg_names.l
View file

@ -1,4 +1,4 @@
[^:]*: Assembler messages:
[^:]*:5: Error: indexed vector register expected at operand 1 -- `dup v0.b,v1.b\[7\]'
[^:]*:6: Error: expected a register at operand 1 -- `mov r0.w,r1.w'
[^:]*:6: Error: expected a register or register list at operand 1 -- `mov r0.w,r1.w'
[^:]*:7: Error: expected an Advanced SIMD vector register at operand 2 -- `dup s0,s1\[3\]'

2
gas/testsuite/gas/aarch64/sme-3-illegal.l
View file

@ -3,7 +3,7 @@
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za2v\.h\[w12,#0\],p0/m,z0.h'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za4v\.s\[w12,#0\],p0/m,z0.s'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za8v\.d\[w12,#0\],p0/m,z0.d'
[^:]*:[0-9]+: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `mova za16v\.q\[w12\],p0/m,z0.q'
[^:]*:[0-9]+: Error: expected a register or register list at operand 1 -- `mova za16v\.q\[w12\],p0/m,z0.q'
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 1 -- `mova za0v\.b\[w15,#16\],p7/m,z31.b'
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `mova za1v\.h\[w15,#8\],p7/m,z31.h'
[^:]*:[0-9]+: Error: immediate offset out of range 0 to 3 at operand 1 -- `mova za3v\.s\[w15,#4\],p7/m,z31.s'

3
gas/testsuite/gas/aarch64/sme2-1-invalid.d Normal file
View file

@ -0,0 +1,3 @@
#as: -march=armv8-a
#source: sme2-1-invalid.s
#error_output: sme2-1-invalid.l

327
gas/testsuite/gas/aarch64/sme2-1-invalid.l Normal file
View file

@ -0,0 +1,327 @@
[^ :]+: Assembler messages:
[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `mov 0,za\.b\[w8,0\]'
[^ :]+:[0-9]+: Error: expected a register at operand 2 -- `mov {z0\.b-z1\.b},0'
[^ :]+:[0-9]+: Error: operand mismatch -- `mov {z0\.d-z1\.d},za\.q\[w8,0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: mov {z0\.d-z1\.d}, za\.d\[w8, 0\]
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: mov {z0\.b-z1\.b}, za\.b\[w8, 0\]
[^ :]+:[0-9]+: Info: mov {z0\.h-z1\.h}, za\.h\[w8, 0\]
[^ :]+:[0-9]+: Info: mov {z0\.s-z1\.s}, za\.s\[w8, 0\]
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z1\.d-z2\.d},za\.d\[w8,0\]'
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 2 -- `mov {z0\.d-z1\.d},za\.d\[w7,0\]'
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 2 -- `mov {z0\.d-z1\.d},za\.d\[w12,0\]'
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 2 -- `mov {z0\.d-z1\.d},za\.d\[w8,-1\]'
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 2 -- `mov {z0\.d-z1\.d},za\.d\[w8,8\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `mov {z0\.d-z3\.d},za\.q\[w8,0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: mov {z0\.d-z3\.d}, za\.d\[w8, 0\]
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: mov {z0\.b-z3\.b}, za\.b\[w8, 0\]
[^ :]+:[0-9]+: Info: mov {z0\.h-z3\.h}, za\.h\[w8, 0\]
[^ :]+:[0-9]+: Info: mov {z0\.s-z3\.s}, za\.s\[w8, 0\]
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z1\.d-z4\.d},za\.d\[w8,0\]'
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z2\.d-z5\.d},za\.d\[w8,0\]'
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z3\.d-z6\.d},za\.d\[w8,0\]'
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 2 -- `mov {z0\.d-z3\.d},za\.d\[w7,0\]'
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 2 -- `mov {z0\.d-z3\.d},za\.d\[w12,0\]'
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 2 -- `mov {z0\.d-z3\.d},za\.d\[w8,-1\]'
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 2 -- `mov {z0\.d-z3\.d},za\.d\[w8,8\]'
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z1\.b-z2\.b},za0h\.b\[w8,0:1\]'
[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.b-z1\.b},za1h\.b\[w12,0:1\]'
[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.b-z1\.b},za1v\.b\[w12,0:1\]'
[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.b-z1\.b},za0h\.b\[w11,0:1\]'
[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.b-z1\.b},za0h\.b\[w16,0:1\]'
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 14 at operand 2 -- `mov {z0\.b-z1\.b},za0h\.b\[w12,-2:-1\]'
[^ :]+:[0-9]+: Error: starting offset is not a multiple of 2 at operand 2 -- `mov {z0\.b-z1\.b},za0h\.b\[w12,1:2\]'
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 14 at operand 2 -- `mov {z0\.b-z1\.b},za0h\.b\[w12,15:16\]'
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 14 at operand 2 -- `mov {z0\.b-z1\.b},za0h\.b\[w12,16:17\]'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 2 -- `mov {z0\.b-z1\.b},za0h\.b\[w12,0\]'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 2 -- `mov {z0\.b-z1\.b},za0h\.b\[w12,0:2\]'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 2 -- `mov {z0\.b-z1\.b},za0h\.b\[w12,0:3\]'
[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 1 -- `mov {z0\.b-z1\.b},za0h\.b\[w12,0:1,vgx2\]'
[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 1 -- `mov {z0\.b-z1\.b},za0h\.b\[w12,0:1,vgx4\]'
[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 2 -- `mov {z0\.b-z1\.b},za0\.b\[w12,0:1\]'
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z1\.h-z2\.h},za0h\.h\[w12,0:1\]'
[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.h-z1\.h},za2h\.h\[w12,0:1\]'
[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.h-z1\.h},za2v\.h\[w12,0:1\]'
[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.h-z1\.h},za0h\.h\[w11,0:1\]'
[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.h-z1\.h},za0h\.h\[w16,0:1\]'
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 6 at operand 2 -- `mov {z0\.h-z1\.h},za0h\.h\[w12,-2:-1\]'
[^ :]+:[0-9]+: Error: starting offset is not a multiple of 2 at operand 2 -- `mov {z0\.h-z1\.h},za0h\.h\[w12,1:2\]'
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 6 at operand 2 -- `mov {z0\.h-z1\.h},za0h\.h\[w12,7:8\]'
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 6 at operand 2 -- `mov {z0\.h-z1\.h},za0h\.h\[w12,8:9\]'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 2 -- `mov {z0\.h-z1\.h},za0h\.h\[w12,0\]'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 2 -- `mov {z0\.h-z1\.h},za0h\.h\[w12,0:2\]'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 2 -- `mov {z0\.h-z1\.h},za0h\.h\[w12,0:3\]'
[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 1 -- `mov {z0\.h-z1\.h},za0h\.h\[w12,0:1,vgx2\]'
[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 1 -- `mov {z0\.h-z1\.h},za0h\.h\[w12,0:1,vgx4\]'
[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 2 -- `mov {z0\.h-z1\.h},za0\.h\[w12,0:1\]'
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z1\.s-z2\.s},za0h\.s\[w12,0:1\]'
[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.s-z1\.s},za4h\.s\[w12,0:1\]'
[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.s-z1\.s},za4v\.s\[w12,0:1\]'
[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.s-z1\.s},za0h\.s\[w11,0:1\]'
[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.s-z1\.s},za0h\.s\[w16,0:1\]'
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 2 at operand 2 -- `mov {z0\.s-z1\.s},za0h\.s\[w12,-2:-1\]'
[^ :]+:[0-9]+: Error: starting offset is not a multiple of 2 at operand 2 -- `mov {z0\.s-z1\.s},za0h\.s\[w12,1:2\]'
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 2 at operand 2 -- `mov {z0\.s-z1\.s},za0h\.s\[w12,3:4\]'
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 2 at operand 2 -- `mov {z0\.s-z1\.s},za0h\.s\[w12,4:5\]'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 2 -- `mov {z0\.s-z1\.s},za0h\.s\[w12,0\]'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 2 -- `mov {z0\.s-z1\.s},za0h\.s\[w12,0:2\]'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 2 -- `mov {z0\.s-z1\.s},za0h\.s\[w12,0:3\]'
[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 1 -- `mov {z0\.s-z1\.s},za0h\.s\[w12,0:1,vgx2\]'
[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 1 -- `mov {z0\.s-z1\.s},za0h\.s\[w12,0:1,vgx4\]'
[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 2 -- `mov {z0\.s-z1\.s},za0\.s\[w12,0:1\]'
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z1\.d-z2\.d},za0h\.d\[w12,0:1\]'
[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.d-z1\.d},za8h\.d\[w12,0:1\]'
[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.d-z1\.d},za8v\.d\[w12,0:1\]'
[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.d-z1\.d},za0h\.d\[w11,0:1\]'
[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.d-z1\.d},za0h\.d\[w16,0:1\]'
[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 2 -- `mov {z0\.d-z1\.d},za0h\.d\[w12,-2:-1\]'
[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 2 -- `mov {z0\.d-z1\.d},za0h\.d\[w12,1:2\]'
[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 2 -- `mov {z0\.d-z1\.d},za0h\.d\[w12,2:3\]'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 2 -- `mov {z0\.d-z1\.d},za0h\.d\[w12,0\]'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 2 -- `mov {z0\.d-z1\.d},za0h\.d\[w12,0:2\]'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 2 -- `mov {z0\.d-z1\.d},za0h\.d\[w12,0:3\]'
[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 1 -- `mov {z0\.d-z1\.d},za0h\.d\[w12,0:1,vgx2\]'
[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 1 -- `mov {z0\.d-z1\.d},za0h\.d\[w12,0:1,vgx4\]'
[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 2 -- `mov {z0\.d-z1\.d},za0\.d\[w12,0:1\]'
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z1\.b-z4\.b},za0h\.b\[w12,0:3\]'
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z2\.b-z5\.b},za0h\.b\[w12,0:3\]'
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z3\.b-z6\.b},za0h\.b\[w12,0:3\]'
[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.b-z3\.b},za1h\.b\[w12,0:3\]'
[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.b-z3\.b},za1v\.b\[w12,0:3\]'
[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.b-z3\.b},za0h\.b\[w11,0:3\]'
[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.b-z3\.b},za0h\.b\[w16,0:3\]'
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 12 at operand 2 -- `mov {z0\.b-z3\.b},za0h\.b\[w12,-4:-1\]'
[^ :]+:[0-9]+: Error: starting offset is not a multiple of 4 at operand 2 -- `mov {z0\.b-z3\.b},za0h\.b\[w12,1:4\]'
[^ :]+:[0-9]+: Error: starting offset is not a multiple of 4 at operand 2 -- `mov {z0\.b-z3\.b},za0h\.b\[w12,2:5\]'
[^ :]+:[0-9]+: Error: starting offset is not a multiple of 4 at operand 2 -- `mov {z0\.b-z3\.b},za0h\.b\[w12,3:6\]'
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 12 at operand 2 -- `mov {z0\.b-z3\.b},za0h\.b\[w12,13:16\]'
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 12 at operand 2 -- `mov {z0\.b-z3\.b},za0h\.b\[w12,14:17\]'
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 12 at operand 2 -- `mov {z0\.b-z3\.b},za0h\.b\[w12,15:18\]'
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 12 at operand 2 -- `mov {z0\.b-z3\.b},za0h\.b\[w12,16:19\]'
[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 2 -- `mov {z0\.b-z3\.b},za0h\.b\[w12,0\]'
[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 2 -- `mov {z0\.b-z3\.b},za0h\.b\[w12,0:1\]'
[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 2 -- `mov {z0\.b-z3\.b},za0h\.b\[w12,0:2\]'
[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 1 -- `mov {z0\.b-z3\.b},za0h\.b\[w12,0:3,vgx2\]'
[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 1 -- `mov {z0\.b-z3\.b},za0h\.b\[w12,0:3,vgx4\]'
[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 2 -- `mov {z0\.b-z3\.b},za0\.b\[w12,0:3\]'
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z1\.h-z2\.h},za0h\.h\[w12,0:3\]'
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z2\.h-z5\.h},za0h\.h\[w12,0:3\]'
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z3\.h-z6\.h},za0h\.h\[w12,0:3\]'
[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.h-z3\.h},za2h\.h\[w12,0:3\]'
[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.h-z3\.h},za2v\.h\[w12,0:3\]'
[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.h-z3\.h},za0h\.h\[w11,0:3\]'
[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.h-z3\.h},za0h\.h\[w16,0:3\]'
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 4 at operand 2 -- `mov {z0\.h-z3\.h},za0h\.h\[w12,-4:-1\]'
[^ :]+:[0-9]+: Error: starting offset is not a multiple of 4 at operand 2 -- `mov {z0\.h-z3\.h},za0h\.h\[w12,1:2\]'
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 4 at operand 2 -- `mov {z0\.h-z3\.h},za0h\.h\[w12,5:8\]'
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 4 at operand 2 -- `mov {z0\.h-z3\.h},za0h\.h\[w12,6:9\]'
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 4 at operand 2 -- `mov {z0\.h-z3\.h},za0h\.h\[w12,7:10\]'
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 4 at operand 2 -- `mov {z0\.h-z3\.h},za0h\.h\[w12,8:11\]'
[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 2 -- `mov {z0\.h-z3\.h},za0h\.h\[w12,0\]'
[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 2 -- `mov {z0\.h-z3\.h},za0h\.h\[w12,0:1\]'
[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 2 -- `mov {z0\.h-z3\.h},za0h\.h\[w12,0:2\]'
[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 1 -- `mov {z0\.h-z3\.h},za0h\.h\[w12,0:3,vgx2\]'
[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 1 -- `mov {z0\.h-z3\.h},za0h\.h\[w12,0:3,vgx4\]'
[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 2 -- `mov {z0\.h-z3\.h},za0\.h\[w12,0:3\]'
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z1\.s-z2\.s},za0h\.s\[w12,0:3\]'
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z2\.s-z5\.s},za0h\.s\[w12,0:3\]'
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z3\.s-z6\.s},za0h\.s\[w12,0:3\]'
[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.s-z3\.s},za4h\.s\[w12,0:3\]'
[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.s-z3\.s},za4v\.s\[w12,0:3\]'
[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.s-z3\.s},za0h\.s\[w11,0:3\]'
[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.s-z3\.s},za0h\.s\[w16,0:3\]'
[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 2 -- `mov {z0\.s-z3\.s},za0h\.s\[w12,-4:-1\]'
[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 2 -- `mov {z0\.s-z3\.s},za0h\.s\[w12,1:4\]'
[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 2 -- `mov {z0\.s-z3\.s},za0h\.s\[w12,2:5\]'
[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 2 -- `mov {z0\.s-z3\.s},za0h\.s\[w12,3:6\]'
[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 2 -- `mov {z0\.s-z3\.s},za0h\.s\[w12,4:7\]'
[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 2 -- `mov {z0\.s-z3\.s},za0h\.s\[w12,0\]'
[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 2 -- `mov {z0\.s-z3\.s},za0h\.s\[w12,0:1\]'
[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 2 -- `mov {z0\.s-z3\.s},za0h\.s\[w12,0:2\]'
[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 1 -- `mov {z0\.s-z3\.s},za0h\.s\[w12,0:3,vgx2\]'
[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 1 -- `mov {z0\.s-z3\.s},za0h\.s\[w12,0:3,vgx4\]'
[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 2 -- `mov {z0\.s-z3\.s},za0\.s\[w12,0:3\]'
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z1\.d-z2\.d},za0h\.d\[w12,0:3\]'
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z2\.d-z5\.d},za0h\.d\[w12,0:3\]'
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z3\.d-z6\.d},za0h\.d\[w12,0:3\]'
[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.d-z3\.d},za8h\.d\[w12,0:3\]'
[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.d-z3\.d},za8v\.d\[w12,0:3\]'
[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.d-z3\.d},za0h\.d\[w11,0:3\]'
[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.d-z3\.d},za0h\.d\[w16,0:3\]'
[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 2 -- `mov {z0\.d-z3\.d},za0h\.d\[w12,-4:-1\]'
[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 2 -- `mov {z0\.d-z3\.d},za0h\.d\[w12,1:4\]'
[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 2 -- `mov {z0\.d-z3\.d},za0h\.d\[w12,2:5\]'
[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 2 -- `mov {z0\.d-z3\.d},za0h\.d\[w12,3:6\]'
[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 2 -- `mov {z0\.d-z3\.d},za0h\.d\[w12,4:7\]'
[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 2 -- `mov {z0\.d-z3\.d},za0h\.d\[w12,0\]'
[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 2 -- `mov {z0\.d-z3\.d},za0h\.d\[w12,0:1\]'
[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 2 -- `mov {z0\.d-z3\.d},za0h\.d\[w12,0:2\]'
[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 1 -- `mov {z0\.d-z3\.d},za0h\.d\[w12,0:3,vgx2\]'
[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 1 -- `mov {z0\.d-z3\.d},za0h\.d\[w12,0:3,vgx4\]'
[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 2 -- `mov {z0\.d-z3\.d},za0\.d\[w12,0:3\]'
[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `mova 0,za\.b\[w8,0\]'
[^ :]+:[0-9]+: Error: expected a register at operand 2 -- `mova {z0\.b-z1\.b},0'
[^ :]+:[0-9]+: Error: operand mismatch -- `mova za\.q\[w8,0\],{z0\.q-z1\.q}'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: mova za\.b\[w8, 0\], {z0\.b-z1\.b}
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: mova za\.h\[w8, 0\], {z0\.h-z1\.h}
[^ :]+:[0-9]+: Info: mova za\.s\[w8, 0\], {z0\.s-z1\.s}
[^ :]+:[0-9]+: Info: mova za\.d\[w8, 0\], {z0\.d-z1\.d}
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `mova za\.d\[w7,0\],{z0\.d-z1\.d}'
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `mova za\.d\[w12,0\],{z0\.d-z1\.d}'
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `mova za\.d\[w8,-1\],{z0\.d-z1\.d}'
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `mova za\.d\[w8,8\],{z0\.d-z1\.d}'
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za\.d\[w8,0\],{z1\.d-z2\.d}'
[^ :]+:[0-9]+: Error: operand mismatch -- `mova za\.q\[w8,0\],{z0\.q-z3\.q}'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: mova za\.b\[w8, 0\], {z0\.b-z3\.b}
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: mova za\.h\[w8, 0\], {z0\.h-z3\.h}
[^ :]+:[0-9]+: Info: mova za\.s\[w8, 0\], {z0\.s-z3\.s}
[^ :]+:[0-9]+: Info: mova za\.d\[w8, 0\], {z0\.d-z3\.d}
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `mova za\.d\[w7,0\],{z0\.d-z3\.d}'
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `mova za\.d\[w12,0\],{z0\.d-z3\.d}'
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `mova za\.d\[w8,-1\],{z0\.d-z3\.d}'
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `mova za\.d\[w8,8\],{z0\.d-z3\.d}'
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za\.d\[w8,0\],{z1\.d-z4\.d}'
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za\.d\[w8,0\],{z2\.d-z5\.d}'
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za\.d\[w8,0\],{z3\.d-z6\.d}'
[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.b\[w8,0:1\],{z1\.b-z2\.b}'
[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za1h\.b\[w12,0:1\],{z0\.b-z1\.b}'
[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za1v\.b\[w12,0:1\],{z0\.b-z1\.b}'
[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.b\[w11,0:1\],{z0\.b-z1\.b}'
[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.b\[w16,0:1\],{z0\.b-z1\.b}'
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 14 at operand 1 -- `mova za0h\.b\[w12,-2:-1\],{z0\.b-z1\.b}'
[^ :]+:[0-9]+: Error: starting offset is not a multiple of 2 at operand 1 -- `mova za0h\.b\[w12,1:2\],{z0\.b-z1\.b}'
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 14 at operand 1 -- `mova za0h\.b\[w12,15:16\],{z0\.b-z1\.b}'
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 14 at operand 1 -- `mova za0h\.b\[w12,16:17\],{z0\.b-z1\.b}'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.b\[w12,0\],{z0\.b-z1\.b}'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.b\[w12,0:2\],{z0\.b-z1\.b}'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.b\[w12,0:3\],{z0\.b-z1\.b}'
[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 1 -- `mova za0h\.b\[w12,0:1,vgx2\],{z0\.b-z1\.b}'
[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 1 -- `mova za0h\.b\[w12,0:1,vgx4\],{z0\.b-z1\.b}'
[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 1 -- `mova za0\.b\[w12,0:1\],{z0\.b-z1\.b}'
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za0h\.h\[w12,0:1\],{z1\.h-z2\.h}'
[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za2h\.h\[w12,0:1\],{z0\.h-z1\.h}'
[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za2v\.h\[w12,0:1\],{z0\.h-z1\.h}'
[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.h\[w11,0:1\],{z0\.h-z1\.h}'
[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.h\[w16,0:1\],{z0\.h-z1\.h}'
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 6 at operand 1 -- `mova za0h\.h\[w12,-2:-1\],{z0\.h-z1\.h}'
[^ :]+:[0-9]+: Error: starting offset is not a multiple of 2 at operand 1 -- `mova za0h\.h\[w12,1:2\],{z0\.h-z1\.h}'
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 6 at operand 1 -- `mova za0h\.h\[w12,7:8\],{z0\.h-z1\.h}'
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 6 at operand 1 -- `mova za0h\.h\[w12,8:9\],{z0\.h-z1\.h}'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.h\[w12,0\],{z0\.h-z1\.h}'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.h\[w12,0:2\],{z0\.h-z1\.h}'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.h\[w12,0:3\],{z0\.h-z1\.h}'
[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 1 -- `mova za0h\.h\[w12,0:1,vgx2\],{z0\.h-z1\.h}'
[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 1 -- `mova za0h\.h\[w12,0:1,vgx4\],{z0\.h-z1\.h}'
[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 1 -- `mova za0\.h\[w12,0:1\],{z0\.h-z1\.h}'
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za0h\.s\[w12,0:1\],{z1\.s-z2\.s}'
[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za4h\.s\[w12,0:1\],{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za4v\.s\[w12,0:1\],{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.s\[w11,0:1\],{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.s\[w16,0:1\],{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 2 at operand 1 -- `mova za0h\.s\[w12,-2:-1\],{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: starting offset is not a multiple of 2 at operand 1 -- `mova za0h\.s\[w12,1:2\],{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 2 at operand 1 -- `mova za0h\.s\[w12,3:4\],{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 2 at operand 1 -- `mova za0h\.s\[w12,4:5\],{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.s\[w12,0\],{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.s\[w12,0:2\],{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.s\[w12,0:3\],{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 1 -- `mova za0h\.s\[w12,0:1,vgx2\],{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 1 -- `mova za0h\.s\[w12,0:1,vgx4\],{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 1 -- `mova za0\.s\[w12,0:1\],{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za0h\.d\[w12,0:1\],{z1\.d-z2\.d}'
[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za8h\.d\[w12,0:1\],{z0\.d-z1\.d}'
[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za8v\.d\[w12,0:1\],{z0\.d-z1\.d}'
[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.d\[w11,0:1\],{z0\.d-z1\.d}'
[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.d\[w16,0:1\],{z0\.d-z1\.d}'
[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `mova za0h\.d\[w12,-2:-1\],{z0\.d-z1\.d}'
[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `mova za0h\.d\[w12,1:2\],{z0\.d-z1\.d}'
[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `mova za0h\.d\[w12,2:3\],{z0\.d-z1\.d}'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.d\[w12,0\],{z0\.d-z1\.d}'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.d\[w12,0:2\],{z0\.d-z1\.d}'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.d\[w12,0:3\],{z0\.d-z1\.d}'
[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 1 -- `mova za0h\.d\[w12,0:1,vgx2\],{z0\.d-z1\.d}'
[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 1 -- `mova za0h\.d\[w12,0:1,vgx4\],{z0\.d-z1\.d}'
[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 1 -- `mova za0\.d\[w12,0:1\],{z0\.d-z1\.d}'
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za0h\.b\[w12,0:3\],{z1\.b-z4\.b}'
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za0h\.b\[w12,0:3\],{z2\.b-z5\.b}'
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za0h\.b\[w12,0:3\],{z3\.b-z6\.b}'
[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za1h\.b\[w12,0:3\],{z0\.b-z3\.b}'
[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za1v\.b\[w12,0:3\],{z0\.b-z3\.b}'
[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.b\[w11,0:3\],{z0\.b-z3\.b}'
[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.b\[w16,0:3\],{z0\.b-z3\.b}'
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 14 at operand 1 -- `mova za0h\.b\[w12,-4:-1\],{z0\.b-z3\.b}'
[^ :]+:[0-9]+: Error: starting offset is not a multiple of 2 at operand 1 -- `mova za0h\.b\[w12,1:4\],{z0\.b-z3\.b}'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.b\[w12,2:5\],{z0\.b-z3\.b}'
[^ :]+:[0-9]+: Error: starting offset is not a multiple of 2 at operand 1 -- `mova za0h\.b\[w12,3:6\],{z0\.b-z3\.b}'
[^ :]+:[0-9]+: Error: starting offset is not a multiple of 2 at operand 1 -- `mova za0h\.b\[w12,13:16\],{z0\.b-z3\.b}'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.b\[w12,14:17\],{z0\.b-z3\.b}'
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 14 at operand 1 -- `mova za0h\.b\[w12,15:18\],{z0\.b-z3\.b}'
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 14 at operand 1 -- `mova za0h\.b\[w12,16:19\],{z0\.b-z3\.b}'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.b\[w12,0\],{z0\.b-z3\.b}'
[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 1 -- `mova za0h\.b\[w12,0:1\],{z0\.b-z3\.b}'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.b\[w12,0:2\],{z0\.b-z3\.b}'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.b\[w12,0:3,vgx2\],{z0\.b-z3\.b}'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.b\[w12,0:3,vgx4\],{z0\.b-z3\.b}'
[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 1 -- `mova za0\.b\[w12,0:3\],{z0\.b-z3\.b}'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.h\[w12,0:3\],{z1\.h-z2\.h}'
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za0h\.h\[w12,0:3\],{z2\.h-z5\.h}'
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za0h\.h\[w12,0:3\],{z3\.h-z6\.h}'
[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za2h\.h\[w12,0:3\],{z0\.h-z3\.h}'
[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za2v\.h\[w12,0:3\],{z0\.h-z3\.h}'
[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.h\[w11,0:3\],{z0\.h-z3\.h}'
[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.h\[w16,0:3\],{z0\.h-z3\.h}'
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 6 at operand 1 -- `mova za0h\.h\[w12,-4:-1\],{z0\.h-z3\.h}'
[^ :]+:[0-9]+: Error: starting offset is not a multiple of 2 at operand 1 -- `mova za0h\.h\[w12,1:2\],{z0\.h-z3\.h}'
[^ :]+:[0-9]+: Error: starting offset is not a multiple of 2 at operand 1 -- `mova za0h\.h\[w12,5:8\],{z0\.h-z3\.h}'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.h\[w12,6:9\],{z0\.h-z3\.h}'
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 6 at operand 1 -- `mova za0h\.h\[w12,7:10\],{z0\.h-z3\.h}'
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 6 at operand 1 -- `mova za0h\.h\[w12,8:11\],{z0\.h-z3\.h}'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.h\[w12,0\],{z0\.h-z3\.h}'
[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 1 -- `mova za0h\.h\[w12,0:1\],{z0\.h-z3\.h}'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.h\[w12,0:2\],{z0\.h-z3\.h}'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.h\[w12,0:3,vgx2\],{z0\.h-z3\.h}'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.h\[w12,0:3,vgx4\],{z0\.h-z3\.h}'
[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 1 -- `mova za0\.h\[w12,0:3\],{z0\.h-z3\.h}'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.s\[w12,0:3\],{z1\.s-z2\.s}'
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za0h\.s\[w12,0:3\],{z2\.s-z5\.s}'
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za0h\.s\[w12,0:3\],{z3\.s-z6\.s}'
[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za4h\.s\[w12,0:3\],{z0\.s-z3\.s}'
[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za4v\.s\[w12,0:3\],{z0\.s-z3\.s}'
[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.s\[w11,0:3\],{z0\.s-z3\.s}'
[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.s\[w16,0:3\],{z0\.s-z3\.s}'
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 2 at operand 1 -- `mova za0h\.s\[w12,-4:-1\],{z0\.s-z3\.s}'
[^ :]+:[0-9]+: Error: starting offset is not a multiple of 2 at operand 1 -- `mova za0h\.s\[w12,1:4\],{z0\.s-z3\.s}'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.s\[w12,2:5\],{z0\.s-z3\.s}'
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 2 at operand 1 -- `mova za0h\.s\[w12,3:6\],{z0\.s-z3\.s}'
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 2 at operand 1 -- `mova za0h\.s\[w12,4:7\],{z0\.s-z3\.s}'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.s\[w12,0\],{z0\.s-z3\.s}'
[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 1 -- `mova za0h\.s\[w12,0:1\],{z0\.s-z3\.s}'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.s\[w12,0:2\],{z0\.s-z3\.s}'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.s\[w12,0:3,vgx2\],{z0\.s-z3\.s}'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.s\[w12,0:3,vgx4\],{z0\.s-z3\.s}'
[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 1 -- `mova za0\.s\[w12,0:3\],{z0\.s-z3\.s}'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.d\[w12,0:3\],{z1\.d-z2\.d}'
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za0h\.d\[w12,0:3\],{z2\.d-z5\.d}'
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za0h\.d\[w12,0:3\],{z3\.d-z6\.d}'
[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za8h\.d\[w12,0:3\],{z0\.d-z3\.d}'
[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za8v\.d\[w12,0:3\],{z0\.d-z3\.d}'
[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.d\[w11,0:3\],{z0\.d-z3\.d}'
[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.d\[w16,0:3\],{z0\.d-z3\.d}'
[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `mova za0h\.d\[w12,-4:-1\],{z0\.d-z3\.d}'
[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `mova za0h\.d\[w12,1:4\],{z0\.d-z3\.d}'
[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `mova za0h\.d\[w12,2:5\],{z0\.d-z3\.d}'
[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `mova za0h\.d\[w12,3:6\],{z0\.d-z3\.d}'
[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `mova za0h\.d\[w12,4:7\],{z0\.d-z3\.d}'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.d\[w12,0\],{z0\.d-z3\.d}'
[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 1 -- `mova za0h\.d\[w12,0:1\],{z0\.d-z3\.d}'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.d\[w12,0:2\],{z0\.d-z3\.d}'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.d\[w12,0:3,vgx2\],{z0\.d-z3\.d}'
[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.d\[w12,0:3,vgx4\],{z0\.d-z3\.d}'
[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 1 -- `mova za0\.d\[w12,0:3\],{z0\.d-z3\.d}'

323
gas/testsuite/gas/aarch64/sme2-1-invalid.s Normal file
View file

@ -0,0 +1,323 @@
mov 0, za.b[w8, 0]
mov { z0.b - z1.b }, 0
mov { z0.d - z1.d }, za.q[w8, 0]
mov { z1.d - z2.d }, za.d[w8, 0]
mov { z0.d - z1.d }, za.d[w7, 0]
mov { z0.d - z1.d }, za.d[w12, 0]
mov { z0.d - z1.d }, za.d[w8, -1]
mov { z0.d - z1.d }, za.d[w8, 8]
mov { z0.d - z3.d }, za.q[w8, 0]
mov { z1.d - z4.d }, za.d[w8, 0]
mov { z2.d - z5.d }, za.d[w8, 0]
mov { z3.d - z6.d }, za.d[w8, 0]
mov { z0.d - z3.d }, za.d[w7, 0]
mov { z0.d - z3.d }, za.d[w12, 0]
mov { z0.d - z3.d }, za.d[w8, -1]
mov { z0.d - z3.d }, za.d[w8, 8]
mov { z1.b - z2.b }, za0h.b[w8, 0:1]
mov { z0.b - z1.b }, za1h.b[w12, 0:1]
mov { z0.b - z1.b }, za1v.b[w12, 0:1]
mov { z0.b - z1.b }, za0h.b[w11, 0:1]
mov { z0.b - z1.b }, za0h.b[w16, 0:1]
mov { z0.b - z1.b }, za0h.b[w12, -2:-1]
mov { z0.b - z1.b }, za0h.b[w12, 1:2]
mov { z0.b - z1.b }, za0h.b[w12, 15:16]
mov { z0.b - z1.b }, za0h.b[w12, 16:17]
mov { z0.b - z1.b }, za0h.b[w12, 0]
mov { z0.b - z1.b }, za0h.b[w12, 0:2]
mov { z0.b - z1.b }, za0h.b[w12, 0:3]
mov { z0.b - z1.b }, za0h.b[w12, 0:1, vgx2]
mov { z0.b - z1.b }, za0h.b[w12, 0:1, vgx4]
mov { z0.b - z1.b }, za0.b[w12, 0:1]
mov { z1.h - z2.h }, za0h.h[w12, 0:1]
mov { z0.h - z1.h }, za2h.h[w12, 0:1]
mov { z0.h - z1.h }, za2v.h[w12, 0:1]
mov { z0.h - z1.h }, za0h.h[w11, 0:1]
mov { z0.h - z1.h }, za0h.h[w16, 0:1]
mov { z0.h - z1.h }, za0h.h[w12, -2:-1]
mov { z0.h - z1.h }, za0h.h[w12, 1:2]
mov { z0.h - z1.h }, za0h.h[w12, 7:8]
mov { z0.h - z1.h }, za0h.h[w12, 8:9]
mov { z0.h - z1.h }, za0h.h[w12, 0]
mov { z0.h - z1.h }, za0h.h[w12, 0:2]
mov { z0.h - z1.h }, za0h.h[w12, 0:3]
mov { z0.h - z1.h }, za0h.h[w12, 0:1, vgx2]
mov { z0.h - z1.h }, za0h.h[w12, 0:1, vgx4]
mov { z0.h - z1.h }, za0.h[w12, 0:1]
mov { z1.s - z2.s }, za0h.s[w12, 0:1]
mov { z0.s - z1.s }, za4h.s[w12, 0:1]
mov { z0.s - z1.s }, za4v.s[w12, 0:1]
mov { z0.s - z1.s }, za0h.s[w11, 0:1]
mov { z0.s - z1.s }, za0h.s[w16, 0:1]
mov { z0.s - z1.s }, za0h.s[w12, -2:-1]
mov { z0.s - z1.s }, za0h.s[w12, 1:2]
mov { z0.s - z1.s }, za0h.s[w12, 3:4]
mov { z0.s - z1.s }, za0h.s[w12, 4:5]
mov { z0.s - z1.s }, za0h.s[w12, 0]
mov { z0.s - z1.s }, za0h.s[w12, 0:2]
mov { z0.s - z1.s }, za0h.s[w12, 0:3]
mov { z0.s - z1.s }, za0h.s[w12, 0:1, vgx2]
mov { z0.s - z1.s }, za0h.s[w12, 0:1, vgx4]
mov { z0.s - z1.s }, za0.s[w12, 0:1]
mov { z1.d - z2.d }, za0h.d[w12, 0:1]
mov { z0.d - z1.d }, za8h.d[w12, 0:1]
mov { z0.d - z1.d }, za8v.d[w12, 0:1]
mov { z0.d - z1.d }, za0h.d[w11, 0:1]
mov { z0.d - z1.d }, za0h.d[w16, 0:1]
mov { z0.d - z1.d }, za0h.d[w12, -2:-1]
mov { z0.d - z1.d }, za0h.d[w12, 1:2]
mov { z0.d - z1.d }, za0h.d[w12, 2:3]
mov { z0.d - z1.d }, za0h.d[w12, 0]
mov { z0.d - z1.d }, za0h.d[w12, 0:2]
mov { z0.d - z1.d }, za0h.d[w12, 0:3]
mov { z0.d - z1.d }, za0h.d[w12, 0:1, vgx2]
mov { z0.d - z1.d }, za0h.d[w12, 0:1, vgx4]
mov { z0.d - z1.d }, za0.d[w12, 0:1]
mov { z1.b - z4.b }, za0h.b[w12, 0:3]
mov { z2.b - z5.b }, za0h.b[w12, 0:3]
mov { z3.b - z6.b }, za0h.b[w12, 0:3]
mov { z0.b - z3.b }, za1h.b[w12, 0:3]
mov { z0.b - z3.b }, za1v.b[w12, 0:3]
mov { z0.b - z3.b }, za0h.b[w11, 0:3]
mov { z0.b - z3.b }, za0h.b[w16, 0:3]
mov { z0.b - z3.b }, za0h.b[w12, -4:-1]
mov { z0.b - z3.b }, za0h.b[w12, 1:4]
mov { z0.b - z3.b }, za0h.b[w12, 2:5]
mov { z0.b - z3.b }, za0h.b[w12, 3:6]
mov { z0.b - z3.b }, za0h.b[w12, 13:16]
mov { z0.b - z3.b }, za0h.b[w12, 14:17]
mov { z0.b - z3.b }, za0h.b[w12, 15:18]
mov { z0.b - z3.b }, za0h.b[w12, 16:19]
mov { z0.b - z3.b }, za0h.b[w12, 0]
mov { z0.b - z3.b }, za0h.b[w12, 0:1]
mov { z0.b - z3.b }, za0h.b[w12, 0:2]
mov { z0.b - z3.b }, za0h.b[w12, 0:3, vgx2]
mov { z0.b - z3.b }, za0h.b[w12, 0:3, vgx4]
mov { z0.b - z3.b }, za0.b[w12, 0:3]
mov { z1.h - z2.h }, za0h.h[w12, 0:3]
mov { z2.h - z5.h }, za0h.h[w12, 0:3]
mov { z3.h - z6.h }, za0h.h[w12, 0:3]
mov { z0.h - z3.h }, za2h.h[w12, 0:3]
mov { z0.h - z3.h }, za2v.h[w12, 0:3]
mov { z0.h - z3.h }, za0h.h[w11, 0:3]
mov { z0.h - z3.h }, za0h.h[w16, 0:3]
mov { z0.h - z3.h }, za0h.h[w12, -4:-1]
mov { z0.h - z3.h }, za0h.h[w12, 1:2]
mov { z0.h - z3.h }, za0h.h[w12, 5:8]
mov { z0.h - z3.h }, za0h.h[w12, 6:9]
mov { z0.h - z3.h }, za0h.h[w12, 7:10]
mov { z0.h - z3.h }, za0h.h[w12, 8:11]
mov { z0.h - z3.h }, za0h.h[w12, 0]
mov { z0.h - z3.h }, za0h.h[w12, 0:1]
mov { z0.h - z3.h }, za0h.h[w12, 0:2]
mov { z0.h - z3.h }, za0h.h[w12, 0:3, vgx2]
mov { z0.h - z3.h }, za0h.h[w12, 0:3, vgx4]
mov { z0.h - z3.h }, za0.h[w12, 0:3]
mov { z1.s - z2.s }, za0h.s[w12, 0:3]
mov { z2.s - z5.s }, za0h.s[w12, 0:3]
mov { z3.s - z6.s }, za0h.s[w12, 0:3]
mov { z0.s - z3.s }, za4h.s[w12, 0:3]
mov { z0.s - z3.s }, za4v.s[w12, 0:3]
mov { z0.s - z3.s }, za0h.s[w11, 0:3]
mov { z0.s - z3.s }, za0h.s[w16, 0:3]
mov { z0.s - z3.s }, za0h.s[w12, -4:-1]
mov { z0.s - z3.s }, za0h.s[w12, 1:4]
mov { z0.s - z3.s }, za0h.s[w12, 2:5]
mov { z0.s - z3.s }, za0h.s[w12, 3:6]
mov { z0.s - z3.s }, za0h.s[w12, 4:7]
mov { z0.s - z3.s }, za0h.s[w12, 0]
mov { z0.s - z3.s }, za0h.s[w12, 0:1]
mov { z0.s - z3.s }, za0h.s[w12, 0:2]
mov { z0.s - z3.s }, za0h.s[w12, 0:3, vgx2]
mov { z0.s - z3.s }, za0h.s[w12, 0:3, vgx4]
mov { z0.s - z3.s }, za0.s[w12, 0:3]
mov { z1.d - z2.d }, za0h.d[w12, 0:3]
mov { z2.d - z5.d }, za0h.d[w12, 0:3]
mov { z3.d - z6.d }, za0h.d[w12, 0:3]
mov { z0.d - z3.d }, za8h.d[w12, 0:3]
mov { z0.d - z3.d }, za8v.d[w12, 0:3]
mov { z0.d - z3.d }, za0h.d[w11, 0:3]
mov { z0.d - z3.d }, za0h.d[w16, 0:3]
mov { z0.d - z3.d }, za0h.d[w12, -4:-1]
mov { z0.d - z3.d }, za0h.d[w12, 1:4]
mov { z0.d - z3.d }, za0h.d[w12, 2:5]
mov { z0.d - z3.d }, za0h.d[w12, 3:6]
mov { z0.d - z3.d }, za0h.d[w12, 4:7]
mov { z0.d - z3.d }, za0h.d[w12, 0]
mov { z0.d - z3.d }, za0h.d[w12, 0:1]
mov { z0.d - z3.d }, za0h.d[w12, 0:2]
mov { z0.d - z3.d }, za0h.d[w12, 0:3, vgx2]
mov { z0.d - z3.d }, za0h.d[w12, 0:3, vgx4]
mov { z0.d - z3.d }, za0.d[w12, 0:3]
mova 0, za.b[w8, 0]
mova { z0.b - z1.b }, 0
mova za.q[w8, 0], { z0.q - z1.q }
mova za.d[w7, 0], { z0.d - z1.d }
mova za.d[w12, 0], { z0.d - z1.d }
mova za.d[w8, -1], { z0.d - z1.d }
mova za.d[w8, 8], { z0.d - z1.d }
mova za.d[w8, 0], { z1.d - z2.d }
mova za.q[w8, 0], { z0.q - z3.q }
mova za.d[w7, 0], { z0.d - z3.d }
mova za.d[w12, 0], { z0.d - z3.d }
mova za.d[w8, -1], { z0.d - z3.d }
mova za.d[w8, 8], { z0.d - z3.d }
mova za.d[w8, 0], { z1.d - z4.d }
mova za.d[w8, 0], { z2.d - z5.d }
mova za.d[w8, 0], { z3.d - z6.d }
mova za0h.b[w8, 0:1], { z1.b - z2.b }
mova za1h.b[w12, 0:1], { z0.b - z1.b }
mova za1v.b[w12, 0:1], { z0.b - z1.b }
mova za0h.b[w11, 0:1], { z0.b - z1.b }
mova za0h.b[w16, 0:1], { z0.b - z1.b }
mova za0h.b[w12, -2:-1], { z0.b - z1.b }
mova za0h.b[w12, 1:2], { z0.b - z1.b }
mova za0h.b[w12, 15:16], { z0.b - z1.b }
mova za0h.b[w12, 16:17], { z0.b - z1.b }
mova za0h.b[w12, 0], { z0.b - z1.b }
mova za0h.b[w12, 0:2], { z0.b - z1.b }
mova za0h.b[w12, 0:3], { z0.b - z1.b }
mova za0h.b[w12, 0:1, vgx2], { z0.b - z1.b }
mova za0h.b[w12, 0:1, vgx4], { z0.b - z1.b }
mova za0.b[w12, 0:1], { z0.b - z1.b }
mova za0h.h[w12, 0:1], { z1.h - z2.h }
mova za2h.h[w12, 0:1], { z0.h - z1.h }
mova za2v.h[w12, 0:1], { z0.h - z1.h }
mova za0h.h[w11, 0:1], { z0.h - z1.h }
mova za0h.h[w16, 0:1], { z0.h - z1.h }
mova za0h.h[w12, -2:-1], { z0.h - z1.h }
mova za0h.h[w12, 1:2], { z0.h - z1.h }
mova za0h.h[w12, 7:8], { z0.h - z1.h }
mova za0h.h[w12, 8:9], { z0.h - z1.h }
mova za0h.h[w12, 0], { z0.h - z1.h }
mova za0h.h[w12, 0:2], { z0.h - z1.h }
mova za0h.h[w12, 0:3], { z0.h - z1.h }
mova za0h.h[w12, 0:1, vgx2], { z0.h - z1.h }
mova za0h.h[w12, 0:1, vgx4], { z0.h - z1.h }
mova za0.h[w12, 0:1], { z0.h - z1.h }
mova za0h.s[w12, 0:1], { z1.s - z2.s }
mova za4h.s[w12, 0:1], { z0.s - z1.s }
mova za4v.s[w12, 0:1], { z0.s - z1.s }
mova za0h.s[w11, 0:1], { z0.s - z1.s }
mova za0h.s[w16, 0:1], { z0.s - z1.s }
mova za0h.s[w12, -2:-1], { z0.s - z1.s }
mova za0h.s[w12, 1:2], { z0.s - z1.s }
mova za0h.s[w12, 3:4], { z0.s - z1.s }
mova za0h.s[w12, 4:5], { z0.s - z1.s }
mova za0h.s[w12, 0], { z0.s - z1.s }
mova za0h.s[w12, 0:2], { z0.s - z1.s }
mova za0h.s[w12, 0:3], { z0.s - z1.s }
mova za0h.s[w12, 0:1, vgx2], { z0.s - z1.s }
mova za0h.s[w12, 0:1, vgx4], { z0.s - z1.s }
mova za0.s[w12, 0:1], { z0.s - z1.s }
mova za0h.d[w12, 0:1], { z1.d - z2.d }
mova za8h.d[w12, 0:1], { z0.d - z1.d }
mova za8v.d[w12, 0:1], { z0.d - z1.d }
mova za0h.d[w11, 0:1], { z0.d - z1.d }
mova za0h.d[w16, 0:1], { z0.d - z1.d }
mova za0h.d[w12, -2:-1], { z0.d - z1.d }
mova za0h.d[w12, 1:2], { z0.d - z1.d }
mova za0h.d[w12, 2:3], { z0.d - z1.d }
mova za0h.d[w12, 0], { z0.d - z1.d }
mova za0h.d[w12, 0:2], { z0.d - z1.d }
mova za0h.d[w12, 0:3], { z0.d - z1.d }
mova za0h.d[w12, 0:1, vgx2], { z0.d - z1.d }
mova za0h.d[w12, 0:1, vgx4], { z0.d - z1.d }
mova za0.d[w12, 0:1], { z0.d - z1.d }
mova za0h.b[w12, 0:3], { z1.b - z4.b }
mova za0h.b[w12, 0:3], { z2.b - z5.b }
mova za0h.b[w12, 0:3], { z3.b - z6.b }
mova za1h.b[w12, 0:3], { z0.b - z3.b }
mova za1v.b[w12, 0:3], { z0.b - z3.b }
mova za0h.b[w11, 0:3], { z0.b - z3.b }
mova za0h.b[w16, 0:3], { z0.b - z3.b }
mova za0h.b[w12, -4:-1], { z0.b - z3.b }
mova za0h.b[w12, 1:4], { z0.b - z3.b }
mova za0h.b[w12, 2:5], { z0.b - z3.b }
mova za0h.b[w12, 3:6], { z0.b - z3.b }
mova za0h.b[w12, 13:16], { z0.b - z3.b }
mova za0h.b[w12, 14:17], { z0.b - z3.b }
mova za0h.b[w12, 15:18], { z0.b - z3.b }
mova za0h.b[w12, 16:19], { z0.b - z3.b }
mova za0h.b[w12, 0], { z0.b - z3.b }
mova za0h.b[w12, 0:1], { z0.b - z3.b }
mova za0h.b[w12, 0:2], { z0.b - z3.b }
mova za0h.b[w12, 0:3, vgx2], { z0.b - z3.b }
mova za0h.b[w12, 0:3, vgx4], { z0.b - z3.b }
mova za0.b[w12, 0:3], { z0.b - z3.b }
mova za0h.h[w12, 0:3], { z1.h - z2.h }
mova za0h.h[w12, 0:3], { z2.h - z5.h }
mova za0h.h[w12, 0:3], { z3.h - z6.h }
mova za2h.h[w12, 0:3], { z0.h - z3.h }
mova za2v.h[w12, 0:3], { z0.h - z3.h }
mova za0h.h[w11, 0:3], { z0.h - z3.h }
mova za0h.h[w16, 0:3], { z0.h - z3.h }
mova za0h.h[w12, -4:-1], { z0.h - z3.h }
mova za0h.h[w12, 1:2], { z0.h - z3.h }
mova za0h.h[w12, 5:8], { z0.h - z3.h }
mova za0h.h[w12, 6:9], { z0.h - z3.h }
mova za0h.h[w12, 7:10], { z0.h - z3.h }
mova za0h.h[w12, 8:11], { z0.h - z3.h }
mova za0h.h[w12, 0], { z0.h - z3.h }
mova za0h.h[w12, 0:1], { z0.h - z3.h }
mova za0h.h[w12, 0:2], { z0.h - z3.h }
mova za0h.h[w12, 0:3, vgx2], { z0.h - z3.h }
mova za0h.h[w12, 0:3, vgx4], { z0.h - z3.h }
mova za0.h[w12, 0:3], { z0.h - z3.h }
mova za0h.s[w12, 0:3], { z1.s - z2.s }
mova za0h.s[w12, 0:3], { z2.s - z5.s }
mova za0h.s[w12, 0:3], { z3.s - z6.s }
mova za4h.s[w12, 0:3], { z0.s - z3.s }
mova za4v.s[w12, 0:3], { z0.s - z3.s }
mova za0h.s[w11, 0:3], { z0.s - z3.s }
mova za0h.s[w16, 0:3], { z0.s - z3.s }
mova za0h.s[w12, -4:-1], { z0.s - z3.s }
mova za0h.s[w12, 1:4], { z0.s - z3.s }
mova za0h.s[w12, 2:5], { z0.s - z3.s }
mova za0h.s[w12, 3:6], { z0.s - z3.s }
mova za0h.s[w12, 4:7], { z0.s - z3.s }
mova za0h.s[w12, 0], { z0.s - z3.s }
mova za0h.s[w12, 0:1], { z0.s - z3.s }
mova za0h.s[w12, 0:2], { z0.s - z3.s }
mova za0h.s[w12, 0:3, vgx2], { z0.s - z3.s }
mova za0h.s[w12, 0:3, vgx4], { z0.s - z3.s }
mova za0.s[w12, 0:3], { z0.s - z3.s }
mova za0h.d[w12, 0:3], { z1.d - z2.d }
mova za0h.d[w12, 0:3], { z2.d - z5.d }
mova za0h.d[w12, 0:3], { z3.d - z6.d }
mova za8h.d[w12, 0:3], { z0.d - z3.d }
mova za8v.d[w12, 0:3], { z0.d - z3.d }
mova za0h.d[w11, 0:3], { z0.d - z3.d }
mova za0h.d[w16, 0:3], { z0.d - z3.d }
mova za0h.d[w12, -4:-1], { z0.d - z3.d }
mova za0h.d[w12, 1:4], { z0.d - z3.d }
mova za0h.d[w12, 2:5], { z0.d - z3.d }
mova za0h.d[w12, 3:6], { z0.d - z3.d }
mova za0h.d[w12, 4:7], { z0.d - z3.d }
mova za0h.d[w12, 0], { z0.d - z3.d }
mova za0h.d[w12, 0:1], { z0.d - z3.d }
mova za0h.d[w12, 0:2], { z0.d - z3.d }
mova za0h.d[w12, 0:3, vgx2], { z0.d - z3.d }
mova za0h.d[w12, 0:3, vgx4], { z0.d - z3.d }
mova za0.d[w12, 0:3], { z0.d - z3.d }

3
gas/testsuite/gas/aarch64/sme2-1-noarch.d Normal file
View file

@ -0,0 +1,3 @@
#as: -march=armv8-a+sme
#source: sme2-1.s
#error_output: sme2-1-noarch.l

289
gas/testsuite/gas/aarch64/sme2-1-noarch.l Normal file
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@ -0,0 +1,289 @@
[^ :]+: Assembler messages:
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.b-z1\.b},za\.b\[w8,0\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.h-z1\.h},za\.h\[w8,0\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.s-z1\.s},za\.s\[w8,0\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z1\.d},za\.d\[w8,0\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z30\.d-z31\.d},za\.d\[w8,0\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z1\.d},za\.d\[w11,0\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z1\.d},za\.d\[w8,7\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.b-z3\.b},za\.b\[w8,0\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.h-z3\.h},za\.h\[w8,0\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.s-z3\.s},za\.s\[w8,0\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z3\.d},za\.d\[w8,0\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z28\.d-z31\.d},za\.d\[w8,0\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z3\.d},za\.d\[w11,0\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z3\.d},za\.d\[w8,7\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.b-z1\.b},za0h\.b\[w12,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z30\.b-z31\.b},za0h\.b\[w12,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.b-z1\.b},za0v\.b\[w12,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.b-z1\.b},za0h\.b\[w15,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.b-z1\.b},za0h\.b\[w12,14:15\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z8\.b-z9\.b},za0h\.b\[w14,6:7\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.h-z1\.h},za0h\.h\[w12,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z30\.h-z31\.h},za0h\.h\[w12,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.h-z1\.h},za0v\.h\[w12,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.h-z1\.h},za1h\.h\[w12,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.h-z1\.h},za1v\.h\[w12,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.h-z1\.h},za0h\.h\[w15,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.h-z1\.h},za0h\.h\[w12,6:7\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z10\.h-z11\.h},za0h\.h\[w13,2:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.s-z1\.s},za0h\.s\[w12,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z30\.s-z31\.s},za0h\.s\[w12,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.s-z1\.s},za0v\.s\[w12,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.s-z1\.s},za3h\.s\[w12,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.s-z1\.s},za3v\.s\[w12,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.s-z1\.s},za0h\.s\[w15,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.s-z1\.s},za0h\.s\[w12,2:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z18\.s-z19\.s},za2h\.s\[w14,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z1\.d},za0h\.d\[w12,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z30\.d-z31\.d},za0h\.d\[w12,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z1\.d},za0v\.d\[w12,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z1\.d},za7h\.d\[w12,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z1\.d},za7v\.d\[w12,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z1\.d},za0h\.d\[w15,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z22\.d-z23\.d},za6h\.d\[w13,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.b-z3\.b},za0h\.b\[w12,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z28\.b-z31\.b},za0h\.b\[w12,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.b-z3\.b},za0v\.b\[w12,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.b-z3\.b},za0h\.b\[w15,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.b-z3\.b},za0h\.b\[w12,12:15\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z12\.b-z15\.b},za0h\.b\[w14,8:11\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.h-z3\.h},za0h\.h\[w12,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z28\.h-z31\.h},za0h\.h\[w12,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.h-z3\.h},za0v\.h\[w12,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.h-z3\.h},za1h\.h\[w12,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.h-z3\.h},za1v\.h\[w12,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.h-z3\.h},za0h\.h\[w15,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.h-z3\.h},za0h\.h\[w12,4:7\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z16\.h-z19\.h},za0h\.h\[w13,4:7\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.s-z3\.s},za0h\.s\[w12,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z28\.s-z31\.s},za0h\.s\[w12,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.s-z3\.s},za0v\.s\[w12,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.s-z3\.s},za3h\.s\[w12,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.s-z3\.s},za3v\.s\[w12,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.s-z3\.s},za0h\.s\[w15,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z20\.s-z23\.s},za2h\.s\[w13,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z3\.d},za0h\.d\[w12,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z28\.d-z31\.d},za0h\.d\[w12,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z3\.d},za0v\.d\[w12,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z3\.d},za7h\.d\[w12,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z3\.d},za7v\.d\[w12,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z3\.d},za0h\.d\[w15,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov {z24\.d-z27\.d},za5h\.d\[w13,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.b\[w8,0\],{z0\.b-z1\.b}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.h\[w8,0\],{z0\.h-z1\.h}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.s\[w8,0\],{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.d\[w8,0\],{z0\.d-z1\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.d\[w11,0\],{z0\.d-z1\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.d\[w8,7\],{z0\.d-z1\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.d\[w8,0\],{z30\.d-z31\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.d\[w9,5\],{z2\.d-z3\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.b\[w8,0\],{z0\.b-z3\.b}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.h\[w8,0\],{z0\.h-z3\.h}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.s\[w8,0\],{z0\.s-z3\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.d\[w8,0\],{z0\.d-z3\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.d\[w11,0\],{z0\.d-z3\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.d\[w8,7\],{z0\.d-z3\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.d\[w8,0\],{z28\.d-z31\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.d\[w10,1\],{z20\.d-z23\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.b\[w12,0:1\],{z0\.b-z1\.b}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za0v\.b\[w12,0:1\],{z0\.b-z1\.b}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.b\[w15,0:1\],{z0\.b-z1\.b}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.b\[w12,14:15\],{z0\.b-z1\.b}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.b\[w12,0:1\],{z30\.b-z31\.b}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.b\[w14,6:7\],{z8\.b-z9\.b}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.h\[w12,0:1\],{z0\.h-z1\.h}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za0v\.h\[w12,0:1\],{z0\.h-z1\.h}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za1h\.h\[w12,0:1\],{z0\.h-z1\.h}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za1v\.h\[w12,0:1\],{z0\.h-z1\.h}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.h\[w15,0:1\],{z0\.h-z1\.h}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.h\[w12,6:7\],{z0\.h-z1\.h}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.h\[w12,0:1\],{z30\.h-z31\.h}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.h\[w13,2:3\],{z10\.h-z11\.h}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.s\[w12,0:1\],{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za0v\.s\[w12,0:1\],{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za3h\.s\[w12,0:1\],{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za3v\.s\[w12,0:1\],{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.s\[w15,0:1\],{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.s\[w12,2:3\],{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.s\[w12,0:1\],{z30\.s-z31\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za2h\.s\[w14,0:1\],{z18\.s-z19\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.d\[w12,0:1\],{z0\.d-z1\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za0v\.d\[w12,0:1\],{z0\.d-z1\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za7h\.d\[w12,0:1\],{z0\.d-z1\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za7v\.d\[w12,0:1\],{z0\.d-z1\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.d\[w15,0:1\],{z0\.d-z1\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.d\[w12,0:1\],{z30\.d-z31\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za6h\.d\[w13,0:1\],{z22\.d-z23\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.b\[w12,0:3\],{z0\.b-z3\.b}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za0v\.b\[w12,0:3\],{z0\.b-z3\.b}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.b\[w15,0:3\],{z0\.b-z3\.b}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.b\[w12,12:15\],{z0\.b-z3\.b}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.b\[w12,0:3\],{z28\.b-z31\.b}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.b\[w14,8:11\],{z12\.b-z15\.b}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.h\[w12,0:3\],{z0\.h-z3\.h}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za0v\.h\[w12,0:3\],{z0\.h-z3\.h}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za1h\.h\[w12,0:3\],{z0\.h-z3\.h}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za1v\.h\[w12,0:3\],{z0\.h-z3\.h}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.h\[w15,0:3\],{z0\.h-z3\.h}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.h\[w12,4:7\],{z0\.h-z3\.h}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.h\[w12,0:3\],{z28\.h-z31\.h}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.h\[w13,4:7\],{z16\.h-z19\.h}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.s\[w12,0:3\],{z0\.s-z3\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za0v\.s\[w12,0:3\],{z0\.s-z3\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za3h\.s\[w12,0:3\],{z0\.s-z3\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za3v\.s\[w12,0:3\],{z0\.s-z3\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.s\[w15,0:3\],{z0\.s-z3\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.s\[w12,0:3\],{z28\.s-z31\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za2h\.s\[w13,0:3\],{z20\.s-z23\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.d\[w12,0:3\],{z0\.d-z3\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za0v\.d\[w12,0:3\],{z0\.d-z3\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za7h\.d\[w12,0:3\],{z0\.d-z3\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za7v\.d\[w12,0:3\],{z0\.d-z3\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.d\[w15,0:3\],{z0\.d-z3\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.d\[w12,0:3\],{z28\.d-z31\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mov za5h\.d\[w13,0:3\],{z24\.d-z27\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.b-z1\.b},za\.b\[w8,0\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.h-z1\.h},za\.h\[w8,0\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.s-z1\.s},za\.s\[w8,0\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z1\.d},za\.d\[w8,0\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z30\.d-z31\.d},za\.d\[w8,0\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z1\.d},za\.d\[w11,0\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z1\.d},za\.d\[w8,7\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.b-z3\.b},za\.b\[w8,0\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.h-z3\.h},za\.h\[w8,0\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.s-z3\.s},za\.s\[w8,0\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z3\.d},za\.d\[w8,0\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z28\.d-z31\.d},za\.d\[w8,0\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z3\.d},za\.d\[w11,0\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z3\.d},za\.d\[w8,7\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.b-z1\.b},za0h\.b\[w12,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z30\.b-z31\.b},za0h\.b\[w12,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.b-z1\.b},za0v\.b\[w12,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.b-z1\.b},za0h\.b\[w15,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.b-z1\.b},za0h\.b\[w12,14:15\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z8\.b-z9\.b},za0h\.b\[w14,6:7\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.h-z1\.h},za0h\.h\[w12,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z30\.h-z31\.h},za0h\.h\[w12,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.h-z1\.h},za0v\.h\[w12,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.h-z1\.h},za1h\.h\[w12,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.h-z1\.h},za1v\.h\[w12,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.h-z1\.h},za0h\.h\[w15,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.h-z1\.h},za0h\.h\[w12,6:7\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z10\.h-z11\.h},za0h\.h\[w13,2:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.s-z1\.s},za0h\.s\[w12,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z30\.s-z31\.s},za0h\.s\[w12,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.s-z1\.s},za0v\.s\[w12,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.s-z1\.s},za3h\.s\[w12,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.s-z1\.s},za3v\.s\[w12,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.s-z1\.s},za0h\.s\[w15,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.s-z1\.s},za0h\.s\[w12,2:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z18\.s-z19\.s},za2h\.s\[w14,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z1\.d},za0h\.d\[w12,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z30\.d-z31\.d},za0h\.d\[w12,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z1\.d},za0v\.d\[w12,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z1\.d},za7h\.d\[w12,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z1\.d},za7v\.d\[w12,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z1\.d},za0h\.d\[w15,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z22\.d-z23\.d},za6h\.d\[w13,0:1\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.b-z3\.b},za0h\.b\[w12,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z28\.b-z31\.b},za0h\.b\[w12,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.b-z3\.b},za0v\.b\[w12,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.b-z3\.b},za0h\.b\[w15,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.b-z3\.b},za0h\.b\[w12,12:15\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z12\.b-z15\.b},za0h\.b\[w14,8:11\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.h-z3\.h},za0h\.h\[w12,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z28\.h-z31\.h},za0h\.h\[w12,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.h-z3\.h},za0v\.h\[w12,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.h-z3\.h},za1h\.h\[w12,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.h-z3\.h},za1v\.h\[w12,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.h-z3\.h},za0h\.h\[w15,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.h-z3\.h},za0h\.h\[w12,4:7\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z16\.h-z19\.h},za0h\.h\[w13,4:7\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.s-z3\.s},za0h\.s\[w12,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z28\.s-z31\.s},za0h\.s\[w12,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.s-z3\.s},za0v\.s\[w12,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.s-z3\.s},za3h\.s\[w12,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.s-z3\.s},za3v\.s\[w12,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.s-z3\.s},za0h\.s\[w15,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z20\.s-z23\.s},za2h\.s\[w13,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z3\.d},za0h\.d\[w12,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z28\.d-z31\.d},za0h\.d\[w12,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z3\.d},za0v\.d\[w12,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z3\.d},za7h\.d\[w12,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z3\.d},za7v\.d\[w12,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z3\.d},za0h\.d\[w15,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova {z24\.d-z27\.d},za5h\.d\[w13,0:3\]'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.b\[w8,0\],{z0\.b-z1\.b}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.h\[w8,0\],{z0\.h-z1\.h}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.s\[w8,0\],{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.d\[w8,0\],{z0\.d-z1\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.d\[w11,0\],{z0\.d-z1\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.d\[w8,7\],{z0\.d-z1\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.d\[w8,0\],{z30\.d-z31\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.d\[w9,5\],{z2\.d-z3\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.b\[w8,0\],{z0\.b-z3\.b}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.h\[w8,0\],{z0\.h-z3\.h}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.s\[w8,0\],{z0\.s-z3\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.d\[w8,0\],{z0\.d-z3\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.d\[w11,0\],{z0\.d-z3\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.d\[w8,7\],{z0\.d-z3\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.d\[w8,0\],{z28\.d-z31\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.d\[w10,1\],{z20\.d-z23\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.b\[w12,0:1\],{z0\.b-z1\.b}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za0v\.b\[w12,0:1\],{z0\.b-z1\.b}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.b\[w15,0:1\],{z0\.b-z1\.b}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.b\[w12,14:15\],{z0\.b-z1\.b}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.b\[w12,0:1\],{z30\.b-z31\.b}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.b\[w14,6:7\],{z8\.b-z9\.b}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.h\[w12,0:1\],{z0\.h-z1\.h}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za0v\.h\[w12,0:1\],{z0\.h-z1\.h}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za1h\.h\[w12,0:1\],{z0\.h-z1\.h}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za1v\.h\[w12,0:1\],{z0\.h-z1\.h}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.h\[w15,0:1\],{z0\.h-z1\.h}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.h\[w12,6:7\],{z0\.h-z1\.h}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.h\[w12,0:1\],{z30\.h-z31\.h}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.h\[w13,2:3\],{z10\.h-z11\.h}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.s\[w12,0:1\],{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za0v\.s\[w12,0:1\],{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za3h\.s\[w12,0:1\],{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za3v\.s\[w12,0:1\],{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.s\[w15,0:1\],{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.s\[w12,2:3\],{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.s\[w12,0:1\],{z30\.s-z31\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za2h\.s\[w14,0:1\],{z18\.s-z19\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.d\[w12,0:1\],{z0\.d-z1\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za0v\.d\[w12,0:1\],{z0\.d-z1\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za7h\.d\[w12,0:1\],{z0\.d-z1\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za7v\.d\[w12,0:1\],{z0\.d-z1\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.d\[w15,0:1\],{z0\.d-z1\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.d\[w12,0:1\],{z30\.d-z31\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za6h\.d\[w13,0:1\],{z22\.d-z23\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.b\[w12,0:3\],{z0\.b-z3\.b}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za0v\.b\[w12,0:3\],{z0\.b-z3\.b}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.b\[w15,0:3\],{z0\.b-z3\.b}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.b\[w12,12:15\],{z0\.b-z3\.b}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.b\[w12,0:3\],{z28\.b-z31\.b}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.b\[w14,8:11\],{z12\.b-z15\.b}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.h\[w12,0:3\],{z0\.h-z3\.h}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za0v\.h\[w12,0:3\],{z0\.h-z3\.h}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za1h\.h\[w12,0:3\],{z0\.h-z3\.h}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za1v\.h\[w12,0:3\],{z0\.h-z3\.h}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.h\[w15,0:3\],{z0\.h-z3\.h}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.h\[w12,4:7\],{z0\.h-z3\.h}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.h\[w12,0:3\],{z28\.h-z31\.h}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.h\[w13,4:7\],{z16\.h-z19\.h}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.s\[w12,0:3\],{z0\.s-z3\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za0v\.s\[w12,0:3\],{z0\.s-z3\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za3h\.s\[w12,0:3\],{z0\.s-z3\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za3v\.s\[w12,0:3\],{z0\.s-z3\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.s\[w15,0:3\],{z0\.s-z3\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.s\[w12,0:3\],{z28\.s-z31\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za2h\.s\[w13,0:3\],{z20\.s-z23\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.d\[w12,0:3\],{z0\.d-z3\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za0v\.d\[w12,0:3\],{z0\.d-z3\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za7h\.d\[w12,0:3\],{z0\.d-z3\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za7v\.d\[w12,0:3\],{z0\.d-z3\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.d\[w15,0:3\],{z0\.d-z3\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.d\[w12,0:3\],{z28\.d-z31\.d}'
[^ :]+:[0-9]+: Error: selected processor does not support `mova za5h\.d\[w13,0:3\],{z24\.d-z27\.d}'

305
gas/testsuite/gas/aarch64/sme2-1.d Normal file
View file

@ -0,0 +1,305 @@
#as: -march=armv8-a+sme2
#objdump: -dr
[^:]+: file format .*
[^:]+:
[^:]+:
[^:]+: c0060800 mov {z0\.d-z1\.d}, za\.d\[w8, 0, vgx2\]
[^:]+: c0060800 mov {z0\.d-z1\.d}, za\.d\[w8, 0, vgx2\]
[^:]+: c0060800 mov {z0\.d-z1\.d}, za\.d\[w8, 0, vgx2\]
[^:]+: c0060800 mov {z0\.d-z1\.d}, za\.d\[w8, 0, vgx2\]
[^:]+: c006081e mov {z30\.d-z31\.d}, za\.d\[w8, 0, vgx2\]
[^:]+: c0066800 mov {z0\.d-z1\.d}, za\.d\[w11, 0, vgx2\]
[^:]+: c00608e0 mov {z0\.d-z1\.d}, za\.d\[w8, 7, vgx2\]
[^:]+: c0060c00 mov {z0\.d-z3\.d}, za\.d\[w8, 0, vgx4\]
[^:]+: c0060c00 mov {z0\.d-z3\.d}, za\.d\[w8, 0, vgx4\]
[^:]+: c0060c00 mov {z0\.d-z3\.d}, za\.d\[w8, 0, vgx4\]
[^:]+: c0060c00 mov {z0\.d-z3\.d}, za\.d\[w8, 0, vgx4\]
[^:]+: c0060c1c mov {z28\.d-z31\.d}, za\.d\[w8, 0, vgx4\]
[^:]+: c0066c00 mov {z0\.d-z3\.d}, za\.d\[w11, 0, vgx4\]
[^:]+: c0060ce0 mov {z0\.d-z3\.d}, za\.d\[w8, 7, vgx4\]
[^:]+: c0060000 mov {z0\.b-z1\.b}, za0h\.b\[w12, 0:1\]
[^:]+: c006001e mov {z30\.b-z31\.b}, za0h\.b\[w12, 0:1\]
[^:]+: c0068000 mov {z0\.b-z1\.b}, za0v\.b\[w12, 0:1\]
[^:]+: c0066000 mov {z0\.b-z1\.b}, za0h\.b\[w15, 0:1\]
[^:]+: c00600e0 mov {z0\.b-z1\.b}, za0h\.b\[w12, 14:15\]
[^:]+: c0064068 mov {z8\.b-z9\.b}, za0h\.b\[w14, 6:7\]
[^:]+: c0460000 mov {z0\.h-z1\.h}, za0h\.h\[w12, 0:1\]
[^:]+: c046001e mov {z30\.h-z31\.h}, za0h\.h\[w12, 0:1\]
[^:]+: c0468000 mov {z0\.h-z1\.h}, za0v\.h\[w12, 0:1\]
[^:]+: c0460080 mov {z0\.h-z1\.h}, za1h\.h\[w12, 0:1\]
[^:]+: c0468080 mov {z0\.h-z1\.h}, za1v\.h\[w12, 0:1\]
[^:]+: c0466000 mov {z0\.h-z1\.h}, za0h\.h\[w15, 0:1\]
[^:]+: c0460060 mov {z0\.h-z1\.h}, za0h\.h\[w12, 6:7\]
[^:]+: c046202a mov {z10\.h-z11\.h}, za0h\.h\[w13, 2:3\]
[^:]+: c0860000 mov {z0\.s-z1\.s}, za0h\.s\[w12, 0:1\]
[^:]+: c086001e mov {z30\.s-z31\.s}, za0h\.s\[w12, 0:1\]
[^:]+: c0868000 mov {z0\.s-z1\.s}, za0v\.s\[w12, 0:1\]
[^:]+: c08600c0 mov {z0\.s-z1\.s}, za3h\.s\[w12, 0:1\]
[^:]+: c08680c0 mov {z0\.s-z1\.s}, za3v\.s\[w12, 0:1\]
[^:]+: c0866000 mov {z0\.s-z1\.s}, za0h\.s\[w15, 0:1\]
[^:]+: c0860020 mov {z0\.s-z1\.s}, za0h\.s\[w12, 2:3\]
[^:]+: c0864092 mov {z18\.s-z19\.s}, za2h\.s\[w14, 0:1\]
[^:]+: c0c60000 mov {z0\.d-z1\.d}, za0h\.d\[w12, 0:1\]
[^:]+: c0c6001e mov {z30\.d-z31\.d}, za0h\.d\[w12, 0:1\]
[^:]+: c0c68000 mov {z0\.d-z1\.d}, za0v\.d\[w12, 0:1\]
[^:]+: c0c600e0 mov {z0\.d-z1\.d}, za7h\.d\[w12, 0:1\]
[^:]+: c0c680e0 mov {z0\.d-z1\.d}, za7v\.d\[w12, 0:1\]
[^:]+: c0c66000 mov {z0\.d-z1\.d}, za0h\.d\[w15, 0:1\]
[^:]+: c0c620d6 mov {z22\.d-z23\.d}, za6h\.d\[w13, 0:1\]
[^:]+: c0060400 mov {z0\.b-z3\.b}, za0h\.b\[w12, 0:3\]
[^:]+: c006041c mov {z28\.b-z31\.b}, za0h\.b\[w12, 0:3\]
[^:]+: c0068400 mov {z0\.b-z3\.b}, za0v\.b\[w12, 0:3\]
[^:]+: c0066400 mov {z0\.b-z3\.b}, za0h\.b\[w15, 0:3\]
[^:]+: c0060460 mov {z0\.b-z3\.b}, za0h\.b\[w12, 12:15\]
[^:]+: c006444c mov {z12\.b-z15\.b}, za0h\.b\[w14, 8:11\]
[^:]+: c0460400 mov {z0\.h-z3\.h}, za0h\.h\[w12, 0:3\]
[^:]+: c046041c mov {z28\.h-z31\.h}, za0h\.h\[w12, 0:3\]
[^:]+: c0468400 mov {z0\.h-z3\.h}, za0v\.h\[w12, 0:3\]
[^:]+: c0460440 mov {z0\.h-z3\.h}, za1h\.h\[w12, 0:3\]
[^:]+: c0468440 mov {z0\.h-z3\.h}, za1v\.h\[w12, 0:3\]
[^:]+: c0466400 mov {z0\.h-z3\.h}, za0h\.h\[w15, 0:3\]
[^:]+: c0460420 mov {z0\.h-z3\.h}, za0h\.h\[w12, 4:7\]
[^:]+: c0462430 mov {z16\.h-z19\.h}, za0h\.h\[w13, 4:7\]
[^:]+: c0860400 mov {z0\.s-z3\.s}, za0h\.s\[w12, 0:3\]
[^:]+: c086041c mov {z28\.s-z31\.s}, za0h\.s\[w12, 0:3\]
[^:]+: c0868400 mov {z0\.s-z3\.s}, za0v\.s\[w12, 0:3\]
[^:]+: c0860460 mov {z0\.s-z3\.s}, za3h\.s\[w12, 0:3\]
[^:]+: c0868460 mov {z0\.s-z3\.s}, za3v\.s\[w12, 0:3\]
[^:]+: c0866400 mov {z0\.s-z3\.s}, za0h\.s\[w15, 0:3\]
[^:]+: c0862454 mov {z20\.s-z23\.s}, za2h\.s\[w13, 0:3\]
[^:]+: c0c60400 mov {z0\.d-z3\.d}, za0h\.d\[w12, 0:3\]
[^:]+: c0c6041c mov {z28\.d-z31\.d}, za0h\.d\[w12, 0:3\]
[^:]+: c0c68400 mov {z0\.d-z3\.d}, za0v\.d\[w12, 0:3\]
[^:]+: c0c604e0 mov {z0\.d-z3\.d}, za7h\.d\[w12, 0:3\]
[^:]+: c0c684e0 mov {z0\.d-z3\.d}, za7v\.d\[w12, 0:3\]
[^:]+: c0c66400 mov {z0\.d-z3\.d}, za0h\.d\[w15, 0:3\]
[^:]+: c0c624b8 mov {z24\.d-z27\.d}, za5h\.d\[w13, 0:3\]
[^:]+: c0060480 \.inst 0xc0060480 ; undefined
[^:]+: c00604e0 \.inst 0xc00604e0 ; undefined
[^:]+: c0460480 \.inst 0xc0460480 ; undefined
[^:]+: c04604e0 \.inst 0xc04604e0 ; undefined
[^:]+: c0860480 \.inst 0xc0860480 ; undefined
[^:]+: c08604e0 \.inst 0xc08604e0 ; undefined
[^:]+: c0c60480 mov {z0\.d-z3\.d}, za4h\.d\[w12, 0:3\]
[^:]+: c0c604e0 mov {z0\.d-z3\.d}, za7h\.d\[w12, 0:3\]
[^:]+: c0040800 mov za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}
[^:]+: c0040800 mov za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}
[^:]+: c0040800 mov za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}
[^:]+: c0040800 mov za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}
[^:]+: c0046800 mov za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d}
[^:]+: c0040807 mov za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d}
[^:]+: c0040bc0 mov za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d}
[^:]+: c0042845 mov za\.d\[w9, 5, vgx2\], {z2\.d-z3\.d}
[^:]+: c0040c00 mov za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}
[^:]+: c0040c00 mov za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}
[^:]+: c0040c00 mov za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}
[^:]+: c0040c00 mov za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}
[^:]+: c0046c00 mov za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d}
[^:]+: c0040c07 mov za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d}
[^:]+: c0040f80 mov za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d}
[^:]+: c0044e81 mov za\.d\[w10, 1, vgx4\], {z20\.d-z23\.d}
[^:]+: c0040000 mov za0h\.b\[w12, 0:1\], {z0\.b-z1\.b}
[^:]+: c0048000 mov za0v\.b\[w12, 0:1\], {z0\.b-z1\.b}
[^:]+: c0046000 mov za0h\.b\[w15, 0:1\], {z0\.b-z1\.b}
[^:]+: c0040007 mov za0h\.b\[w12, 14:15\], {z0\.b-z1\.b}
[^:]+: c00403c0 mov za0h\.b\[w12, 0:1\], {z30\.b-z31\.b}
[^:]+: c0044103 mov za0h\.b\[w14, 6:7\], {z8\.b-z9\.b}
[^:]+: c0440000 mov za0h\.h\[w12, 0:1\], {z0\.h-z1\.h}
[^:]+: c0448000 mov za0v\.h\[w12, 0:1\], {z0\.h-z1\.h}
[^:]+: c0440004 mov za1h\.h\[w12, 0:1\], {z0\.h-z1\.h}
[^:]+: c0448004 mov za1v\.h\[w12, 0:1\], {z0\.h-z1\.h}
[^:]+: c0446000 mov za0h\.h\[w15, 0:1\], {z0\.h-z1\.h}
[^:]+: c0440003 mov za0h\.h\[w12, 6:7\], {z0\.h-z1\.h}
[^:]+: c04403c0 mov za0h\.h\[w12, 0:1\], {z30\.h-z31\.h}
[^:]+: c0442141 mov za0h\.h\[w13, 2:3\], {z10\.h-z11\.h}
[^:]+: c0840000 mov za0h\.s\[w12, 0:1\], {z0\.s-z1\.s}
[^:]+: c0848000 mov za0v\.s\[w12, 0:1\], {z0\.s-z1\.s}
[^:]+: c0840006 mov za3h\.s\[w12, 0:1\], {z0\.s-z1\.s}
[^:]+: c0848006 mov za3v\.s\[w12, 0:1\], {z0\.s-z1\.s}
[^:]+: c0846000 mov za0h\.s\[w15, 0:1\], {z0\.s-z1\.s}
[^:]+: c0840001 mov za0h\.s\[w12, 2:3\], {z0\.s-z1\.s}
[^:]+: c08403c0 mov za0h\.s\[w12, 0:1\], {z30\.s-z31\.s}
[^:]+: c0844244 mov za2h\.s\[w14, 0:1\], {z18\.s-z19\.s}
[^:]+: c0c40000 mov za0h\.d\[w12, 0:1\], {z0\.d-z1\.d}
[^:]+: c0c48000 mov za0v\.d\[w12, 0:1\], {z0\.d-z1\.d}
[^:]+: c0c40007 mov za7h\.d\[w12, 0:1\], {z0\.d-z1\.d}
[^:]+: c0c48007 mov za7v\.d\[w12, 0:1\], {z0\.d-z1\.d}
[^:]+: c0c46000 mov za0h\.d\[w15, 0:1\], {z0\.d-z1\.d}
[^:]+: c0c403c0 mov za0h\.d\[w12, 0:1\], {z30\.d-z31\.d}
[^:]+: c0c422c6 mov za6h\.d\[w13, 0:1\], {z22\.d-z23\.d}
[^:]+: c0040400 mov za0h\.b\[w12, 0:3\], {z0\.b-z3\.b}
[^:]+: c0048400 mov za0v\.b\[w12, 0:3\], {z0\.b-z3\.b}
[^:]+: c0046400 mov za0h\.b\[w15, 0:3\], {z0\.b-z3\.b}
[^:]+: c0040403 mov za0h\.b\[w12, 12:15\], {z0\.b-z3\.b}
[^:]+: c0040780 mov za0h\.b\[w12, 0:3\], {z28\.b-z31\.b}
[^:]+: c0044582 mov za0h\.b\[w14, 8:11\], {z12\.b-z15\.b}
[^:]+: c0440400 mov za0h\.h\[w12, 0:3\], {z0\.h-z3\.h}
[^:]+: c0448400 mov za0v\.h\[w12, 0:3\], {z0\.h-z3\.h}
[^:]+: c0440402 mov za1h\.h\[w12, 0:3\], {z0\.h-z3\.h}
[^:]+: c0448402 mov za1v\.h\[w12, 0:3\], {z0\.h-z3\.h}
[^:]+: c0446400 mov za0h\.h\[w15, 0:3\], {z0\.h-z3\.h}
[^:]+: c0440401 mov za0h\.h\[w12, 4:7\], {z0\.h-z3\.h}
[^:]+: c0440780 mov za0h\.h\[w12, 0:3\], {z28\.h-z31\.h}
[^:]+: c0442601 mov za0h\.h\[w13, 4:7\], {z16\.h-z19\.h}
[^:]+: c0840400 mov za0h\.s\[w12, 0:3\], {z0\.s-z3\.s}
[^:]+: c0848400 mov za0v\.s\[w12, 0:3\], {z0\.s-z3\.s}
[^:]+: c0840403 mov za3h\.s\[w12, 0:3\], {z0\.s-z3\.s}
[^:]+: c0848403 mov za3v\.s\[w12, 0:3\], {z0\.s-z3\.s}
[^:]+: c0846400 mov za0h\.s\[w15, 0:3\], {z0\.s-z3\.s}
[^:]+: c0840780 mov za0h\.s\[w12, 0:3\], {z28\.s-z31\.s}
[^:]+: c0842682 mov za2h\.s\[w13, 0:3\], {z20\.s-z23\.s}
[^:]+: c0c40400 mov za0h\.d\[w12, 0:3\], {z0\.d-z3\.d}
[^:]+: c0c48400 mov za0v\.d\[w12, 0:3\], {z0\.d-z3\.d}
[^:]+: c0c40407 mov za7h\.d\[w12, 0:3\], {z0\.d-z3\.d}
[^:]+: c0c48407 mov za7v\.d\[w12, 0:3\], {z0\.d-z3\.d}
[^:]+: c0c46400 mov za0h\.d\[w15, 0:3\], {z0\.d-z3\.d}
[^:]+: c0c40780 mov za0h\.d\[w12, 0:3\], {z28\.d-z31\.d}
[^:]+: c0c42705 mov za5h\.d\[w13, 0:3\], {z24\.d-z27\.d}
[^:]+: c0060800 mov {z0\.d-z1\.d}, za\.d\[w8, 0, vgx2\]
[^:]+: c0060800 mov {z0\.d-z1\.d}, za\.d\[w8, 0, vgx2\]
[^:]+: c0060800 mov {z0\.d-z1\.d}, za\.d\[w8, 0, vgx2\]
[^:]+: c0060800 mov {z0\.d-z1\.d}, za\.d\[w8, 0, vgx2\]
[^:]+: c006081e mov {z30\.d-z31\.d}, za\.d\[w8, 0, vgx2\]
[^:]+: c0066800 mov {z0\.d-z1\.d}, za\.d\[w11, 0, vgx2\]
[^:]+: c00608e0 mov {z0\.d-z1\.d}, za\.d\[w8, 7, vgx2\]
[^:]+: c0060c00 mov {z0\.d-z3\.d}, za\.d\[w8, 0, vgx4\]
[^:]+: c0060c00 mov {z0\.d-z3\.d}, za\.d\[w8, 0, vgx4\]
[^:]+: c0060c00 mov {z0\.d-z3\.d}, za\.d\[w8, 0, vgx4\]
[^:]+: c0060c00 mov {z0\.d-z3\.d}, za\.d\[w8, 0, vgx4\]
[^:]+: c0060c1c mov {z28\.d-z31\.d}, za\.d\[w8, 0, vgx4\]
[^:]+: c0066c00 mov {z0\.d-z3\.d}, za\.d\[w11, 0, vgx4\]
[^:]+: c0060ce0 mov {z0\.d-z3\.d}, za\.d\[w8, 7, vgx4\]
[^:]+: c0060000 mov {z0\.b-z1\.b}, za0h\.b\[w12, 0:1\]
[^:]+: c006001e mov {z30\.b-z31\.b}, za0h\.b\[w12, 0:1\]
[^:]+: c0068000 mov {z0\.b-z1\.b}, za0v\.b\[w12, 0:1\]
[^:]+: c0066000 mov {z0\.b-z1\.b}, za0h\.b\[w15, 0:1\]
[^:]+: c00600e0 mov {z0\.b-z1\.b}, za0h\.b\[w12, 14:15\]
[^:]+: c0064068 mov {z8\.b-z9\.b}, za0h\.b\[w14, 6:7\]
[^:]+: c0460000 mov {z0\.h-z1\.h}, za0h\.h\[w12, 0:1\]
[^:]+: c046001e mov {z30\.h-z31\.h}, za0h\.h\[w12, 0:1\]
[^:]+: c0468000 mov {z0\.h-z1\.h}, za0v\.h\[w12, 0:1\]
[^:]+: c0460080 mov {z0\.h-z1\.h}, za1h\.h\[w12, 0:1\]
[^:]+: c0468080 mov {z0\.h-z1\.h}, za1v\.h\[w12, 0:1\]
[^:]+: c0466000 mov {z0\.h-z1\.h}, za0h\.h\[w15, 0:1\]
[^:]+: c0460060 mov {z0\.h-z1\.h}, za0h\.h\[w12, 6:7\]
[^:]+: c046202a mov {z10\.h-z11\.h}, za0h\.h\[w13, 2:3\]
[^:]+: c0860000 mov {z0\.s-z1\.s}, za0h\.s\[w12, 0:1\]
[^:]+: c086001e mov {z30\.s-z31\.s}, za0h\.s\[w12, 0:1\]
[^:]+: c0868000 mov {z0\.s-z1\.s}, za0v\.s\[w12, 0:1\]
[^:]+: c08600c0 mov {z0\.s-z1\.s}, za3h\.s\[w12, 0:1\]
[^:]+: c08680c0 mov {z0\.s-z1\.s}, za3v\.s\[w12, 0:1\]
[^:]+: c0866000 mov {z0\.s-z1\.s}, za0h\.s\[w15, 0:1\]
[^:]+: c0860020 mov {z0\.s-z1\.s}, za0h\.s\[w12, 2:3\]
[^:]+: c0864092 mov {z18\.s-z19\.s}, za2h\.s\[w14, 0:1\]
[^:]+: c0c60000 mov {z0\.d-z1\.d}, za0h\.d\[w12, 0:1\]
[^:]+: c0c6001e mov {z30\.d-z31\.d}, za0h\.d\[w12, 0:1\]
[^:]+: c0c68000 mov {z0\.d-z1\.d}, za0v\.d\[w12, 0:1\]
[^:]+: c0c600e0 mov {z0\.d-z1\.d}, za7h\.d\[w12, 0:1\]
[^:]+: c0c680e0 mov {z0\.d-z1\.d}, za7v\.d\[w12, 0:1\]
[^:]+: c0c66000 mov {z0\.d-z1\.d}, za0h\.d\[w15, 0:1\]
[^:]+: c0c620d6 mov {z22\.d-z23\.d}, za6h\.d\[w13, 0:1\]
[^:]+: c0060400 mov {z0\.b-z3\.b}, za0h\.b\[w12, 0:3\]
[^:]+: c006041c mov {z28\.b-z31\.b}, za0h\.b\[w12, 0:3\]
[^:]+: c0068400 mov {z0\.b-z3\.b}, za0v\.b\[w12, 0:3\]
[^:]+: c0066400 mov {z0\.b-z3\.b}, za0h\.b\[w15, 0:3\]
[^:]+: c0060460 mov {z0\.b-z3\.b}, za0h\.b\[w12, 12:15\]
[^:]+: c006444c mov {z12\.b-z15\.b}, za0h\.b\[w14, 8:11\]
[^:]+: c0460400 mov {z0\.h-z3\.h}, za0h\.h\[w12, 0:3\]
[^:]+: c046041c mov {z28\.h-z31\.h}, za0h\.h\[w12, 0:3\]
[^:]+: c0468400 mov {z0\.h-z3\.h}, za0v\.h\[w12, 0:3\]
[^:]+: c0460440 mov {z0\.h-z3\.h}, za1h\.h\[w12, 0:3\]
[^:]+: c0468440 mov {z0\.h-z3\.h}, za1v\.h\[w12, 0:3\]
[^:]+: c0466400 mov {z0\.h-z3\.h}, za0h\.h\[w15, 0:3\]
[^:]+: c0460420 mov {z0\.h-z3\.h}, za0h\.h\[w12, 4:7\]
[^:]+: c0462430 mov {z16\.h-z19\.h}, za0h\.h\[w13, 4:7\]
[^:]+: c0860400 mov {z0\.s-z3\.s}, za0h\.s\[w12, 0:3\]
[^:]+: c086041c mov {z28\.s-z31\.s}, za0h\.s\[w12, 0:3\]
[^:]+: c0868400 mov {z0\.s-z3\.s}, za0v\.s\[w12, 0:3\]
[^:]+: c0860460 mov {z0\.s-z3\.s}, za3h\.s\[w12, 0:3\]
[^:]+: c0868460 mov {z0\.s-z3\.s}, za3v\.s\[w12, 0:3\]
[^:]+: c0866400 mov {z0\.s-z3\.s}, za0h\.s\[w15, 0:3\]
[^:]+: c0862454 mov {z20\.s-z23\.s}, za2h\.s\[w13, 0:3\]
[^:]+: c0c60400 mov {z0\.d-z3\.d}, za0h\.d\[w12, 0:3\]
[^:]+: c0c6041c mov {z28\.d-z31\.d}, za0h\.d\[w12, 0:3\]
[^:]+: c0c68400 mov {z0\.d-z3\.d}, za0v\.d\[w12, 0:3\]
[^:]+: c0c604e0 mov {z0\.d-z3\.d}, za7h\.d\[w12, 0:3\]
[^:]+: c0c684e0 mov {z0\.d-z3\.d}, za7v\.d\[w12, 0:3\]
[^:]+: c0c66400 mov {z0\.d-z3\.d}, za0h\.d\[w15, 0:3\]
[^:]+: c0c624b8 mov {z24\.d-z27\.d}, za5h\.d\[w13, 0:3\]
[^:]+: c0040800 mov za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}
[^:]+: c0040800 mov za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}
[^:]+: c0040800 mov za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}
[^:]+: c0040800 mov za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}
[^:]+: c0046800 mov za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d}
[^:]+: c0040807 mov za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d}
[^:]+: c0040bc0 mov za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d}
[^:]+: c0042845 mov za\.d\[w9, 5, vgx2\], {z2\.d-z3\.d}
[^:]+: c0040c00 mov za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}
[^:]+: c0040c00 mov za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}
[^:]+: c0040c00 mov za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}
[^:]+: c0040c00 mov za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}
[^:]+: c0046c00 mov za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d}
[^:]+: c0040c07 mov za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d}
[^:]+: c0040f80 mov za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d}
[^:]+: c0044e81 mov za\.d\[w10, 1, vgx4\], {z20\.d-z23\.d}
[^:]+: c0040000 mov za0h\.b\[w12, 0:1\], {z0\.b-z1\.b}
[^:]+: c0048000 mov za0v\.b\[w12, 0:1\], {z0\.b-z1\.b}
[^:]+: c0046000 mov za0h\.b\[w15, 0:1\], {z0\.b-z1\.b}
[^:]+: c0040007 mov za0h\.b\[w12, 14:15\], {z0\.b-z1\.b}
[^:]+: c00403c0 mov za0h\.b\[w12, 0:1\], {z30\.b-z31\.b}
[^:]+: c0044103 mov za0h\.b\[w14, 6:7\], {z8\.b-z9\.b}
[^:]+: c0440000 mov za0h\.h\[w12, 0:1\], {z0\.h-z1\.h}
[^:]+: c0448000 mov za0v\.h\[w12, 0:1\], {z0\.h-z1\.h}
[^:]+: c0440004 mov za1h\.h\[w12, 0:1\], {z0\.h-z1\.h}
[^:]+: c0448004 mov za1v\.h\[w12, 0:1\], {z0\.h-z1\.h}
[^:]+: c0446000 mov za0h\.h\[w15, 0:1\], {z0\.h-z1\.h}
[^:]+: c0440003 mov za0h\.h\[w12, 6:7\], {z0\.h-z1\.h}
[^:]+: c04403c0 mov za0h\.h\[w12, 0:1\], {z30\.h-z31\.h}
[^:]+: c0442141 mov za0h\.h\[w13, 2:3\], {z10\.h-z11\.h}
[^:]+: c0840000 mov za0h\.s\[w12, 0:1\], {z0\.s-z1\.s}
[^:]+: c0848000 mov za0v\.s\[w12, 0:1\], {z0\.s-z1\.s}
[^:]+: c0840006 mov za3h\.s\[w12, 0:1\], {z0\.s-z1\.s}
[^:]+: c0848006 mov za3v\.s\[w12, 0:1\], {z0\.s-z1\.s}
[^:]+: c0846000 mov za0h\.s\[w15, 0:1\], {z0\.s-z1\.s}
[^:]+: c0840001 mov za0h\.s\[w12, 2:3\], {z0\.s-z1\.s}
[^:]+: c08403c0 mov za0h\.s\[w12, 0:1\], {z30\.s-z31\.s}
[^:]+: c0844244 mov za2h\.s\[w14, 0:1\], {z18\.s-z19\.s}
[^:]+: c0c40000 mov za0h\.d\[w12, 0:1\], {z0\.d-z1\.d}
[^:]+: c0c48000 mov za0v\.d\[w12, 0:1\], {z0\.d-z1\.d}
[^:]+: c0c40007 mov za7h\.d\[w12, 0:1\], {z0\.d-z1\.d}
[^:]+: c0c48007 mov za7v\.d\[w12, 0:1\], {z0\.d-z1\.d}
[^:]+: c0c46000 mov za0h\.d\[w15, 0:1\], {z0\.d-z1\.d}
[^:]+: c0c403c0 mov za0h\.d\[w12, 0:1\], {z30\.d-z31\.d}
[^:]+: c0c422c6 mov za6h\.d\[w13, 0:1\], {z22\.d-z23\.d}
[^:]+: c0040400 mov za0h\.b\[w12, 0:3\], {z0\.b-z3\.b}
[^:]+: c0048400 mov za0v\.b\[w12, 0:3\], {z0\.b-z3\.b}
[^:]+: c0046400 mov za0h\.b\[w15, 0:3\], {z0\.b-z3\.b}
[^:]+: c0040403 mov za0h\.b\[w12, 12:15\], {z0\.b-z3\.b}
[^:]+: c0040780 mov za0h\.b\[w12, 0:3\], {z28\.b-z31\.b}
[^:]+: c0044582 mov za0h\.b\[w14, 8:11\], {z12\.b-z15\.b}
[^:]+: c0440400 mov za0h\.h\[w12, 0:3\], {z0\.h-z3\.h}
[^:]+: c0448400 mov za0v\.h\[w12, 0:3\], {z0\.h-z3\.h}
[^:]+: c0440402 mov za1h\.h\[w12, 0:3\], {z0\.h-z3\.h}
[^:]+: c0448402 mov za1v\.h\[w12, 0:3\], {z0\.h-z3\.h}
[^:]+: c0446400 mov za0h\.h\[w15, 0:3\], {z0\.h-z3\.h}
[^:]+: c0440401 mov za0h\.h\[w12, 4:7\], {z0\.h-z3\.h}
[^:]+: c0440780 mov za0h\.h\[w12, 0:3\], {z28\.h-z31\.h}
[^:]+: c0442601 mov za0h\.h\[w13, 4:7\], {z16\.h-z19\.h}
[^:]+: c0840400 mov za0h\.s\[w12, 0:3\], {z0\.s-z3\.s}
[^:]+: c0848400 mov za0v\.s\[w12, 0:3\], {z0\.s-z3\.s}
[^:]+: c0840403 mov za3h\.s\[w12, 0:3\], {z0\.s-z3\.s}
[^:]+: c0848403 mov za3v\.s\[w12, 0:3\], {z0\.s-z3\.s}
[^:]+: c0846400 mov za0h\.s\[w15, 0:3\], {z0\.s-z3\.s}
[^:]+: c0840780 mov za0h\.s\[w12, 0:3\], {z28\.s-z31\.s}
[^:]+: c0842682 mov za2h\.s\[w13, 0:3\], {z20\.s-z23\.s}
[^:]+: c0c40400 mov za0h\.d\[w12, 0:3\], {z0\.d-z3\.d}
[^:]+: c0c48400 mov za0v\.d\[w12, 0:3\], {z0\.d-z3\.d}
[^:]+: c0c40407 mov za7h\.d\[w12, 0:3\], {z0\.d-z3\.d}
[^:]+: c0c48407 mov za7v\.d\[w12, 0:3\], {z0\.d-z3\.d}
[^:]+: c0c46400 mov za0h\.d\[w15, 0:3\], {z0\.d-z3\.d}
[^:]+: c0c40780 mov za0h\.d\[w12, 0:3\], {z28\.d-z31\.d}
[^:]+: c0c42705 mov za5h\.d\[w13, 0:3\], {z24\.d-z27\.d}

338
gas/testsuite/gas/aarch64/sme2-1.s Normal file
View file

@ -0,0 +1,338 @@
mov { z0.b - z1.b }, za.b[w8, 0]
mov { z0.h - z1.h }, za.h[w8, 0]
mov { z0.s - z1.s }, za.s[w8, 0]
mov { z0.d - z1.d }, za.d[w8, 0]
mov { z30.d - z31.d }, za.d[w8, 0]
mov { z0.d - z1.d }, za.d[w11, 0]
mov { z0.d - z1.d }, za.d[w8, 7]
mov { z0.b - z3.b }, za.b[w8, 0]
mov { z0.h - z3.h }, za.h[w8, 0]
mov { z0.s - z3.s }, za.s[w8, 0]
mov { z0.d - z3.d }, za.d[w8, 0]
mov { z28.d - z31.d }, za.d[w8, 0]
mov { z0.d - z3.d }, za.d[w11, 0]
mov { z0.d - z3.d }, za.d[w8, 7]
mov { z0.b - z1.b }, za0h.b[w12, 0:1]
mov { z30.b - z31.b }, za0h.b[w12, 0:1]
mov { z0.b - z1.b }, za0v.b[w12, 0:1]
mov { z0.b - z1.b }, za0h.b[w15, 0:1]
mov { z0.b - z1.b }, za0h.b[w12, 14:15]
mov { z8.b - z9.b }, za0h.b[w14, 6:7]
mov { z0.h - z1.h }, za0h.h[w12, 0:1]
mov { z30.h - z31.h }, za0h.h[w12, 0:1]
mov { z0.h - z1.h }, za0v.h[w12, 0:1]
mov { z0.h - z1.h }, za1h.h[w12, 0:1]
mov { z0.h - z1.h }, za1v.h[w12, 0:1]
mov { z0.h - z1.h }, za0h.h[w15, 0:1]
mov { z0.h - z1.h }, za0h.h[w12, 6:7]
mov { z10.h - z11.h }, za0h.h[w13, 2:3]
mov { z0.s - z1.s }, za0h.s[w12, 0:1]
mov { z30.s - z31.s }, za0h.s[w12, 0:1]
mov { z0.s - z1.s }, za0v.s[w12, 0:1]
mov { z0.s - z1.s }, za3h.s[w12, 0:1]
mov { z0.s - z1.s }, za3v.s[w12, 0:1]
mov { z0.s - z1.s }, za0h.s[w15, 0:1]
mov { z0.s - z1.s }, za0h.s[w12, 2:3]
mov { z18.s - z19.s }, za2h.s[w14, 0:1]
mov { z0.d - z1.d }, za0h.d[w12, 0:1]
mov { z30.d - z31.d }, za0h.d[w12, 0:1]
mov { z0.d - z1.d }, za0v.d[w12, 0:1]
mov { z0.d - z1.d }, za7h.d[w12, 0:1]
mov { z0.d - z1.d }, za7v.d[w12, 0:1]
mov { z0.d - z1.d }, za0h.d[w15, 0:1]
mov { z22.d - z23.d }, za6h.d[w13, 0:1]
mov { z0.b - z3.b }, za0h.b[w12, 0:3]
mov { z28.b - z31.b }, za0h.b[w12, 0:3]
mov { z0.b - z3.b }, za0v.b[w12, 0:3]
mov { z0.b - z3.b }, za0h.b[w15, 0:3]
mov { z0.b - z3.b }, za0h.b[w12, 12:15]
mov { z12.b - z15.b }, za0h.b[w14, 8:11]
mov { z0.h - z3.h }, za0h.h[w12, 0:3]
mov { z28.h - z31.h }, za0h.h[w12, 0:3]
mov { z0.h - z3.h }, za0v.h[w12, 0:3]
mov { z0.h - z3.h }, za1h.h[w12, 0:3]
mov { z0.h - z3.h }, za1v.h[w12, 0:3]
mov { z0.h - z3.h }, za0h.h[w15, 0:3]
mov { z0.h - z3.h }, za0h.h[w12, 4:7]
mov { z16.h - z19.h }, za0h.h[w13, 4:7]
mov { z0.s - z3.s }, za0h.s[w12, 0:3]
mov { z28.s - z31.s }, za0h.s[w12, 0:3]
mov { z0.s - z3.s }, za0v.s[w12, 0:3]
mov { z0.s - z3.s }, za3h.s[w12, 0:3]
mov { z0.s - z3.s }, za3v.s[w12, 0:3]
mov { z0.s - z3.s }, za0h.s[w15, 0:3]
mov { z20.s - z23.s }, za2h.s[w13, 0:3]
mov { z0.d - z3.d }, za0h.d[w12, 0:3]
mov { z28.d - z31.d }, za0h.d[w12, 0:3]
mov { z0.d - z3.d }, za0v.d[w12, 0:3]
mov { z0.d - z3.d }, za7h.d[w12, 0:3]
mov { z0.d - z3.d }, za7v.d[w12, 0:3]
mov { z0.d - z3.d }, za0h.d[w15, 0:3]
mov { z24.d - z27.d }, za5h.d[w13, 0:3]
// Invalid MOVAs
.inst 0xc0060480
.inst 0xc00604e0
.inst 0xc0460480
.inst 0xc04604e0
.inst 0xc0860480
.inst 0xc08604e0
// Valid MOVAs
.inst 0xc0c60480
.inst 0xc0c604e0
mov za.b[w8, 0], { z0.b - z1.b }
mov za.h[w8, 0], { z0.h - z1.h }
mov za.s[w8, 0], { z0.s - z1.s }
mov za.d[w8, 0], { z0.d - z1.d }
mov za.d[w11, 0], { z0.d - z1.d }
mov za.d[w8, 7], { z0.d - z1.d }
mov za.d[w8, 0], { z30.d - z31.d }
mov za.d[w9, 5], { z2.d - z3.d }
mov za.b[w8, 0], { z0.b - z3.b }
mov za.h[w8, 0], { z0.h - z3.h }
mov za.s[w8, 0], { z0.s - z3.s }
mov za.d[w8, 0], { z0.d - z3.d }
mov za.d[w11, 0], { z0.d - z3.d }
mov za.d[w8, 7], { z0.d - z3.d }
mov za.d[w8, 0], { z28.d - z31.d }
mov za.d[w10, 1], { z20.d - z23.d }
mov za0h.b[w12, 0:1], { z0.b - z1.b }
mov za0v.b[w12, 0:1], { z0.b - z1.b }
mov za0h.b[w15, 0:1], { z0.b - z1.b }
mov za0h.b[w12, 14:15], { z0.b - z1.b }
mov za0h.b[w12, 0:1], { z30.b - z31.b }
mov za0h.b[w14, 6:7], { z8.b - z9.b }
mov za0h.h[w12, 0:1], { z0.h - z1.h }
mov za0v.h[w12, 0:1], { z0.h - z1.h }
mov za1h.h[w12, 0:1], { z0.h - z1.h }
mov za1v.h[w12, 0:1], { z0.h - z1.h }
mov za0h.h[w15, 0:1], { z0.h - z1.h }
mov za0h.h[w12, 6:7], { z0.h - z1.h }
mov za0h.h[w12, 0:1], { z30.h - z31.h }
mov za0h.h[w13, 2:3], { z10.h - z11.h }
mov za0h.s[w12, 0:1], { z0.s - z1.s }
mov za0v.s[w12, 0:1], { z0.s - z1.s }
mov za3h.s[w12, 0:1], { z0.s - z1.s }
mov za3v.s[w12, 0:1], { z0.s - z1.s }
mov za0h.s[w15, 0:1], { z0.s - z1.s }
mov za0h.s[w12, 2:3], { z0.s - z1.s }
mov za0h.s[w12, 0:1], { z30.s - z31.s }
mov za2h.s[w14, 0:1], { z18.s - z19.s }
mov za0h.d[w12, 0:1], { z0.d - z1.d }
mov za0v.d[w12, 0:1], { z0.d - z1.d }
mov za7h.d[w12, 0:1], { z0.d - z1.d }
mov za7v.d[w12, 0:1], { z0.d - z1.d }
mov za0h.d[w15, 0:1], { z0.d - z1.d }
mov za0h.d[w12, 0:1], { z30.d - z31.d }
mov za6h.d[w13, 0:1], { z22.d - z23.d }
mov za0h.b[w12, 0:3], { z0.b - z3.b }
mov za0v.b[w12, 0:3], { z0.b - z3.b }
mov za0h.b[w15, 0:3], { z0.b - z3.b }
mov za0h.b[w12, 12:15], { z0.b - z3.b }
mov za0h.b[w12, 0:3], { z28.b - z31.b }
mov za0h.b[w14, 8:11], { z12.b - z15.b }
mov za0h.h[w12, 0:3], { z0.h - z3.h }
mov za0v.h[w12, 0:3], { z0.h - z3.h }
mov za1h.h[w12, 0:3], { z0.h - z3.h }
mov za1v.h[w12, 0:3], { z0.h - z3.h }
mov za0h.h[w15, 0:3], { z0.h - z3.h }
mov za0h.h[w12, 4:7], { z0.h - z3.h }
mov za0h.h[w12, 0:3], { z28.h - z31.h }
mov za0h.h[w13, 4:7], { z16.h - z19.h }
mov za0h.s[w12, 0:3], { z0.s - z3.s }
mov za0v.s[w12, 0:3], { z0.s - z3.s }
mov za3h.s[w12, 0:3], { z0.s - z3.s }
mov za3v.s[w12, 0:3], { z0.s - z3.s }
mov za0h.s[w15, 0:3], { z0.s - z3.s }
mov za0h.s[w12, 0:3], { z28.s - z31.s }
mov za2h.s[w13, 0:3], { z20.s - z23.s }
mov za0h.d[w12, 0:3], { z0.d - z3.d }
mov za0v.d[w12, 0:3], { z0.d - z3.d }
mov za7h.d[w12, 0:3], { z0.d - z3.d }
mov za7v.d[w12, 0:3], { z0.d - z3.d }
mov za0h.d[w15, 0:3], { z0.d - z3.d }
mov za0h.d[w12, 0:3], { z28.d - z31.d }
mov za5h.d[w13, 0:3], { z24.d - z27.d }
mova { z0.b - z1.b }, za.b[w8, 0]
mova { z0.h - z1.h }, za.h[w8, 0]
mova { z0.s - z1.s }, za.s[w8, 0]
mova { z0.d - z1.d }, za.d[w8, 0]
mova { z30.d - z31.d }, za.d[w8, 0]
mova { z0.d - z1.d }, za.d[w11, 0]
mova { z0.d - z1.d }, za.d[w8, 7]
mova { z0.b - z3.b }, za.b[w8, 0]
mova { z0.h - z3.h }, za.h[w8, 0]
mova { z0.s - z3.s }, za.s[w8, 0]
mova { z0.d - z3.d }, za.d[w8, 0]
mova { z28.d - z31.d }, za.d[w8, 0]
mova { z0.d - z3.d }, za.d[w11, 0]
mova { z0.d - z3.d }, za.d[w8, 7]
mova { z0.b - z1.b }, za0h.b[w12, 0:1]
mova { z30.b - z31.b }, za0h.b[w12, 0:1]
mova { z0.b - z1.b }, za0v.b[w12, 0:1]
mova { z0.b - z1.b }, za0h.b[w15, 0:1]
mova { z0.b - z1.b }, za0h.b[w12, 14:15]
mova { z8.b - z9.b }, za0h.b[w14, 6:7]
mova { z0.h - z1.h }, za0h.h[w12, 0:1]
mova { z30.h - z31.h }, za0h.h[w12, 0:1]
mova { z0.h - z1.h }, za0v.h[w12, 0:1]
mova { z0.h - z1.h }, za1h.h[w12, 0:1]
mova { z0.h - z1.h }, za1v.h[w12, 0:1]
mova { z0.h - z1.h }, za0h.h[w15, 0:1]
mova { z0.h - z1.h }, za0h.h[w12, 6:7]
mova { z10.h - z11.h }, za0h.h[w13, 2:3]
mova { z0.s - z1.s }, za0h.s[w12, 0:1]
mova { z30.s - z31.s }, za0h.s[w12, 0:1]
mova { z0.s - z1.s }, za0v.s[w12, 0:1]
mova { z0.s - z1.s }, za3h.s[w12, 0:1]
mova { z0.s - z1.s }, za3v.s[w12, 0:1]
mova { z0.s - z1.s }, za0h.s[w15, 0:1]
mova { z0.s - z1.s }, za0h.s[w12, 2:3]
mova { z18.s - z19.s }, za2h.s[w14, 0:1]
mova { z0.d - z1.d }, za0h.d[w12, 0:1]
mova { z30.d - z31.d }, za0h.d[w12, 0:1]
mova { z0.d - z1.d }, za0v.d[w12, 0:1]
mova { z0.d - z1.d }, za7h.d[w12, 0:1]
mova { z0.d - z1.d }, za7v.d[w12, 0:1]
mova { z0.d - z1.d }, za0h.d[w15, 0:1]
mova { z22.d - z23.d }, za6h.d[w13, 0:1]
mova { z0.b - z3.b }, za0h.b[w12, 0:3]
mova { z28.b - z31.b }, za0h.b[w12, 0:3]
mova { z0.b - z3.b }, za0v.b[w12, 0:3]
mova { z0.b - z3.b }, za0h.b[w15, 0:3]
mova { z0.b - z3.b }, za0h.b[w12, 12:15]
mova { z12.b - z15.b }, za0h.b[w14, 8:11]
mova { z0.h - z3.h }, za0h.h[w12, 0:3]
mova { z28.h - z31.h }, za0h.h[w12, 0:3]
mova { z0.h - z3.h }, za0v.h[w12, 0:3]
mova { z0.h - z3.h }, za1h.h[w12, 0:3]
mova { z0.h - z3.h }, za1v.h[w12, 0:3]
mova { z0.h - z3.h }, za0h.h[w15, 0:3]
mova { z0.h - z3.h }, za0h.h[w12, 4:7]
mova { z16.h - z19.h }, za0h.h[w13, 4:7]
mova { z0.s - z3.s }, za0h.s[w12, 0:3]
mova { z28.s - z31.s }, za0h.s[w12, 0:3]
mova { z0.s - z3.s }, za0v.s[w12, 0:3]
mova { z0.s - z3.s }, za3h.s[w12, 0:3]
mova { z0.s - z3.s }, za3v.s[w12, 0:3]
mova { z0.s - z3.s }, za0h.s[w15, 0:3]
mova { z20.s - z23.s }, za2h.s[w13, 0:3]
mova { z0.d - z3.d }, za0h.d[w12, 0:3]
mova { z28.d - z31.d }, za0h.d[w12, 0:3]
mova { z0.d - z3.d }, za0v.d[w12, 0:3]
mova { z0.d - z3.d }, za7h.d[w12, 0:3]
mova { z0.d - z3.d }, za7v.d[w12, 0:3]
mova { z0.d - z3.d }, za0h.d[w15, 0:3]
mova { z24.d - z27.d }, za5h.d[w13, 0:3]
mova za.b[w8, 0], { z0.b - z1.b }
mova za.h[w8, 0], { z0.h - z1.h }
mova za.s[w8, 0], { z0.s - z1.s }
mova za.d[w8, 0], { z0.d - z1.d }
mova za.d[w11, 0], { z0.d - z1.d }
mova za.d[w8, 7], { z0.d - z1.d }
mova za.d[w8, 0], { z30.d - z31.d }
mova za.d[w9, 5], { z2.d - z3.d }
mova za.b[w8, 0], { z0.b - z3.b }
mova za.h[w8, 0], { z0.h - z3.h }
mova za.s[w8, 0], { z0.s - z3.s }
mova za.d[w8, 0], { z0.d - z3.d }
mova za.d[w11, 0], { z0.d - z3.d }
mova za.d[w8, 7], { z0.d - z3.d }
mova za.d[w8, 0], { z28.d - z31.d }
mova za.d[w10, 1], { z20.d - z23.d }
mova za0h.b[w12, 0:1], { z0.b - z1.b }
mova za0v.b[w12, 0:1], { z0.b - z1.b }
mova za0h.b[w15, 0:1], { z0.b - z1.b }
mova za0h.b[w12, 14:15], { z0.b - z1.b }
mova za0h.b[w12, 0:1], { z30.b - z31.b }
mova za0h.b[w14, 6:7], { z8.b - z9.b }
mova za0h.h[w12, 0:1], { z0.h - z1.h }
mova za0v.h[w12, 0:1], { z0.h - z1.h }
mova za1h.h[w12, 0:1], { z0.h - z1.h }
mova za1v.h[w12, 0:1], { z0.h - z1.h }
mova za0h.h[w15, 0:1], { z0.h - z1.h }
mova za0h.h[w12, 6:7], { z0.h - z1.h }
mova za0h.h[w12, 0:1], { z30.h - z31.h }
mova za0h.h[w13, 2:3], { z10.h - z11.h }
mova za0h.s[w12, 0:1], { z0.s - z1.s }
mova za0v.s[w12, 0:1], { z0.s - z1.s }
mova za3h.s[w12, 0:1], { z0.s - z1.s }
mova za3v.s[w12, 0:1], { z0.s - z1.s }
mova za0h.s[w15, 0:1], { z0.s - z1.s }
mova za0h.s[w12, 2:3], { z0.s - z1.s }
mova za0h.s[w12, 0:1], { z30.s - z31.s }
mova za2h.s[w14, 0:1], { z18.s - z19.s }
mova za0h.d[w12, 0:1], { z0.d - z1.d }
mova za0v.d[w12, 0:1], { z0.d - z1.d }
mova za7h.d[w12, 0:1], { z0.d - z1.d }
mova za7v.d[w12, 0:1], { z0.d - z1.d }
mova za0h.d[w15, 0:1], { z0.d - z1.d }
mova za0h.d[w12, 0:1], { z30.d - z31.d }
mova za6h.d[w13, 0:1], { z22.d - z23.d }
mova za0h.b[w12, 0:3], { z0.b - z3.b }
mova za0v.b[w12, 0:3], { z0.b - z3.b }
mova za0h.b[w15, 0:3], { z0.b - z3.b }
mova za0h.b[w12, 12:15], { z0.b - z3.b }
mova za0h.b[w12, 0:3], { z28.b - z31.b }
mova za0h.b[w14, 8:11], { z12.b - z15.b }
mova za0h.h[w12, 0:3], { z0.h - z3.h }
mova za0v.h[w12, 0:3], { z0.h - z3.h }
mova za1h.h[w12, 0:3], { z0.h - z3.h }
mova za1v.h[w12, 0:3], { z0.h - z3.h }
mova za0h.h[w15, 0:3], { z0.h - z3.h }
mova za0h.h[w12, 4:7], { z0.h - z3.h }
mova za0h.h[w12, 0:3], { z28.h - z31.h }
mova za0h.h[w13, 4:7], { z16.h - z19.h }
mova za0h.s[w12, 0:3], { z0.s - z3.s }
mova za0v.s[w12, 0:3], { z0.s - z3.s }
mova za3h.s[w12, 0:3], { z0.s - z3.s }
mova za3v.s[w12, 0:3], { z0.s - z3.s }
mova za0h.s[w15, 0:3], { z0.s - z3.s }
mova za0h.s[w12, 0:3], { z28.s - z31.s }
mova za2h.s[w13, 0:3], { z20.s - z23.s }
mova za0h.d[w12, 0:3], { z0.d - z3.d }
mova za0v.d[w12, 0:3], { z0.d - z3.d }
mova za7h.d[w12, 0:3], { z0.d - z3.d }
mova za7v.d[w12, 0:3], { z0.d - z3.d }
mova za0h.d[w15, 0:3], { z0.d - z3.d }
mova za0h.d[w12, 0:3], { z28.d - z31.d }
mova za5h.d[w13, 0:3], { z24.d - z27.d }

10
include/opcode/aarch64.h
View file

@ -485,13 +485,21 @@ enum aarch64_opnd
AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */
AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */
AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */
AARCH64_OPND_SME_Zdnx2, /* SVE vector register list from [4:1]*2. */
AARCH64_OPND_SME_Zdnx4, /* SVE vector register list from [4:2]*4. */
AARCH64_OPND_SME_Znx2, /* SVE vector register list from [9:6]*2. */
AARCH64_OPND_SME_Znx4, /* SVE vector register list from [9:7]*4. */
AARCH64_OPND_SME_ZAda_2b, /* SME <ZAda>.S, 2-bits. */
AARCH64_OPND_SME_ZAda_3b, /* SME <ZAda>.D, 3-bits. */
AARCH64_OPND_SME_ZA_HV_idx_src, /* SME source ZA tile vector. */
AARCH64_OPND_SME_ZA_HV_idx_srcxN, /* SME N source ZA tile vectors. */
AARCH64_OPND_SME_ZA_HV_idx_dest, /* SME destination ZA tile vector. */
AARCH64_OPND_SME_ZA_HV_idx_destxN, /* SME N dest ZA tile vectors. */
AARCH64_OPND_SME_Pm, /* SME scalable predicate register, bits [15:13]. */
AARCH64_OPND_SME_list_of_64bit_tiles, /* SME list of ZA tiles. */
AARCH64_OPND_SME_ZA_HV_idx_ldstr, /* SME destination ZA tile vector. */
AARCH64_OPND_SME_ZA_array_off3_0, /* SME ZA[<Wv>{, #<imm3>}]. */
AARCH64_OPND_SME_ZA_array_off3_5, /* SME ZA[<Wv>{, #<imm3>}]. */
AARCH64_OPND_SME_ZA_array_off4, /* SME ZA[<Wv>{, #<imm>}]. */
AARCH64_OPND_SME_ADDR_RI_U4xVL, /* SME [<Xn|SP>{, #<imm>, MUL VL}]. */
AARCH64_OPND_SME_SM_ZA, /* SME {SM | ZA}. */
@ -669,9 +677,11 @@ enum aarch64_insn_class
sme_mov,
sme_ldr,
sme_psel,
sme_size_22,
sme_str,
sme_start,
sme_stop,
sme2_mov,
sve_cpy,
sve_index,
sve_limm,

34
opcodes/aarch64-asm-2.c
View file

@ -667,9 +667,9 @@ aarch64_insert_operand (const aarch64_operand *self,
case 203:
case 209:
case 212:
case 214:
case 215:
case 218:
case 219:
case 224:
return aarch64_ins_regno (self, info, code, inst, errors);
case 15:
return aarch64_ins_reg_extended (self, info, code, inst, errors);
@ -681,7 +681,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 33:
case 34:
case 35:
case 226:
case 234:
return aarch64_ins_reglane (self, info, code, inst, errors);
case 36:
return aarch64_ins_reglist (self, info, code, inst, errors);
@ -726,10 +726,10 @@ aarch64_insert_operand (const aarch64_operand *self,
case 192:
case 193:
case 194:
case 219:
case 225:
case 230:
case 231:
case 233:
case 238:
case 239:
return aarch64_ins_imm (self, info, code, inst, errors);
case 44:
case 45:
@ -889,21 +889,31 @@ aarch64_insert_operand (const aarch64_operand *self,
case 211:
case 213:
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
case 214:
case 215:
case 216:
case 217:
return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
case 220:
case 222:
case 226:
return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
case 221:
return aarch64_ins_sme_za_array (self, info, code, inst, errors);
case 222:
return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
case 223:
return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
case 224:
return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors);
case 227:
case 228:
case 229:
return aarch64_ins_sme_za_array (self, info, code, inst, errors);
case 230:
return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
case 231:
return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
case 232:
return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
case 235:
case 236:
case 237:
return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
default: assert (0); abort ();
}

50
opcodes/aarch64-asm.c
View file

@ -1167,6 +1167,19 @@ aarch64_ins_sve_aimm (const aarch64_operand *self,
return true;
}
bool
aarch64_ins_sve_aligned_reglist (const aarch64_operand *self,
const aarch64_opnd_info *info,
aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
{
unsigned int num_regs = get_operand_specific_data (self);
unsigned int val = info->reglist.first_regno;
insert_field (self->fields[0], code, val / num_regs, 0);
return true;
}
/* Encode an SVE CPY/DUP immediate. */
bool
aarch64_ins_sve_asimm (const aarch64_operand *self,
@ -1384,6 +1397,35 @@ aarch64_ins_sme_za_hv_tiles (const aarch64_operand *self,
return true;
}
bool
aarch64_ins_sme_za_hv_tiles_range (const aarch64_operand *self,
const aarch64_opnd_info *info,
aarch64_insn *code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
aarch64_operand_error *errors
ATTRIBUTE_UNUSED)
{
int ebytes = aarch64_get_qualifier_esize (info->qualifier);
int range_size = get_opcode_dependent_value (inst->opcode);
int fld_v = info->indexed_za.v;
int fld_rv = info->indexed_za.index.regno - 12;
int imm = info->indexed_za.index.imm;
int max_value = 16 / range_size / ebytes;
if (max_value == 0)
max_value = 1;
assert (imm % range_size == 0 && (imm / range_size) < max_value);
int fld_zan_imm = (info->indexed_za.regno * max_value) | (imm / range_size);
assert (fld_zan_imm < (range_size == 4 && ebytes < 8 ? 4 : 8));
insert_field (self->fields[0], code, fld_v, 0);
insert_field (self->fields[1], code, fld_rv, 0);
insert_field (self->fields[2], code, fld_zan_imm, 0);
return true;
}
/* Encode in SME instruction ZERO list of up to eight 64-bit element tile names
separated by commas, encoded in the "imm8" field.
@ -1410,7 +1452,7 @@ aarch64_ins_sme_za_array (const aarch64_operand *self,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
{
int regno = info->indexed_za.index.regno - 12;
int regno = info->indexed_za.index.regno & 3;
int imm = info->indexed_za.index.imm;
insert_field (self->fields[0], code, regno, 0);
insert_field (self->fields[1], code, imm, 0);
@ -1858,6 +1900,11 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
/* The variant is encoded as part of the immediate. */
break;
case sme_size_22:
insert_field (FLD_SME_size_22, &inst->value,
aarch64_get_variant (inst), 0);
break;
case sve_cpy:
insert_fields (&inst->value, aarch64_get_variant (inst),
0, 2, FLD_SVE_M_14, FLD_size);
@ -1873,6 +1920,7 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
break;
case sve_limm:
case sme2_mov:
/* For sve_limm, the .B, .H, and .S forms are just a convenience
and depend on the immediate. They don't have a separate
encoding. */

2
opcodes/aarch64-asm.h
View file

@ -87,6 +87,7 @@ AARCH64_DECL_OPD_INSERTER (ins_sve_addr_zz_lsl);
AARCH64_DECL_OPD_INSERTER (ins_sve_addr_zz_sxtw);
AARCH64_DECL_OPD_INSERTER (ins_sve_addr_zz_uxtw);
AARCH64_DECL_OPD_INSERTER (ins_sve_aimm);
AARCH64_DECL_OPD_INSERTER (ins_sve_aligned_reglist);
AARCH64_DECL_OPD_INSERTER (ins_sve_asimm);
AARCH64_DECL_OPD_INSERTER (ins_sve_float_half_one);
AARCH64_DECL_OPD_INSERTER (ins_sve_float_half_two);
@ -99,6 +100,7 @@ AARCH64_DECL_OPD_INSERTER (ins_sve_scale);
AARCH64_DECL_OPD_INSERTER (ins_sve_shlimm);
AARCH64_DECL_OPD_INSERTER (ins_sve_shrimm);
AARCH64_DECL_OPD_INSERTER (ins_sme_za_hv_tiles);
AARCH64_DECL_OPD_INSERTER (ins_sme_za_hv_tiles_range);
AARCH64_DECL_OPD_INSERTER (ins_sme_za_list);
AARCH64_DECL_OPD_INSERTER (ins_sme_za_array);
AARCH64_DECL_OPD_INSERTER (ins_sme_addr_ri_u4xvl);

702
opcodes/aarch64-dis-2.c
View file

File diff suppressed because it is too large Load diff

60
opcodes/aarch64-dis.c
View file

@ -1715,6 +1715,20 @@ aarch64_ext_sve_aimm (const aarch64_operand *self,
&& decode_sve_aimm (info, (uint8_t) info->imm.value));
}
bool
aarch64_ext_sve_aligned_reglist (const aarch64_operand *self,
aarch64_opnd_info *info, aarch64_insn code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
{
unsigned int num_regs = get_operand_specific_data (self);
unsigned int val = extract_field (self->fields[0], code, 0);
info->reglist.first_regno = val * num_regs;
info->reglist.num_regs = num_regs;
info->reglist.stride = 1;
return true;
}
/* Decode an SVE CPY/DUP immediate. */
bool
aarch64_ext_sve_asimm (const aarch64_operand *self,
@ -1823,6 +1837,36 @@ aarch64_ext_sme_za_hv_tiles (const aarch64_operand *self,
return true;
}
bool
aarch64_ext_sme_za_hv_tiles_range (const aarch64_operand *self,
aarch64_opnd_info *info, aarch64_insn code,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
aarch64_operand_error *errors
ATTRIBUTE_UNUSED)
{
int ebytes = aarch64_get_qualifier_esize (info->qualifier);
int range_size = get_opcode_dependent_value (inst->opcode);
int fld_v = extract_field (self->fields[0], code, 0);
int fld_rv = extract_field (self->fields[1], code, 0);
int fld_zan_imm = extract_field (self->fields[2], code, 0);
int max_value = 16 / range_size / ebytes;
if (max_value == 0)
max_value = 1;
int regno = fld_zan_imm / max_value;
if (regno >= ebytes)
return false;
info->indexed_za.regno = regno;
info->indexed_za.index.imm = (fld_zan_imm % max_value) * range_size;
info->indexed_za.index.countm1 = range_size - 1;
info->indexed_za.index.regno = fld_rv + 12;
info->indexed_za.v = fld_v;
return true;
}
/* Decode in SME instruction ZERO list of up to eight 64-bit element tile names
separated by commas, encoded in the "imm8" field.
@ -1850,10 +1894,15 @@ aarch64_ext_sme_za_array (const aarch64_operand *self,
const aarch64_inst *inst ATTRIBUTE_UNUSED,
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
{
int regno = extract_field (self->fields[0], code, 0) + 12;
int regno = extract_field (self->fields[0], code, 0);
if (info->type == AARCH64_OPND_SME_ZA_array_off4)
regno += 12;
else
regno += 8;
int imm = extract_field (self->fields[1], code, 0);
info->indexed_za.index.regno = regno;
info->indexed_za.index.imm = imm;
info->indexed_za.group_size = get_opcode_dependent_value (inst->opcode);
return true;
}
@ -2979,6 +3028,10 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst)
}
break;
case sme_size_22:
variant = extract_field (FLD_SME_size_22, inst->value, 0);
break;
case sve_cpy:
variant = extract_fields (inst->value, 0, 2, FLD_size, FLD_SVE_M_14);
break;
@ -3006,6 +3059,11 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst)
variant = 3;
break;
case sme2_mov:
/* .D is preferred over the other sizes in disassembly. */
variant = 3;
break;
case sme_misc:
case sve_misc:
/* These instructions have only a single variant. */

2
opcodes/aarch64-dis.h
View file

@ -111,6 +111,7 @@ AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_zz_lsl);
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_zz_sxtw);
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_zz_uxtw);
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_aimm);
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_aligned_reglist);
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_asimm);
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_float_half_one);
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_float_half_two);
@ -123,6 +124,7 @@ AARCH64_DECL_OPD_EXTRACTOR (ext_sve_scale);
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_shlimm);
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_shrimm);
AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_hv_tiles);
AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_hv_tiles_range);
AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_list);
AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_array);
AARCH64_DECL_OPD_EXTRACTOR (ext_sme_addr_ri_u4xvl);

8
opcodes/aarch64-opc-2.c
View file

@ -238,13 +238,21 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_SVE_REGLIST, "SVE_ZnxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "a list of SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REG, "SVE_Zt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "an SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REGLIST, "SVE_ZtxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zdnx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zdn2}, "a list of SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zdnx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zdn4}, "a list of SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zn2}, "a list of SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zn4}, "a list of SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_2b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZAda_2b}, "an SME ZA tile ZA0-ZA3"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_3b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZAda_3b}, "an SME ZA tile ZA0-ZA7"},
{AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_src", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_22,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_5}, "an SME horizontal or vertical vector access register"},
{AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_srcxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_V,FLD_SME_Rv,FLD_imm3_5}, "an SME horizontal or vertical vector access register"},
{AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_dest", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_22,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_0}, "an SME horizontal or vertical vector access register"},
{AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_destxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_V,FLD_SME_Rv,FLD_imm3_0}, "an SME horizontal or vertical vector access register"},
{AARCH64_OPND_CLASS_PRED_REG, "SME_Pm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Pm}, "an SVE predicate register"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_list_of_64bit_tiles", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_zero_mask}, "a list of 64-bit ZA element tiles"},
{AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_ldstr", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_22,FLD_index2,FLD_SME_V,FLD_SME_Rv,FLD_imm4_0}, "an SME horizontal or vertical vector access register"},
{AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off3_0", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rv,FLD_imm3_0}, "ZA array"},
{AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off3_5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rv,FLD_imm3_5}, "ZA array"},
{AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rv,FLD_imm4_0}, "ZA array"},
{AARCH64_OPND_CLASS_ADDRESS, "SME_ADDR_RI_U4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm4_0}, "memory offset"},
{AARCH64_OPND_CLASS_ADDRESS, "SME_SM_ZA", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "streaming mode"},

79
opcodes/aarch64-opc.c
View file

@ -227,6 +227,10 @@ const aarch64_field fields[] =
{ 15, 1 }, /* SME_V: (horizontal / vertical tiles), bit 15. */
{ 0, 2 }, /* SME_ZAda_2b: tile ZA0-ZA3. */
{ 0, 3 }, /* SME_ZAda_3b: tile ZA0-ZA7. */
{ 1, 4 }, /* SME_Zdn2: Z0-Z31, multiple of 2, bits [4:1]. */
{ 2, 3 }, /* SME_Zdn4: Z0-Z31, multiple of 4, bits [4:2]. */
{ 6, 4 }, /* SME_Zn2: Z0-Z31, multiple of 2, bits [9:6]. */
{ 7, 3 }, /* SME_Zn4: Z0-Z31, multiple of 4, bits [9:7]. */
{ 23, 1 }, /* SME_i1: immediate field, bit 23. */
{ 22, 2 }, /* SME_size_22: size<1>, size<0> class field, [23:22]. */
{ 22, 1 }, /* SME_tszh: immediate and qualifier field, bit 22. */
@ -296,6 +300,8 @@ const aarch64_field fields[] =
{ 0, 4 }, /* cond2: condition in truly conditional-executed inst. */
{ 5, 5 }, /* defgh: d:e:f:g:h bits in AdvSIMD modified immediate. */
{ 21, 2 }, /* hw: in move wide constant instructions. */
{ 0, 3 }, /* imm3_0: general immediate in bits [2:0]. */
{ 5, 3 }, /* imm3_5: general immediate in bits [7:5]. */
{ 10, 3 }, /* imm3_10: in add/sub extended reg instructions. */
{ 0, 4 }, /* imm4_0: in rmif instructions. */
{ 5, 4 }, /* imm4_5: in SME instructions. */
@ -1546,6 +1552,10 @@ check_za_access (const aarch64_opnd_info *opnd,
set_other_error (mismatch_detail, idx,
_("expected a selection register in the"
" range w12-w15"));
else if (min_wreg == 8)
set_other_error (mismatch_detail, idx,
_("expected a selection register in the"
" range w8-w11"));
else
abort ();
return false;
@ -1574,6 +1584,12 @@ check_za_access (const aarch64_opnd_info *opnd,
set_other_error (mismatch_detail, idx,
_("expected a single offset rather than"
" a range"));
else if (range_size == 2)
set_other_error (mismatch_detail, idx,
_("expected a range of two offsets"));
else if (range_size == 4)
set_other_error (mismatch_detail, idx,
_("expected a range of four offsets"));
else
abort ();
return false;
@ -1715,9 +1731,33 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
break;
case AARCH64_OPND_CLASS_SVE_REGLIST:
num = get_opcode_dependent_value (opcode);
if (!check_reglist (opnd, mismatch_detail, idx, num, 1))
return 0;
switch (type)
{
case AARCH64_OPND_SME_Zdnx2:
case AARCH64_OPND_SME_Zdnx4:
case AARCH64_OPND_SME_Znx2:
case AARCH64_OPND_SME_Znx4:
num = get_operand_specific_data (&aarch64_operands[type]);
if (!check_reglist (opnd, mismatch_detail, idx, num, 1))
return 0;
if ((opnd->reglist.first_regno % num) != 0)
{
set_other_error (mismatch_detail, idx,
_("start register out of range"));
return 0;
}
break;
case AARCH64_OPND_SVE_ZnxN:
case AARCH64_OPND_SVE_ZtxN:
num = get_opcode_dependent_value (opcode);
if (!check_reglist (opnd, mismatch_detail, idx, num, 1))
return 0;
break;
default:
abort ();
}
break;
case AARCH64_OPND_CLASS_ZA_ACCESS:
@ -1739,6 +1779,25 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
return 0;
break;
case AARCH64_OPND_SME_ZA_array_off3_0:
case AARCH64_OPND_SME_ZA_array_off3_5:
if (!check_za_access (opnd, mismatch_detail, idx, 8, 7, 1,
get_opcode_dependent_value (opcode)))
return 0;
break;
case AARCH64_OPND_SME_ZA_HV_idx_srcxN:
case AARCH64_OPND_SME_ZA_HV_idx_destxN:
size = aarch64_get_qualifier_esize (opnd->qualifier);
num = get_opcode_dependent_value (opcode);
max_value = 16 / num / size;
if (max_value > 0)
max_value -= 1;
if (!check_za_access (opnd, mismatch_detail, idx,
12, max_value, num, 0))
return 0;
break;
default:
abort ();
}
@ -3709,6 +3768,10 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
case AARCH64_OPND_SVE_ZnxN:
case AARCH64_OPND_SVE_ZtxN:
case AARCH64_OPND_SME_Zdnx2:
case AARCH64_OPND_SME_Zdnx4:
case AARCH64_OPND_SME_Znx2:
case AARCH64_OPND_SME_Znx4:
print_register_list (buf, size, opnd, "z", styler);
break;
@ -3732,7 +3795,9 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
break;
case AARCH64_OPND_SME_ZA_HV_idx_src:
case AARCH64_OPND_SME_ZA_HV_idx_srcxN:
case AARCH64_OPND_SME_ZA_HV_idx_dest:
case AARCH64_OPND_SME_ZA_HV_idx_destxN:
case AARCH64_OPND_SME_ZA_HV_idx_ldstr:
snprintf (buf, size, "%s%s[%s, %s%s%s%s%s]%s",
opnd->type == AARCH64_OPND_SME_ZA_HV_idx_ldstr ? "{" : "",
@ -3760,9 +3825,15 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
print_sme_za_list (buf, size, opnd->reg.regno, styler);
break;
case AARCH64_OPND_SME_ZA_array_off3_0:
case AARCH64_OPND_SME_ZA_array_off3_5:
case AARCH64_OPND_SME_ZA_array_off4:
snprintf (buf, size, "%s[%s, %s%s%s%s%s]",
style_reg (styler, "za"),
style_reg (styler, "za%s%s",
opnd->qualifier == AARCH64_OPND_QLF_NIL ? "" : ".",
(opnd->qualifier == AARCH64_OPND_QLF_NIL
? ""
: aarch64_get_qualifier_name (opnd->qualifier))),
style_reg (styler, "w%d", opnd->indexed_za.index.regno),
style_imm (styler, "%" PRIi64, opnd->indexed_za.index.imm),
opnd->indexed_za.index.countm1 ? ":" : "",

6
opcodes/aarch64-opc.h
View file

@ -55,6 +55,10 @@ enum aarch64_field_kind
FLD_SME_V,
FLD_SME_ZAda_2b,
FLD_SME_ZAda_3b,
FLD_SME_Zdn2,
FLD_SME_Zdn4,
FLD_SME_Zn2,
FLD_SME_Zn4,
FLD_SME_i1,
FLD_SME_size_22,
FLD_SME_tszh,
@ -124,6 +128,8 @@ enum aarch64_field_kind
FLD_cond2,
FLD_defgh,
FLD_hw,
FLD_imm3_0,
FLD_imm3_5,
FLD_imm3_10,
FLD_imm4_0,
FLD_imm4_5,

43
opcodes/aarch64-tbl.h
View file

@ -2477,6 +2477,9 @@ static const aarch64_feature_set aarch64_feature_sme_f64f64 =
static const aarch64_feature_set aarch64_feature_sme_i16i64 =
AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SME
| AARCH64_FEATURE_SME_I16I64, 0);
static const aarch64_feature_set aarch64_feature_sme2 =
AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SME
| AARCH64_FEATURE_SME2, 0);
static const aarch64_feature_set aarch64_feature_v8_6 =
AARCH64_FEATURE (AARCH64_FEATURE_V8_6, 0);
static const aarch64_feature_set aarch64_feature_v8_7 =
@ -2545,6 +2548,7 @@ static const aarch64_feature_set aarch64_feature_cssc =
#define SME &aarch64_feature_sme
#define SME_F64F64 &aarch64_feature_sme_f64f64
#define SME_I16I64 &aarch64_feature_sme_i16i64
#define SME2 &aarch64_feature_sme2
#define ARMV8_6 &aarch64_feature_v8_6
#define ARMV8_6_SVE &aarch64_feature_v8_6
#define BFLOAT16_SVE &aarch64_feature_bfloat16_sve
@ -2656,6 +2660,9 @@ static const aarch64_feature_set aarch64_feature_cssc =
#define SME_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
{ NAME, OPCODE, MASK, CLASS, OP, SME, OPS, QUALS, \
F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL }
#define SME2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
{ NAME, OPCODE, MASK, CLASS, OP, SME2, OPS, QUALS, \
F_STRICT | FLAGS, 0, TIED, NULL }
#define SVE2BITPERM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
{ NAME, OPCODE, MASK, CLASS, OP, SVE2_BITPERM, OPS, QUALS, \
FLAGS | F_STRICT, 0, TIED, NULL }
@ -5278,6 +5285,24 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SME_INSN ("psel", 0x25204000, 0xff20c210, sme_psel, 0, OP3 (SVE_Pd, SVE_Pg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, 0, 0),
SME_INSN ("psel", 0x25204000, 0xff20c210, sme_psel, 0, OP3 (SVE_PNd, SVE_PNg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, 0, 0),
/* SME2 extensions to SME. */
SME2_INSN ("mov", 0xc0060800, 0xffff9f01, sme2_mov, 0, OP2 (SME_Zdnx2, SME_ZA_array_off3_5), OP_SVE_VV_BHSD, F_OD (2), 0),
SME2_INSN ("mov", 0xc0060c00, 0xffff9f03, sme2_mov, 0, OP2 (SME_Zdnx4, SME_ZA_array_off3_5), OP_SVE_VV_BHSD, F_OD (4), 0),
SME2_INSN ("mov", 0xc0060000, 0xff3f1f01, sme_size_22, 0, OP2 (SME_Zdnx2, SME_ZA_HV_idx_srcxN), OP_SVE_VV_BHSDQ, F_OD (2), 0),
SME2_INSN ("mov", 0xc0060400, 0xff3f1f03, sme_size_22, 0, OP2 (SME_Zdnx4, SME_ZA_HV_idx_srcxN), OP_SVE_VV_BHSDQ, F_OD (4), 0),
SME2_INSN ("mov", 0xc0040800, 0xffff9c38, sme2_mov, 0, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_VV_BHSD, F_OD (2), 0),
SME2_INSN ("mov", 0xc0040c00, 0xffff9c78, sme2_mov, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VV_BHSD, F_OD (4), 0),
SME2_INSN ("mov", 0xc0040000, 0xff3f1c38, sme_size_22, 0, OP2 (SME_ZA_HV_idx_destxN, SME_Znx2), OP_SVE_VV_BHSDQ, F_OD (2), 0),
SME2_INSN ("mov", 0xc0040400, 0xff3f1c78, sme_size_22, 0, OP2 (SME_ZA_HV_idx_destxN, SME_Znx4), OP_SVE_VV_BHSDQ, F_OD (4), 0),
SME2_INSN ("mova", 0xc0060800, 0xffff9f01, sme2_mov, 0, OP2 (SME_Zdnx2, SME_ZA_array_off3_5), OP_SVE_VV_BHSD, F_OD (2), 0),
SME2_INSN ("mova", 0xc0060c00, 0xffff9f03, sme2_mov, 0, OP2 (SME_Zdnx4, SME_ZA_array_off3_5), OP_SVE_VV_BHSD, F_OD (4), 0),
SME2_INSN ("mova", 0xc0060000, 0xff3f1f01, sme_size_22, 0, OP2 (SME_Zdnx2, SME_ZA_HV_idx_srcxN), OP_SVE_VV_BHSDQ, F_OD (2), 0),
SME2_INSN ("mova", 0xc0060400, 0xff3f1f03, sme_size_22, 0, OP2 (SME_Zdnx4, SME_ZA_HV_idx_srcxN), OP_SVE_VV_BHSDQ, F_OD (4), 0),
SME2_INSN ("mova", 0xc0040800, 0xffff9c38, sme2_mov, 0, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_VV_BHSD, F_OD (2), 0),
SME2_INSN ("mova", 0xc0040c00, 0xffff9c78, sme2_mov, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VV_BHSD, F_OD (4), 0),
SME2_INSN ("mova", 0xc0040000, 0xff3f1c38, sme_size_22, 0, OP2 (SME_ZA_HV_idx_destxN, SME_Znx2), OP_SVE_VV_BHSDQ, F_OD (2), 0),
SME2_INSN ("mova", 0xc0040400, 0xff3f1c78, sme_size_22, 0, OP2 (SME_ZA_HV_idx_destxN, SME_Znx4), OP_SVE_VV_BHSDQ, F_OD (4), 0),
/* SIMD Dot Product (optional in v8.2-A). */
DOT_INSN ("udot", 0x2e009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ),
DOT_INSN ("sdot", 0xe009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ),
@ -5917,6 +5942,14 @@ const struct aarch64_opcode aarch64_opcode_table[] =
"an SVE vector register") \
Y(SVE_REGLIST, sve_reglist, "SVE_ZtxN", 0, F(FLD_SVE_Zt), \
"a list of SVE vector registers") \
Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zdnx2", 2 << OPD_F_OD_LSB, \
F(FLD_SME_Zdn2), "a list of SVE vector registers") \
Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zdnx4", 4 << OPD_F_OD_LSB, \
F(FLD_SME_Zdn4), "a list of SVE vector registers") \
Y(SVE_REGLIST, sve_aligned_reglist, "SME_Znx2", 2 << OPD_F_OD_LSB, \
F(FLD_SME_Zn2), "a list of SVE vector registers") \
Y(SVE_REGLIST, sve_aligned_reglist, "SME_Znx4", 4 << OPD_F_OD_LSB, \
F(FLD_SME_Zn4), "a list of SVE vector registers") \
Y(SVE_REG, regno, "SME_ZAda_2b", 0, F(FLD_SME_ZAda_2b), \
"an SME ZA tile ZA0-ZA3") \
Y(SVE_REG, regno, "SME_ZAda_3b", 0, F(FLD_SME_ZAda_3b), \
@ -5924,9 +5957,15 @@ const struct aarch64_opcode aarch64_opcode_table[] =
Y(ZA_ACCESS, sme_za_hv_tiles, "SME_ZA_HV_idx_src", 0, \
F(FLD_SME_size_22,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_5), \
"an SME horizontal or vertical vector access register") \
Y(ZA_ACCESS, sme_za_hv_tiles_range, "SME_ZA_HV_idx_srcxN", 0, \
F(FLD_SME_V,FLD_SME_Rv,FLD_imm3_5), \
"an SME horizontal or vertical vector access register") \
Y(ZA_ACCESS, sme_za_hv_tiles, "SME_ZA_HV_idx_dest", 0, \
F(FLD_SME_size_22,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_0), \
"an SME horizontal or vertical vector access register") \
Y(ZA_ACCESS, sme_za_hv_tiles_range, "SME_ZA_HV_idx_destxN", 0, \
F(FLD_SME_V,FLD_SME_Rv,FLD_imm3_0), \
"an SME horizontal or vertical vector access register") \
Y(PRED_REG, regno, "SME_Pm", 0, F(FLD_SME_Pm), \
"an SVE predicate register") \
Y(SVE_REG, imm, "SME_list_of_64bit_tiles", 0, \
@ -5934,6 +5973,10 @@ const struct aarch64_opcode aarch64_opcode_table[] =
Y(ZA_ACCESS, sme_za_hv_tiles, "SME_ZA_HV_idx_ldstr", 0, \
F(FLD_SME_size_22,FLD_index2,FLD_SME_V,FLD_SME_Rv,FLD_imm4_0), \
"an SME horizontal or vertical vector access register") \
Y(ZA_ACCESS, sme_za_array, "SME_ZA_array_off3_0", 0, \
F(FLD_SME_Rv,FLD_imm3_0), "ZA array") \
Y(ZA_ACCESS, sme_za_array, "SME_ZA_array_off3_5", 0, \
F(FLD_SME_Rv,FLD_imm3_5), "ZA array") \
Y(ZA_ACCESS, sme_za_array, "SME_ZA_array_off4", 0, \
F(FLD_SME_Rv,FLD_imm4_0), "ZA array") \
Y(ADDRESS, sme_addr_ri_u4xvl, "SME_ADDR_RI_U4xVL", 0 << OPD_F_OD_LSB, \