[AArch64] Add separate feature flag for weaker release consistent load insns
The weaker release consistency support of ARMv8.3-A is allowed as an optional extension for ARMv8.2-A, so separate command line option and feature flag is added: -march=armv8.2-a+rcpc turns LDAPR, LDAPRB, LDAPRH instructions on. opcodes/ * aarch64-tbl.h (RCPC, RCPC_INSN): Define. (aarch64_opcode_table): Use RCPC_INSN. include/ * opcode/aarch64.h (AARCH64_FEATURE_RCPC): Define. (AARCH64_ARCH_V8_3): Update. gas/ * config/tc-aarch64.c (aarch64_features): Add rcpc. * doc/c-aarch64.texi (AArch64 Extensions): Document rcpc. * testsuite/gas/aarch64/ldst-exclusive-armv8_3.d: Rename to ... * testsuite/gas/aarch64/ldst-rcpc.d: This. * testsuite/gas/aarch64/ldst-exclusive-armv8_3.s: Rename to ... * testsuite/gas/aarch64/ldst-rcpc.s: This. * testsuite/gas/aarch64/ldst-rcpc-armv8_2.d: New test.
This commit is contained in:
Szabolcs Nagy
parent
10ab38d930
commit
d74d4880e2
9 changed files with 54 additions and 4 deletions
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@ -1,3 +1,13 @@
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2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
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* config/tc-aarch64.c (aarch64_features): Add rcpc.
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* doc/c-aarch64.texi (AArch64 Extensions): Document rcpc.
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* testsuite/gas/aarch64/ldst-exclusive-armv8_3.d: Rename to ...
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* testsuite/gas/aarch64/ldst-rcpc.d: This.
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* testsuite/gas/aarch64/ldst-exclusive-armv8_3.s: Rename to ...
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* testsuite/gas/aarch64/ldst-rcpc.s: This.
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* testsuite/gas/aarch64/ldst-rcpc-armv8_2.d: New test.
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2017-01-04 Norm Jacobs <norm.jacobs@oracle.com>
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PR gas/20992
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@ -8438,6 +8438,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
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{"sve", AARCH64_FEATURE (AARCH64_FEATURE_SVE, 0),
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AARCH64_FEATURE (AARCH64_FEATURE_FP
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| AARCH64_FEATURE_SIMD, 0)},
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{"rcpc", AARCH64_FEATURE (AARCH64_FEATURE_RCPC, 0),
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AARCH64_ARCH_NONE},
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{NULL, AARCH64_ARCH_NONE, AARCH64_ARCH_NONE},
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};
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21
gas/testsuite/gas/aarch64/ldst-rcpc-armv8_2.d
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21
gas/testsuite/gas/aarch64/ldst-rcpc-armv8_2.d
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@ -0,0 +1,21 @@
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#objdump: -dr
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#as: -march=armv8.2-a+rcpc
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#source: ldst-rcpc.s
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.*: file format .*
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Disassembly of section \.text:
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0+ <.*>:
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0: 38bfc0e1 ldaprb w1, \[x7\]
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4: 38bfc0e1 ldaprb w1, \[x7\]
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8: 38bfc0e1 ldaprb w1, \[x7\]
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c: 78bfc0e1 ldaprh w1, \[x7\]
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10: 78bfc0e1 ldaprh w1, \[x7\]
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14: 78bfc0e1 ldaprh w1, \[x7\]
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18: b8bfc0e1 ldapr w1, \[x7\]
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1c: b8bfc0e1 ldapr w1, \[x7\]
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20: b8bfc0e1 ldapr w1, \[x7\]
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24: f8bfc0e1 ldapr x1, \[x7\]
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28: f8bfc0e1 ldapr x1, \[x7\]
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2c: f8bfc0e1 ldapr x1, \[x7\]
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@ -1,3 +1,8 @@
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2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
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* opcode/aarch64.h (AARCH64_FEATURE_RCPC): Define.
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(AARCH64_ARCH_V8_3): Update.
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2017-01-03 Kito Cheng <kito.cheng@gmail.com>
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* opcode/riscv-opc.h: Add support for the "q" ISA extension.
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@ -53,6 +53,7 @@ typedef uint32_t aarch64_insn;
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#define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */
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#define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */
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#define AARCH64_FEATURE_SVE 0x10000000 /* SVE instructions. */
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#define AARCH64_FEATURE_RCPC 0x20000000 /* RCPC instructions. */
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/* Architectures are the sum of the base and extensions. */
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#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
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@ -70,7 +71,8 @@ typedef uint32_t aarch64_insn;
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| AARCH64_FEATURE_F16 \
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| AARCH64_FEATURE_RAS)
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#define AARCH64_ARCH_V8_3 AARCH64_FEATURE (AARCH64_ARCH_V8_2, \
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AARCH64_FEATURE_V8_3)
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AARCH64_FEATURE_V8_3 \
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| AARCH64_FEATURE_RCPC)
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#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
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#define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
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@ -1,3 +1,8 @@
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2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
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* aarch64-tbl.h (RCPC, RCPC_INSN): Define.
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(aarch64_opcode_table): Use RCPC_INSN.
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2017-01-03 Kito Cheng <kito.cheng@gmail.com>
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* riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
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@ -1940,6 +1940,8 @@ static const aarch64_feature_set aarch64_feature_fp_v8_3 =
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AARCH64_FEATURE (AARCH64_FEATURE_V8_3 | AARCH64_FEATURE_FP, 0);
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static const aarch64_feature_set aarch64_feature_simd_v8_3 =
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AARCH64_FEATURE (AARCH64_FEATURE_V8_3 | AARCH64_FEATURE_SIMD, 0);
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static const aarch64_feature_set aarch64_feature_rcpc =
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AARCH64_FEATURE (AARCH64_FEATURE_RCPC, 0);
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#define CORE &aarch64_feature_v8
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#define FP &aarch64_feature_fp
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@ -1958,6 +1960,7 @@ static const aarch64_feature_set aarch64_feature_simd_v8_3 =
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#define ARMV8_3 &aarch64_feature_v8_3
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#define FP_V8_3 &aarch64_feature_fp_v8_3
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#define SIMD_V8_3 &aarch64_feature_simd_v8_3
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#define RCPC &aarch64_feature_rcpc
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#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
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{ NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, NULL }
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@ -1986,6 +1989,8 @@ static const aarch64_feature_set aarch64_feature_simd_v8_3 =
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FLAGS | F_STRICT, TIED, NULL }
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#define V8_3_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
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{ NAME, OPCODE, MASK, CLASS, 0, ARMV8_3, OPS, QUALS, FLAGS, 0, NULL }
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#define RCPC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
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{ NAME, OPCODE, MASK, CLASS, 0, RCPC, OPS, QUALS, FLAGS, 0, NULL }
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struct aarch64_opcode aarch64_opcode_table[] =
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{
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@ -2982,9 +2987,9 @@ struct aarch64_opcode aarch64_opcode_table[] =
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CORE_INSN ("ldaxp", 0x887f8000, 0xbfe08000, ldstexcl, 0, OP3 (Rt, Rt2, ADDR_SIMPLE), QL_R2NIL, F_GPRSIZE_IN_Q),
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CORE_INSN ("stlr", 0x889ffc00, 0xbfe08000, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q),
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CORE_INSN ("ldar", 0x88dffc00, 0xbfeffc00, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q),
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V8_3_INSN ("ldaprb", 0x38bfc000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0),
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V8_3_INSN ("ldaprh", 0x78bfc000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0),
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V8_3_INSN ("ldapr", 0xb8bfc000, 0xbffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q),
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RCPC_INSN ("ldaprb", 0x38bfc000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0),
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RCPC_INSN ("ldaprh", 0x78bfc000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0),
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RCPC_INSN ("ldapr", 0xb8bfc000, 0xbffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q),
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/* Limited Ordering Regions load/store instructions. */
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_LOR_INSN ("ldlar", 0x88df7c00, 0xbfe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q),
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_LOR_INSN ("ldlarb", 0x08df7c00, 0xffe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0),
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