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Contribute sh64-elf.

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2001-10-08  Nick Clifton  <nickc@cambridge.redhat.com>
* sh64-opc.c: Regenerate.
2001-03-13  DJ Delorie  <dj@redhat.com>
* sh64-opc.h: Rename A_RESV_Fx to A_REUSE_PREV so that its
purpose is more obvious.
* sh64-opc.c (shmedia_table): Ditto.
* sh64-dis.c (initialize_shmedia_opcode_mask_table): Ditto.
(print_insn_shmedia): Ditto.
2001-03-12  DJ Delorie  <dj@redhat.com>
* sh64-opc.c: Adjust comments to reflect reality: replace bits
3:0 with zeros (not "reserved"), replace "rrrrrr" with
"gggggg" for two-operand floating point opcodes.  Remove
"fsina".
2001-01-08  Hans-Peter Nilsson  <hpn@cygnus.com>
* sh64-dis.c (print_insn_shmedia) <failing read_memory_func>:
Correct printing of .byte:s.  Return number of printed bytes or
-1; never 0.
(print_insn_sh64x) <not CRT_SH5_ISA16>: Ditto.  Print as .byte:s
to next four-byte-alignment if insn or data is not aligned.
2001-01-06  Hans-Peter Nilsson  <hpn@cygnus.com>
* sh64-dis.c: Update comments and fix comment formatting.
(initialize_shmedia_opcode_mask_table) <case A_IMMM>:
Abort instead of setting length to 0.
(crange_qsort_cmpb, crange_qsort_cmpl, crange_bsearch_cmpb,
crange_bsearch_cmpl, sh64_get_contents_type,
sh64_address_in_cranges): Move to bfd/elf32-sh64.c.
2001-01-05  Hans-Peter Nilsson  <hpn@cygnus.com>
* sh64-opc.c: Remove #if 0:d entries for instructions not found in
SH-5/ST50-023-04: fcosa.s, fsrra.s and prefo.
2000-12-30  Hans-Peter Nilsson  <hpn@cygnus.com>
* sh64-dis.c (print_insn_shmedia): Display MOVI/SHORI-formed
address with same prefix as SHcompact.
In the disassembler, use a .cranges section for linked executables.
* sh64-dis.c (SAVED_MOVI_R, SAVED_MOVI_IMM): Move to head of file
and update for using structure in info->private_data.
(struct sh64_disassemble_info): New.
(is_shmedia_p): Delete.
(crange_qsort_cmpb): New function.
(crange_qsort_cmpl, crange_bsearch_cmpb): New functions.
(crange_bsearch_cmpl, sh64_address_in_cranges): New functions.
(init_sh64_disasm_info, sh64_get_contents_type_disasm): New functions.
(sh64_get_contents_type, sh64_address_is_shmedia): New functions.
(print_insn_shmedia): Correct displaying of address after MOVI/SHORI
pair.  Display addresses for linked executables only.
(print_insn_sh64x_media): Initialize info->private_data by calling
init_sh64_disasm_info.
(print_insn_sh64x): Ditto.  Find out type of contents by calling
sh64_contents_type_disasm.  Display data regions using ".long" and
".byte" similar to unrecognized opcodes.
2000-12-19  Hans-Peter Nilsson  <hpn@cygnus.com>
* sh64-dis.c (is_shmedia_p): Check info->section and look for ISA
information in section flags before considering symbols.  Don't
assume an info->mach setting of bfd_mach_sh5 means SHmedia code.
* configure.in (bfd_sh_arch): Check presence of sh64 insns by
matching $target $canon_targets instead of looking at the
now-removed -DINCLUDE_SHMEDIA in $targ_cflags.
* configure: Regenerate.
2000-11-25  Hans-Peter Nilsson  <hpn@cygnus.com>
* sh64-opc.c (shmedia_creg_table): New.
* sh64-opc.h (shmedia_creg_info): New type.
(shmedia_creg_table): Declare.
* sh64-dis.c (creg_name): New function.
(print_insn_shmedia): Use it.
* disassemble.c (disassembler) [ARCH_sh, INCLUDE_SHMEDIA]: Map
bfd_mach_sh5 to print_insn_sh64 if big-endian and to
print_insn_sh64l if little-endian.
* sh64-dis.c (print_insn_shmedia): Make r unsigned.
(print_insn_sh64l): New.
(print_insn_sh64x): New.
(print_insn_sh64x_media): New.
(print_insn_sh64): Break out code to print_insn_sh64x and
print_insn_sh64x_media.
2000-11-24  Hans-Peter Nilsson  <hpn@cygnus.com>
* sh64-opc.h: New file
* sh64-opc.c: New file
* sh64-dis.c: New file
* Makefile.am: Add sh64 targets.
(HFILES): Add sh64-opc.h.
(CFILES): Add sh64-opc.c and sh64-dis.c.
(ALL_MACHINES): Add sh64 files.
* Makefile.in: Regenerate.
* configure.in: Add support for sh64 to bfd_sh_arch.
* configure: Regenerate.
* disassemble.c [ARCH_all] (INCLUDE_SHMEDIA): Define.
(disassembler) [ARCH_sh, INCLUDE_SHMEDIA]: Map bfd_mach_sh5 to
print_insn_sh64.
* sh-dis.c (print_insn_shx): Handle bfd_mach_sh5 as arch_sh4.
* po/POTFILES.in: Regenerate.
* po/opcodes.pot: Regenerate.
This commit is contained in:
Alexandre Oliva 2002-02-08 05:51:04 +00:00
parent fbca6ad9f3
commit d28847ce8e
12 changed files with 1909 additions and 197 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

93
opcodes/ChangeLog
View file

@ -1,3 +1,96 @@
2002-02-08 Alexandre Oliva <aoliva@redhat.com>
Contribute sh64-elf.
2001-10-08 Nick Clifton <nickc@cambridge.redhat.com>
* sh64-opc.c: Regenerate.
2001-03-13 DJ Delorie <dj@redhat.com>
* sh64-opc.h: Rename A_RESV_Fx to A_REUSE_PREV so that its
purpose is more obvious.
* sh64-opc.c (shmedia_table): Ditto.
* sh64-dis.c (initialize_shmedia_opcode_mask_table): Ditto.
(print_insn_shmedia): Ditto.
2001-03-12 DJ Delorie <dj@redhat.com>
* sh64-opc.c: Adjust comments to reflect reality: replace bits
3:0 with zeros (not "reserved"), replace "rrrrrr" with
"gggggg" for two-operand floating point opcodes. Remove
"fsina".
2001-01-08 Hans-Peter Nilsson <hpn@cygnus.com>
* sh64-dis.c (print_insn_shmedia) <failing read_memory_func>:
Correct printing of .byte:s. Return number of printed bytes or
-1; never 0.
(print_insn_sh64x) <not CRT_SH5_ISA16>: Ditto. Print as .byte:s
to next four-byte-alignment if insn or data is not aligned.
2001-01-06 Hans-Peter Nilsson <hpn@cygnus.com>
* sh64-dis.c: Update comments and fix comment formatting.
(initialize_shmedia_opcode_mask_table) <case A_IMMM>:
Abort instead of setting length to 0.
(crange_qsort_cmpb, crange_qsort_cmpl, crange_bsearch_cmpb,
crange_bsearch_cmpl, sh64_get_contents_type,
sh64_address_in_cranges): Move to bfd/elf32-sh64.c.
2001-01-05 Hans-Peter Nilsson <hpn@cygnus.com>
* sh64-opc.c: Remove #if 0:d entries for instructions not found in
SH-5/ST50-023-04: fcosa.s, fsrra.s and prefo.
2000-12-30 Hans-Peter Nilsson <hpn@cygnus.com>
* sh64-dis.c (print_insn_shmedia): Display MOVI/SHORI-formed
address with same prefix as SHcompact.
In the disassembler, use a .cranges section for linked executables.
* sh64-dis.c (SAVED_MOVI_R, SAVED_MOVI_IMM): Move to head of file
and update for using structure in info->private_data.
(struct sh64_disassemble_info): New.
(is_shmedia_p): Delete.
(crange_qsort_cmpb): New function.
(crange_qsort_cmpl, crange_bsearch_cmpb): New functions.
(crange_bsearch_cmpl, sh64_address_in_cranges): New functions.
(init_sh64_disasm_info, sh64_get_contents_type_disasm): New functions.
(sh64_get_contents_type, sh64_address_is_shmedia): New functions.
(print_insn_shmedia): Correct displaying of address after MOVI/SHORI
pair. Display addresses for linked executables only.
(print_insn_sh64x_media): Initialize info->private_data by calling
init_sh64_disasm_info.
(print_insn_sh64x): Ditto. Find out type of contents by calling
sh64_contents_type_disasm. Display data regions using ".long" and
".byte" similar to unrecognized opcodes.
2000-12-19 Hans-Peter Nilsson <hpn@cygnus.com>
* sh64-dis.c (is_shmedia_p): Check info->section and look for ISA
information in section flags before considering symbols. Don't
assume an info->mach setting of bfd_mach_sh5 means SHmedia code.
* configure.in (bfd_sh_arch): Check presence of sh64 insns by
matching $target $canon_targets instead of looking at the
now-removed -DINCLUDE_SHMEDIA in $targ_cflags.
* configure: Regenerate.
2000-11-25 Hans-Peter Nilsson <hpn@cygnus.com>
* sh64-opc.c (shmedia_creg_table): New.
* sh64-opc.h (shmedia_creg_info): New type.
(shmedia_creg_table): Declare.
* sh64-dis.c (creg_name): New function.
(print_insn_shmedia): Use it.
* disassemble.c (disassembler) [ARCH_sh, INCLUDE_SHMEDIA]: Map
bfd_mach_sh5 to print_insn_sh64 if big-endian and to
print_insn_sh64l if little-endian.
* sh64-dis.c (print_insn_shmedia): Make r unsigned.
(print_insn_sh64l): New.
(print_insn_sh64x): New.
(print_insn_sh64x_media): New.
(print_insn_sh64): Break out code to print_insn_sh64x and
print_insn_sh64x_media.
2000-11-24 Hans-Peter Nilsson <hpn@cygnus.com>
* sh64-opc.h: New file
* sh64-opc.c: New file
* sh64-dis.c: New file
* Makefile.am: Add sh64 targets.
(HFILES): Add sh64-opc.h.
(CFILES): Add sh64-opc.c and sh64-dis.c.
(ALL_MACHINES): Add sh64 files.
* Makefile.in: Regenerate.
* configure.in: Add support for sh64 to bfd_sh_arch.
* configure: Regenerate.
* disassemble.c [ARCH_all] (INCLUDE_SHMEDIA): Define.
(disassembler) [ARCH_sh, INCLUDE_SHMEDIA]: Map bfd_mach_sh5 to
print_insn_sh64.
* sh-dis.c (print_insn_shx): Handle bfd_mach_sh5 as arch_sh4.
* po/POTFILES.in: Regenerate.
* po/opcodes.pot: Regenerate.
2002-02-04 Frank Ch. Eigler <fche@redhat.com>
* cgen-dis.in (print_insn_@arch@): Support disassemble_info.insn_sets.

9
opcodes/Makefile.am
View file

@ -31,6 +31,7 @@ HFILES = \
sysdep.h \
ia64-asmtab.h \
ia64-opc.h \
sh64-opc.h \
w65-opc.h \
xstormy16-desc.h xstormy16-opc.h \
z8k-opc.h
@ -128,6 +129,8 @@ CFILES = \
v850-dis.c \
v850-opc.c \
vax-dis.c \
sh64-dis.c \
sh64-opc.c \
w65-dis.c \
xstormy16-asm.c \
xstormy16-desc.c \
@ -218,6 +221,8 @@ ALL_MACHINES = \
v850-dis.lo \
v850-opc.lo \
vax-dis.lo \
sh64-dis.lo \
sh64-opc.lo \
w65-dis.lo \
xstormy16-asm.lo \
xstormy16-desc.lo \
@ -314,6 +319,10 @@ $(srcdir)/fr30-desc.h $(srcdir)/fr30-desc.c $(srcdir)/fr30-opc.h $(srcdir)/fr30-
stamp-fr30: $(CGENDEPS) $(CPUDIR)/fr30.cpu $(CPUDIR)/fr30.opc
$(MAKE) run-cgen arch=fr30 prefix=fr30 options= extrafiles=
sh64-opc.lo: sh64-opc.c sh64-opc.h
sh64-dis.lo: sh64-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
sh64-opc.h $(INCDIR)/dis-asm.h $(BFD_H) opintl.h
$(srcdir)/openrisc-desc.h $(srcdir)/openrisc-desc.c $(srcdir)/openrisc-opc.h $(srcdir)/openrisc-opc.c $(srcdir)/openrisc-ibld.c $(srcdir)/openrisc-asm.c $(srcdir)/openrisc-dis.c: $(OPENRISC_DEPS)
@true
stamp-openrisc: $(CGENDEPS) $(CPUDIR)/openrisc.cpu $(CPUDIR)/openrisc.opc

17
opcodes/Makefile.in
View file

@ -1,6 +1,6 @@
# Makefile.in generated automatically by automake 1.4-p5 from Makefile.am
# Makefile.in generated automatically by automake 1.4 from Makefile.am
# Copyright (C) 1994, 1995-8, 1999, 2001 Free Software Foundation, Inc.
# Copyright (C) 1994, 1995-8, 1999 Free Software Foundation, Inc.
# This Makefile.in is free software; the Free Software Foundation
# gives unlimited permission to copy and/or distribute it,
# with or without modifications, as long as this notice is preserved.
@ -141,6 +141,7 @@ HFILES = \
sysdep.h \
ia64-asmtab.h \
ia64-opc.h \
sh64-opc.h \
w65-opc.h \
xstormy16-desc.h xstormy16-opc.h \
z8k-opc.h
@ -239,6 +240,8 @@ CFILES = \
v850-dis.c \
v850-opc.c \
vax-dis.c \
sh64-dis.c \
sh64-opc.c \
w65-dis.c \
xstormy16-asm.c \
xstormy16-desc.c \
@ -330,6 +333,8 @@ ALL_MACHINES = \
v850-dis.lo \
v850-opc.lo \
vax-dis.lo \
sh64-dis.lo \
sh64-opc.lo \
w65-dis.lo \
xstormy16-asm.lo \
xstormy16-desc.lo \
@ -411,7 +416,7 @@ acinclude.m4 aclocal.m4 config.in configure configure.in
DISTFILES = $(DIST_COMMON) $(SOURCES) $(HEADERS) $(TEXINFOS) $(EXTRA_DIST)
TAR = tar
TAR = gtar
GZIP_ENV = --best
SOURCES = libopcodes.a.c $(libopcodes_la_SOURCES)
OBJECTS = libopcodes.a.$(OBJEXT) $(libopcodes_la_OBJECTS)
@ -576,7 +581,7 @@ maintainer-clean-recursive:
dot_seen=no; \
rev=''; list='$(SUBDIRS)'; for subdir in $$list; do \
rev="$$subdir $$rev"; \
test "$$subdir" != "." || dot_seen=yes; \
test "$$subdir" = "." && dot_seen=yes; \
done; \
test "$$dot_seen" = "no" && rev=". $$rev"; \
target=`echo $@ | sed s/-recursive//`; \
@ -825,6 +830,10 @@ $(srcdir)/fr30-desc.h $(srcdir)/fr30-desc.c $(srcdir)/fr30-opc.h $(srcdir)/fr30-
stamp-fr30: $(CGENDEPS) $(CPUDIR)/fr30.cpu $(CPUDIR)/fr30.opc
$(MAKE) run-cgen arch=fr30 prefix=fr30 options= extrafiles=
sh64-opc.lo: sh64-opc.c sh64-opc.h
sh64-dis.lo: sh64-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
sh64-opc.h $(INCDIR)/dis-asm.h $(BFD_H) opintl.h
$(srcdir)/openrisc-desc.h $(srcdir)/openrisc-desc.c $(srcdir)/openrisc-opc.h $(srcdir)/openrisc-opc.c $(srcdir)/openrisc-ibld.c $(srcdir)/openrisc-asm.c $(srcdir)/openrisc-dis.c: $(OPENRISC_DEPS)
@true
stamp-openrisc: $(CGENDEPS) $(CPUDIR)/openrisc.cpu $(CPUDIR)/openrisc.opc

380
opcodes/configure vendored
View file

File diff suppressed because it is too large Load diff

6
opcodes/configure.in
View file

@ -209,6 +209,12 @@ if test x${all_targets} = xfalse ; then
bfd_rs6000_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;;
bfd_s390_arch) ta="$ta s390-dis.lo s390-opc.lo" ;;
bfd_sh_arch)
# We can't decide what we want just from the CPU family.
case " $target $canon_targets " in
*" all "* | *" sh64-"* )
ta="$ta sh64-dis.lo sh64-opc.lo"
archdefs="$archdefs -DINCLUDE_SHMEDIA";;
esac;
ta="$ta sh-dis.lo" ;;
bfd_sparc_arch) ta="$ta sparc-dis.lo sparc-opc.lo" ;;
bfd_tahoe_arch) ;;

11
opcodes/disassemble.c
View file

@ -65,6 +65,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#define ARCH_w65
#define ARCH_xstormy16
#define ARCH_z8k
#define INCLUDE_SHMEDIA
#endif
@ -277,6 +278,16 @@ disassembler (abfd)
#endif
#ifdef ARCH_sh
case bfd_arch_sh:
#ifdef INCLUDE_SHMEDIA
if (bfd_get_mach (abfd) == bfd_mach_sh5)
{
if (bfd_big_endian (abfd))
disassemble = print_insn_sh64;
else
disassemble = print_insn_sh64l;
break;
}
#endif
if (bfd_big_endian (abfd))
disassemble = print_insn_sh;
else

3
opcodes/po/POTFILES.in
View file

@ -91,6 +91,9 @@ s390-mkopc.c
s390-opc.c
sh-dis.c
sh-opc.h
sh64-dis.c
sh64-opc.c
sh64-opc.h
sparc-dis.c
sparc-opc.c
sysdep.h

10
opcodes/po/opcodes.pot
View file

@ -6,7 +6,7 @@
msgid ""
msgstr ""
"Project-Id-Version: PACKAGE VERSION\n"
"POT-Creation-Date: 2002-01-31 17:10+0000\n"
"POT-Creation-Date: 2002-02-08 03:24-0200\n"
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
"Language-Team: LANGUAGE <LL@li.org>\n"
@ -320,21 +320,21 @@ msgid "invalid register operand when updating"
msgstr ""
#. Mark as non-valid instruction
#: sparc-dis.c:749
#: sparc-dis.c:750
msgid "unknown"
msgstr ""
#: sparc-dis.c:824
#: sparc-dis.c:825
#, c-format
msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
msgstr ""
#: sparc-dis.c:835
#: sparc-dis.c:836
#, c-format
msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
msgstr ""
#: sparc-dis.c:884
#: sparc-dis.c:885
#, c-format
msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"
msgstr ""

5
opcodes/sh-dis.c
View file

@ -323,6 +323,11 @@ print_insn_shx (memaddr, info)
case bfd_mach_sh4:
target_arch = arch_sh4;
break;
case bfd_mach_sh5:
/* When we get here for sh64, it's because we want to disassemble
SHcompact, i.e. arch_sh4. */
target_arch = arch_sh4;
break;
default:
abort ();
}

659
opcodes/sh64-dis.c Normal file
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@ -0,0 +1,659 @@
/* Disassemble SH64 instructions.
Copyright (C) 2000, 2001 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include <stdio.h>
#include "dis-asm.h"
#include "sysdep.h"
#include "sh64-opc.h"
#include "libiberty.h"
/* We need to refer to the ELF header structure. */
#include "elf-bfd.h"
#include "elf/sh.h"
#define ELF_MODE32_CODE_LABEL_P(SYM) \
(((elf_symbol_type *) (SYM))->internal_elf_sym.st_other & STO_SH5_ISA32)
#define SAVED_MOVI_R(INFO) \
(((struct sh64_disassemble_info *) ((INFO)->private_data))->address_reg)
#define SAVED_MOVI_IMM(INFO) \
(((struct sh64_disassemble_info *) ((INFO)->private_data))->built_address)
struct sh64_disassemble_info
{
/* When we see a MOVI, we save the register and the value, and merge a
subsequent SHORI and display the address, if there is one. */
unsigned int address_reg;
bfd_signed_vma built_address;
/* This is the range decriptor for the current address. It is kept
around for the next call. */
sh64_elf_crange crange;
};
/* Each item in the table is a mask to indicate which bits to be set
to determine an instruction's operator.
The index is as same as the instruction in the opcode table.
Note that some archs have this as a field in the opcode table. */
static unsigned long *shmedia_opcode_mask_table;
static void initialize_shmedia_opcode_mask_table PARAMS ((void));
static int print_insn_shmedia PARAMS ((bfd_vma, disassemble_info *));
static int print_insn_sh64x
PARAMS ((bfd_vma, disassemble_info *,
int (*) PARAMS ((bfd_vma, struct disassemble_info *)),
enum bfd_endian));
static const char *creg_name PARAMS ((int));
static boolean init_sh64_disasm_info PARAMS ((struct disassemble_info *));
static enum sh64_elf_cr_type sh64_get_contents_type_disasm
PARAMS ((bfd_vma, struct disassemble_info *));
/* Initialize the SH64 opcode mask table for each instruction in SHmedia
mode. */
static void
initialize_shmedia_opcode_mask_table ()
{
int n_opc;
int n;
/* Calculate number of opcodes. */
for (n_opc = 0; shmedia_table[n_opc].name != NULL; n_opc++)
;
shmedia_opcode_mask_table
= xmalloc (sizeof (shmedia_opcode_mask_table[0]) * n_opc);
for (n = 0; n < n_opc; n++)
{
int i;
unsigned long mask = 0;
for (i = 0; shmedia_table[n].arg[i] != A_NONE; i++)
{
int offset = shmedia_table[n].nibbles[i];
int length;
switch (shmedia_table[n].arg[i])
{
case A_GREG_M:
case A_GREG_N:
case A_GREG_D:
case A_CREG_K:
case A_CREG_J:
case A_FREG_G:
case A_FREG_H:
case A_FREG_F:
case A_DREG_G:
case A_DREG_H:
case A_DREG_F:
case A_FMREG_G:
case A_FMREG_H:
case A_FMREG_F:
case A_FPREG_G:
case A_FPREG_H:
case A_FPREG_F:
case A_FVREG_G:
case A_FVREG_H:
case A_FVREG_F:
case A_REUSE_PREV:
length = 6;
break;
case A_TREG_A:
case A_TREG_B:
length = 3;
break;
case A_IMMM:
abort ();
break;
case A_IMMU5:
length = 5;
break;
case A_IMMS6:
case A_IMMU6:
case A_IMMS6BY32:
length = 6;
break;
case A_IMMS10:
case A_IMMS10BY1:
case A_IMMS10BY2:
case A_IMMS10BY4:
case A_IMMS10BY8:
length = 10;
break;
case A_IMMU16:
case A_IMMS16:
case A_PCIMMS16BY4:
case A_PCIMMS16BY4_PT:
length = 16;
break;
default:
abort ();
length = 0;
break;
}
if (length != 0)
mask |= (0xffffffff >> (32 - length)) << offset;
}
shmedia_opcode_mask_table[n] = 0xffffffff & ~mask;
}
}
/* Get a predefined control-register-name, or return NULL. */
const char *
creg_name (cregno)
int cregno;
{
const shmedia_creg_info *cregp;
/* If control register usage is common enough, change this to search a
hash-table. */
for (cregp = shmedia_creg_table; cregp->name != NULL; cregp++)
{
if (cregp->cregno == cregno)
return cregp->name;
}
return NULL;
}
/* Main function to disassemble SHmedia instructions. */
static int
print_insn_shmedia (memaddr, info)
bfd_vma memaddr;
struct disassemble_info *info;
{
fprintf_ftype fprintf_fn = info->fprintf_func;
void *stream = info->stream;
unsigned char insn[4];
unsigned long instruction;
int status;
int n;
const shmedia_opcode_info *op;
int i;
unsigned int r = 0;
long imm = 0;
bfd_vma disp_pc_addr;
status = info->read_memory_func (memaddr, insn, 4, info);
/* If we can't read four bytes, something is wrong. Display any data we
can get as .byte:s. */
if (status != 0)
{
int i;
for (i = 0; i < 3; i++)
{
status = info->read_memory_func (memaddr + i, insn, 1, info);
if (status != 0)
break;
(*fprintf_fn) (stream, "%s0x%02x",
i == 0 ? ".byte " : ", ",
insn[0]);
}
return i ? i : -1;
}
/* Rearrange the bytes to make up an instruction. */
if (info->endian == BFD_ENDIAN_LITTLE)
instruction = bfd_getl32 (insn);
else
instruction = bfd_getb32 (insn);
/* FIXME: Searching could be implemented using a hash on relevant
fields. */
for (n = 0, op = shmedia_table;
op->name != NULL
&& ((instruction & shmedia_opcode_mask_table[n]) != op->opcode_base);
n++, op++)
;
/* FIXME: We should also check register number constraints. */
if (op->name == NULL)
{
fprintf_fn (stream, ".long 0x%08x", instruction);
return 4;
}
fprintf_fn (stream, "%s\t", op->name);
for (i = 0; i < 3 && op->arg[i] != A_NONE; i++)
{
unsigned long temp = instruction >> op->nibbles[i];
int by_number = 0;
if (i > 0 && op->arg[i] != A_REUSE_PREV)
fprintf_fn (stream, ",");
switch (op->arg[i])
{
case A_REUSE_PREV:
continue;
case A_GREG_M:
case A_GREG_N:
case A_GREG_D:
r = temp & 0x3f;
fprintf_fn (stream, "r%d", r);
break;
case A_FVREG_F:
case A_FVREG_G:
case A_FVREG_H:
r = temp & 0x3f;
fprintf_fn (stream, "fv%d", r);
break;
case A_FPREG_F:
case A_FPREG_G:
case A_FPREG_H:
r = temp & 0x3f;
fprintf_fn (stream, "fp%d", r);
break;
case A_FMREG_F:
case A_FMREG_G:
case A_FMREG_H:
r = temp & 0x3f;
fprintf_fn (stream, "mtrx%d", r);
break;
case A_CREG_K:
case A_CREG_J:
{
const char *name;
r = temp & 0x3f;
name = creg_name (r);
if (name != NULL)
fprintf_fn (stream, "%s", name);
else
fprintf_fn (stream, "cr%d", r);
}
break;
case A_FREG_G:
case A_FREG_H:
case A_FREG_F:
r = temp & 0x3f;
fprintf_fn (stream, "fr%d", r);
break;
case A_DREG_G:
case A_DREG_H:
case A_DREG_F:
r = temp & 0x3f;
fprintf_fn (stream, "dr%d", r);
break;
case A_TREG_A:
case A_TREG_B:
r = temp & 0x7;
fprintf_fn (stream, "tr%d", r);
break;
/* A signed 6-bit number. */
case A_IMMS6:
imm = temp & 0x3f;
if (imm & (unsigned long) 0x20)
imm |= ~(unsigned long) 0x3f;
fprintf_fn (stream, "%d", imm);
break;
/* A signed 6-bit number, multiplied by 32 when used. */
case A_IMMS6BY32:
imm = temp & 0x3f;
if (imm & (unsigned long) 0x20)
imm |= ~(unsigned long) 0x3f;
fprintf_fn (stream, "%d", imm * 32);
break;
/* A signed 10-bit number, multiplied by 8 when used. */
case A_IMMS10BY8:
by_number++;
/* Fall through. */
/* A signed 10-bit number, multiplied by 4 when used. */
case A_IMMS10BY4:
by_number++;
/* Fall through. */
/* A signed 10-bit number, multiplied by 2 when used. */
case A_IMMS10BY2:
by_number++;
/* Fall through. */
/* A signed 10-bit number. */
case A_IMMS10:
case A_IMMS10BY1:
imm = temp & 0x3ff;
if (imm & (unsigned long) 0x200)
imm |= ~(unsigned long) 0x3ff;
imm <<= by_number;
fprintf_fn (stream, "%d", imm);
break;
/* A signed 16-bit number. */
case A_IMMS16:
imm = temp & 0xffff;
if (imm & (unsigned long) 0x8000)
imm |= ~((unsigned long) 0xffff);
fprintf_fn (stream, "%d", imm);
break;
/* A PC-relative signed 16-bit number, multiplied by 4 when
used. */
case A_PCIMMS16BY4:
imm = temp & 0xffff; /* 16 bits */
if (imm & (unsigned long) 0x8000)
imm |= ~(unsigned long) 0xffff;
imm <<= 2;
disp_pc_addr = (bfd_vma) imm + memaddr;
(*info->print_address_func) (disp_pc_addr, info);
break;
/* An unsigned 5-bit number. */
case A_IMMU5:
imm = temp & 0x1f;
fprintf_fn (stream, "%d", imm);
break;
/* An unsigned 6-bit number. */
case A_IMMU6:
imm = temp & 0x3f;
fprintf_fn (stream, "%d", imm);
break;
/* An unsigned 16-bit number. */
case A_IMMU16:
imm = temp & 0xffff;
fprintf_fn (stream, "%d", imm);
break;
default:
abort ();
break;
}
}
/* FIXME: Looks like 32-bit values only are handled.
FIXME: PC-relative numbers aren't handled correctly. */
if (op->opcode_base == (unsigned long) SHMEDIA_SHORI_OPC
&& SAVED_MOVI_R (info) == r)
{
asection *section = info->section;
/* Most callers do not set the section field correctly yet. Revert
to getting the section from symbols, if any. */
if (section == NULL
&& info->symbols != NULL
&& bfd_asymbol_flavour (info->symbols[0]) == bfd_target_elf_flavour
&& ! bfd_is_und_section (bfd_get_section (info->symbols[0]))
&& ! bfd_is_abs_section (bfd_get_section (info->symbols[0])))
section = bfd_get_section (info->symbols[0]);
/* Only guess addresses when the contents of this section is fully
relocated. Otherwise, the value will be zero or perhaps even
bogus. */
if (section == NULL
|| section->owner == NULL
|| elf_elfheader (section->owner)->e_type == ET_EXEC)
{
bfd_signed_vma shori_addr;
shori_addr = SAVED_MOVI_IMM (info) << 16;
shori_addr |= imm;
fprintf_fn (stream, "\t! 0x");
(*info->print_address_func) (shori_addr, info);
}
}
if (op->opcode_base == SHMEDIA_MOVI_OPC)
{
SAVED_MOVI_IMM (info) = imm;
SAVED_MOVI_R (info) = r;
}
else
{
SAVED_MOVI_IMM (info) = 0;
SAVED_MOVI_R (info) = 255;
}
return 4;
}
/* Check the type of contents about to be disassembled. This is like
sh64_get_contents_type (which may be called from here), except that it
takes the same arguments as print_insn_* and does what can be done if
no section is available. */
static enum sh64_elf_cr_type
sh64_get_contents_type_disasm (memaddr, info)
bfd_vma memaddr;
struct disassemble_info *info;
{
struct sh64_disassemble_info *sh64_infop = info->private_data;
/* Perhaps we have a region from a previous probe and it still counts
for this address? */
if (sh64_infop->crange.cr_type != CRT_NONE
&& memaddr >= sh64_infop->crange.cr_addr
&& memaddr < sh64_infop->crange.cr_addr + sh64_infop->crange.cr_size)
return sh64_infop->crange.cr_type;
/* If we have a section, try and use it. */
if (info->section
&& bfd_get_flavour (info->section->owner) == bfd_target_elf_flavour)
{
enum sh64_elf_cr_type cr_type
= sh64_get_contents_type (info->section, memaddr,
&sh64_infop->crange);
if (cr_type != CRT_NONE)
return cr_type;
}
/* If we have symbols, we can try and get at a section from *that*. */
if (info->symbols != NULL
&& bfd_asymbol_flavour (info->symbols[0]) == bfd_target_elf_flavour
&& ! bfd_is_und_section (bfd_get_section (info->symbols[0]))
&& ! bfd_is_abs_section (bfd_get_section (info->symbols[0])))
{
enum sh64_elf_cr_type cr_type
= sh64_get_contents_type (bfd_get_section (info->symbols[0]),
memaddr, &sh64_infop->crange);
if (cr_type != CRT_NONE)
return cr_type;
}
/* We can make a reasonable guess based on the st_other field of a
symbol; for a BranchTarget this is marked as STO_SH5_ISA32 and then
it's most probably code there. */
if (info->symbols
&& bfd_asymbol_flavour (info->symbols[0]) == bfd_target_elf_flavour
&& elf_symbol_from (bfd_asymbol_bfd (info->symbols[0]),
info->symbols[0])->internal_elf_sym.st_other
== STO_SH5_ISA32)
return CRT_SH5_ISA32;
/* If all else fails, guess this is code and guess on the low bit set. */
return (memaddr & 1) == 1 ? CRT_SH5_ISA32 : CRT_SH5_ISA16;
}
/* Initialize static and dynamic disassembly state. */
static boolean
init_sh64_disasm_info (info)
struct disassemble_info *info;
{
struct sh64_disassemble_info *sh64_infop
= calloc (sizeof (*sh64_infop), 1);
if (sh64_infop == NULL)
return false;
info->private_data = sh64_infop;
SAVED_MOVI_IMM (info) = 0;
SAVED_MOVI_R (info) = 255;
if (shmedia_opcode_mask_table == NULL)
initialize_shmedia_opcode_mask_table ();
return true;
}
/* Main entry to disassemble SHmedia instructions, given an endian set in
INFO. Note that the simulator uses this as the main entry and does not
use any of the functions further below. */
int
print_insn_sh64x_media (memaddr, info)
bfd_vma memaddr;
struct disassemble_info *info;
{
if (info->private_data == NULL && ! init_sh64_disasm_info (info))
return -1;
/* Make reasonable output. */
info->bytes_per_line = 4;
info->bytes_per_chunk = 4;
return print_insn_shmedia (memaddr, info);
}
/* Main entry to disassemble SHcompact or SHmedia insns. */
static int
print_insn_sh64x (memaddr, info, pfun_compact, endian)
bfd_vma memaddr;
struct disassemble_info *info;
int (*pfun_compact) PARAMS ((bfd_vma, struct disassemble_info *));
enum bfd_endian endian;
{
enum sh64_elf_cr_type cr_type;
if (info->private_data == NULL && ! init_sh64_disasm_info (info))
return -1;
cr_type = sh64_get_contents_type_disasm (memaddr, info);
if (cr_type != CRT_SH5_ISA16)
{
int length = 4 - (memaddr % 4);
info->display_endian = endian;
/* Only disassemble on four-byte boundaries. Addresses that are not
a multiple of four can happen after a data region. */
if (cr_type == CRT_SH5_ISA32 && length == 4)
return print_insn_sh64x_media (memaddr, info);
/* We get CRT_DATA *only* for data regions in a mixed-contents
section. For sections with data only, we get indication of one
of the ISA:s. You may think that we shouldn't disassemble
section with only data if we can figure that out. However, the
disassembly function is by default not called for data-only
sections, so if the user explicitly specified disassembly of a
data section, that's what we should do. */
if (cr_type == CRT_DATA || length != 4)
{
int status;
unsigned char data[4];
struct sh64_disassemble_info *sh64_infop = info->private_data;
if (length == 4
&& sh64_infop->crange.cr_type != CRT_NONE
&& memaddr >= sh64_infop->crange.cr_addr
&& memaddr < (sh64_infop->crange.cr_addr
+ sh64_infop->crange.cr_size))
length
= (sh64_infop->crange.cr_addr
+ sh64_infop->crange.cr_size - memaddr);
status
= (*info->read_memory_func) (memaddr, data,
length >= 4 ? 4 : length, info);
if (status == 0 && length >= 4)
{
(*info->fprintf_func) (info->stream, ".long 0x%08lx",
endian == BFD_ENDIAN_BIG
? (long) (bfd_getb32 (data))
: (long) (bfd_getl32 (data)));
return 4;
}
else
{
int i;
for (i = 0; i < length; i++)
{
status = info->read_memory_func (memaddr + i, data, 1, info);
if (status != 0)
break;
(*info->fprintf_func) (info->stream, "%s0x%02x",
i == 0 ? ".byte " : ", ",
data[0]);
}
return i ? i : -1;
}
}
}
return (*pfun_compact) (memaddr, info);
}
/* Main entry to disassemble SHcompact or SHmedia insns, big endian. */
int
print_insn_sh64 (memaddr, info)
bfd_vma memaddr;
struct disassemble_info *info;
{
return
print_insn_sh64x (memaddr, info, print_insn_sh, BFD_ENDIAN_BIG);
}
/* Main entry to disassemble SHcompact or SHmedia insns, little endian. */
int
print_insn_sh64l (memaddr, info)
bfd_vma memaddr;
struct disassemble_info *info;
{
return
print_insn_sh64x (memaddr, info, print_insn_shl, BFD_ENDIAN_LITTLE);
}

774
opcodes/sh64-opc.c Normal file
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@ -0,0 +1,774 @@
/* Definitions for SH64 opcodes.
Copyright (C) 2000, 2001 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include "sh64-opc.h"
#include <stdio.h>
/* Users currently assume that no mnemonic appears twice. For
disassembly, the first complete match is displayed. */
const shmedia_opcode_info shmedia_table[] = {
/* 000000mmmmmm1001nnnnnndddddd0000 add <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "add", {A_GREG_M,A_GREG_N,A_GREG_D},
{OFFSET_20,OFFSET_10,OFFSET_4}, SHMEDIA_ADD_OPC
},
/* 000000mmmmmm1000nnnnnndddddd0000 add.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "add.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x00080000
},
/* 110100mmmmmmssssssssssdddddd0000 addi <A_GREG_M>,<A_IMMS10>,<A_GREG_D> */
{ "addi", {A_GREG_M,A_IMMS10BY1,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4},
SHMEDIA_ADDI_OPC
},
/* 110101mmmmmmssssssssssdddddd0000 addi.l <A_GREG_M>,<A_IMMS10>,<A_GREG_D> */
{ "addi.l", {A_GREG_M,A_IMMS10BY1,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xd4000000
},
/* 000000mmmmmm1100nnnnnndddddd0000 addz.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "addz.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x000c0000
},
/* 111000mmmmmm0100ssssss1111110000 alloco <A_GREG_M>,<A_IMMS6BY32> */
{ "alloco", {A_GREG_M,A_IMMS6BY32}, {OFFSET_20,OFFSET_10}, 0xe00403f0
},
/* 000001mmmmmm1011nnnnnndddddd0000 and <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "and", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x040b0000
},
/* 000001mmmmmm1111nnnnnndddddd0000 andc <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "andc", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x040f0000
},
/* 110110mmmmmmssssssssssdddddd0000 andi <A_GREG_M>,<A_IMMS10>,<A_GREG_D> */
{ "andi", {A_GREG_M,A_IMMS10,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xd8000000
},
/* 011001mmmmmm0001nnnnnnl00ccc0000 beq <A_GREG_M>,<A_GREG_N>,<A_TREG_A> */
{ "beq/l", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64010200
},
/* 011001mmmmmm0001nnnnnnl00ccc0000 beq <A_GREG_M>,<A_GREG_N>,<A_TREG_A> */
{ "beq", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64010200
},
/* 011001mmmmmm0001nnnnnn000ccc0000 beq/u <A_GREG_M>,<A_GREG_N>,<A_TREG_A> */
{ "beq/u", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64010000
},
/* 111001mmmmmm0001ssssssl00ccc0000 beqi <A_GREG_M>,<A_IMMS6>,<A_TREG_A> */
{ "beqi/l", {A_GREG_M,A_IMMS6,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe4010200
},
/* 111001mmmmmm0001ssssssl00ccc0000 beqi <A_GREG_M>,<A_IMMS6>,<A_TREG_A> */
{ "beqi", {A_GREG_M,A_IMMS6,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe4010200
},
/* 111001mmmmmm0001ssssss000ccc0000 beqi/u <A_GREG_M>,<A_IMMS6>,<A_TREG_A> */
{ "beqi/u", {A_GREG_M,A_IMMS6,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe4010000
},
/* 011001mmmmmm0011nnnnnnl00ccc0000 bge <A_GREG_M>,<A_GREG_N>,<A_TREG_A> */
{ "bge/l", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64030200
},
/* 011001mmmmmm0011nnnnnnl00ccc0000 bge <A_GREG_M>,<A_GREG_N>,<A_TREG_A> */
{ "bge", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64030200
},
/* 011001mmmmmm0011nnnnnn000ccc0000 bge/u <A_GREG_M>,<A_GREG_N>,<A_TREG_A> */
{ "bge/u", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64030000
},
/* 011001mmmmmm1011nnnnnnl00ccc0000 bgeu <A_GREG_M>,<A_GREG_N>,<A_TREG_A> */
{ "bgeu/l", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x640b0200
},
/* 011001mmmmmm1011nnnnnnl00ccc0000 bgeu <A_GREG_M>,<A_GREG_N>,<A_TREG_A> */
{ "bgeu", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x640b0200
},
/* 011001mmmmmm1011nnnnnn000ccc0000 bgeu/u <A_GREG_M>,<A_GREG_N>,<A_TREG_A> */
{ "bgeu/u", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x640b0000
},
/* 011001mmmmmm0111nnnnnnl00ccc0000 bgt <A_GREG_M>,<A_GREG_N>,<A_TREG_A> */
{ "bgt/l", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64070200
},
/* 011001mmmmmm0111nnnnnnl00ccc0000 bgt <A_GREG_M>,<A_GREG_N>,<A_TREG_A> */
{ "bgt", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64070200
},
/* 011001mmmmmm0111nnnnnn000ccc0000 bgt/u <A_GREG_M>,<A_GREG_N>,<A_TREG_A> */
{ "bgt/u", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64070000
},
/* 011001mmmmmm1111nnnnnnl00ccc0000 bgtu <A_GREG_M>,<A_GREG_N>,<A_TREG_A> */
{ "bgtu/l", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x640f0200
},
/* 011001mmmmmm1111nnnnnnl00ccc0000 bgtu <A_GREG_M>,<A_GREG_N>,<A_TREG_A> */
{ "bgtu", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x640f0200
},
/* 011001mmmmmm1111nnnnnn000ccc0000 bgtu/u <A_GREG_M>,<A_GREG_N>,<A_TREG_A> */
{ "bgtu/u", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x640f0000
},
/* 010001000bbb0001111111dddddd0000 blink <A_TREG_B>,<A_GREG_D> */
{ "blink", {A_TREG_B,A_GREG_D}, {OFFSET_20,OFFSET_4}, 0x4401fc00
},
/* 011001mmmmmm0101nnnnnnl00ccc0000 bne <A_GREG_M>,<A_GREG_N>,<A_TREG_A> */
{ "bne/l", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64050200
},
/* 011001mmmmmm0101nnnnnnl00ccc0000 bne <A_GREG_M>,<A_GREG_N>,<A_TREG_A> */
{ "bne", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64050200
},
/* 011001mmmmmm0101nnnnnn000ccc0000 bne/u <A_GREG_M>,<A_GREG_N>,<A_TREG_A> */
{ "bne/u", {A_GREG_M,A_GREG_N,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x64050000
},
/* 111001mmmmmm0101ssssssl00ccc0000 bnei <A_GREG_M>,<A_IMMS6>,<A_TREG_A> */
{ "bnei/l", {A_GREG_M,A_IMMS6,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe4050200
},
/* 111001mmmmmm0101ssssssl00ccc0000 bnei <A_GREG_M>,<A_IMMS6>,<A_TREG_A> */
{ "bnei", {A_GREG_M,A_IMMS6,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe4050200
},
/* 111001mmmmmm0101ssssss000ccc0000 bnei/u <A_GREG_M>,<A_IMMS6>,<A_TREG_A> */
{ "bnei/u", {A_GREG_M,A_IMMS6,A_TREG_A}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe4050000
},
/* 01101111111101011111111111110000 brk */
{ "brk", {A_NONE}, {OFFSET_NONE}, 0x6ff5fff0
},
/* 000000mmmmmm1111111111dddddd0000 byterev <A_GREG_M>,<A_GREG_D> */
{ "byterev", {A_GREG_M,A_GREG_D}, {OFFSET_20,OFFSET_4}, 0x000ffc00
},
/* 000000mmmmmm0001nnnnnndddddd0000 cmpeq <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "cmpeq", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x00010000
},
/* 000000mmmmmm0011nnnnnndddddd0000 cmpgt <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "cmpgt", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x00030000
},
/* 000000mmmmmm0111nnnnnndddddd0000 cmpgtu <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "cmpgtu", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x00070000
},
/* 001000mmmmmm0001nnnnnnwwwwww0000 cmveq <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "cmveq", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x20010000
},
/* 001000mmmmmm0101nnnnnnwwwwww0000 cmvne <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "cmvne", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x20050000
},
/* 000110gggggg0001ggggggffffff0000 fabs.d <A_DREG_G>,<A_DREG_F> */
{ "fabs.d", {A_DREG_G,A_REUSE_PREV,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x18010000
},
/* 000110gggggg0000ggggggffffff0000 fabs.s <A_FREG_G>,<A_FREG_F> */
{ "fabs.s", {A_FREG_G,A_REUSE_PREV,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x18000000
},
/* 001101gggggg0001hhhhhhffffff0000 fadd.s <A_DREG_G>,<A_DREG_H>,<A_DREG_F> */
{ "fadd.d", {A_DREG_G,A_DREG_H,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x34010000
},
/* 001101gggggg0000hhhhhhffffff0000 fadd.s <A_FREG_G>,<A_FREG_H>,<A_FREG_F> */
{ "fadd.s", {A_FREG_G,A_FREG_H,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x34000000
},
/* 001100gggggg1001hhhhhhdddddd0000 fcmpeq.s <A_DREG_G>,<A_DREG_H>,<A_GREG_D> */
{ "fcmpeq.d", {A_DREG_G,A_DREG_H,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x30090000
},
/* 001100gggggg1000hhhhhhdddddd0000 fcmpeq.s <A_FREG_G>,<A_FREG_H>,<A_GREG_D> */
{ "fcmpeq.s", {A_FREG_G,A_FREG_H,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x30080000
},
/* 001100gggggg1111hhhhhhdddddd0000 fcmpge.d <A_DREG_G>,<A_DREG_H>,<A_GREG_D> */
{ "fcmpge.d", {A_DREG_G,A_DREG_H,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x300f0000
},
/* 001100gggggg1110hhhhhhdddddd0000 fcmpge.s <A_FREG_G>,<A_FREG_H>,<A_GREG_D> */
{ "fcmpge.s", {A_FREG_G,A_FREG_H,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x300e0000
},
/* 001100gggggg1101hhhhhhdddddd0000 fcmpgt.d <A_DREG_G>,<A_DREG_H>,<A_GREG_D> */
{ "fcmpgt.d", {A_DREG_G,A_DREG_H,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x300d0000
},
/* 001100gggggg1100hhhhhhdddddd0000 fcmpgt.s <A_FREG_G>,<A_FREG_H>,<A_GREG_D> */
{ "fcmpgt.s", {A_FREG_G,A_FREG_H,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x300c0000
},
/* 001100gggggg1011hhhhhhdddddd0000 fcmpun.d <A_DREG_G>,<A_DREG_H>,<A_GREG_D> */
{ "fcmpun.d", {A_DREG_G,A_DREG_H,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x300b0000
},
/* 001100gggggg1010hhhhhhdddddd0000 fcmpun.s <A_FREG_G>,<A_FREG_H>,<A_GREG_D> */
{ "fcmpun.s", {A_FREG_G,A_FREG_H,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x300a0000
},
/* 001110gggggg0111ggggggffffff0000 fcnv.ds <A_DREG_G>,<A_FREG_F> */
{ "fcnv.ds", {A_DREG_G,A_REUSE_PREV,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x38070000
},
/* 001110gggggg0110ggggggffffff0000 fcnv.sd <A_FREG_G>,<A_DREG_F> */
{ "fcnv.sd", {A_FREG_G,A_REUSE_PREV,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x38060000
},
/* 001101gggggg0101hhhhhhffffff0000 fdiv.d <A_DREG_G>,<A_DREG_H>,<A_DREG_F> */
{ "fdiv.d", {A_DREG_G,A_DREG_H,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x34050000
},
/* 001101gggggg0100hhhhhhffffff0000 fdiv.s <A_FREG_G>,<A_FREG_H>,<A_FREG_F> */
{ "fdiv.s", {A_FREG_G,A_FREG_H,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x34040000
},
/* 0001111111110010111111ffffff0000 fgetscr <A_FREG_F> */
{ "fgetscr", {A_FREG_F}, {OFFSET_4}, 0x1ff2fc00
},
/* 000101gggggg0110hhhhhhffffff0000 fipr.s <A_FVREG_G>,<A_FVREG_H>,<A_FREG_F> */
{ "fipr.s", {A_FVREG_G,A_FVREG_H,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x14060000
},
/* 100111mmmmmmssssssssssffffff0000 fld.d <A_GREG_M>,<A_IMMS10BY8>,<A_DREG_F> */
{ "fld.d", {A_GREG_M,A_IMMS10BY8,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x9c000000
},
/* 100110mmmmmmssssssssssffffff0000 fld.p <A_GREG_M>,<A_IMMS10BY8>,<A_FPREG_F> */
{ "fld.p", {A_GREG_M,A_IMMS10BY8,A_FPREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x98000000
},
/* 100101mmmmmmssssssssssffffff0000 fld.s <A_GREG_M>,<A_IMMS10BY4>,<A_FREG_F> */
{ "fld.s", {A_GREG_M,A_IMMS10BY4,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x94000000
},
/* 000111mmmmmm1001nnnnnnffffff0000 fldx.d <A_GREG_M>,<A_GREG_N>,<A_DREG_F> */
{ "fldx.d", {A_GREG_M,A_GREG_N,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x1c090000
},
/* 000111mmmmmm1101nnnnnnffffff0000 fldx.p <A_GREG_M>,<A_GREG_N>,<A_FPREG_F> */
{ "fldx.p", {A_GREG_M,A_GREG_N,A_FPREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x1c0d0000
},
/* 000111mmmmmm1000nnnnnnffffff0000 fldx.s <A_GREG_M>,<A_GREG_N>,<A_FREG_F> */
{ "fldx.s", {A_GREG_M,A_GREG_N,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x1c080000
},
/* 001110gggggg1110ggggggffffff0000 float.ld <A_FREG_G>,<A_DREG_F> */
{ "float.ld", {A_FREG_G,A_REUSE_PREV,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x380e0000
},
/* 001110gggggg1100ggggggffffff0000 float.ls <A_FREG_G>,<A_FREG_F> */
{ "float.ls", {A_FREG_G,A_REUSE_PREV,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x380c0000
},
/* 001110gggggg1101ggggggffffff0000 float.qd <A_DREG_G>,<A_DREG_F> */
{ "float.qd", {A_DREG_G,A_REUSE_PREV,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x380d0000
},
/* 001110gggggg1111ggggggffffff0000 float.qs <A_DREG_G>,<A_FREG_F> */
{ "float.qs", {A_DREG_G,A_REUSE_PREV,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x380f0000
},
/* 001101gggggg1110hhhhhhqqqqqq0000 fmac.s <A_FREG_G>,<A_FREG_H>,<A_FREG_F> */
{ "fmac.s", {A_FREG_G,A_FREG_H,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x340e0000
},
/* 001110gggggg0001ggggggffffff0000 fmov.d <A_DREG_G>,<A_DREG_F> */
{ "fmov.d", {A_DREG_G,A_REUSE_PREV,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x38010000
},
/* 001100gggggg0001ggggggdddddd0000 fmov.dq <A_DREG_G>,<A_GREG_D> */
{ "fmov.dq", {A_DREG_G,A_REUSE_PREV,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x30010000
},
/* 000111mmmmmm0000111111ffffff0000 fmov.ls <A_GREG_M>,<A_FREG_F> */
{ "fmov.ls", {A_GREG_M,A_FREG_F}, {OFFSET_20,OFFSET_4}, 0x1c00fc00
},
/* 000111mmmmmm0001111111ffffff0000 fmov.qd <A_GREG_M>,<A_DREG_F> */
{ "fmov.qd", {A_GREG_M,A_DREG_F}, {OFFSET_20,OFFSET_4}, 0x1c01fc00
},
/* 001110gggggg0000ggggggffffff0000 fmov.s <A_FREG_G>,<A_FREG_F> */
{ "fmov.s", {A_FREG_G,A_REUSE_PREV,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x38000000
},
/* 001100gggggg0000ggggggdddddd0000 fmov.sl <A_FREG_G>,<A_GREG_D> */
{ "fmov.sl", {A_FREG_G,A_REUSE_PREV,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x30000000
},
/* 001101gggggg0111hhhhhhffffff0000 fmul.d <A_DREG_G>,<A_DREG_H>,<A_DREG_F> */
{ "fmul.d", {A_DREG_G,A_DREG_H,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x34070000
},
/* 001101gggggg0110hhhhhhffffff0000 fmul.s <A_FREG_G>,<A_FREG_H>,<A_FREG_F> */
{ "fmul.s", {A_FREG_G,A_FREG_H,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x34060000
},
/* 000110gggggg0011ggggggffffff0000 fneg.d <A_DREG_G>,<A_DREG_F> */
{ "fneg.d", {A_DREG_G,A_REUSE_PREV,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x18030000
},
/* 000110gggggg0010ggggggffffff0000 fneg.s <A_FREG_G>,<A_FREG_F> */
{ "fneg.s", {A_FREG_G,A_REUSE_PREV,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x18020000
},
/* 001100gggggg0010gggggg1111110000 fputscr <A_FREG_G> */
{ "fputscr", {A_FREG_G,A_REUSE_PREV}, {OFFSET_20,OFFSET_10}, 0x300203f0
},
/* 001110gggggg0101ggggggffffff0000 fsqrt.d <A_DREG_G>,<A_DREG_F> */
{ "fsqrt.d", {A_DREG_G,A_REUSE_PREV,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x38050000
},
/* 001110gggggg0100ggggggffffff0000 fsqrt.s <A_FREG_G>,<A_FREG_F> */
{ "fsqrt.s", {A_FREG_G,A_REUSE_PREV,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x38040000
},
/* 101111mmmmmmsssssssssszzzzzz0000 fst.d <A_GREG_M>,<A_IMMS10BY8>,<A_DREG_F> */
{ "fst.d", {A_GREG_M,A_IMMS10BY8,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xbc000000
},
/* 101110mmmmmmsssssssssszzzzzz0000 fst.p <A_GREG_M>,<A_IMMS10BY8>,<A_FPREG_F> */
{ "fst.p", {A_GREG_M,A_IMMS10BY8,A_FPREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xb8000000
},
/* 101101mmmmmmsssssssssszzzzzz0000 fst.s <A_GREG_M>,<A_IMMS10BY4>,<A_FREG_F> */
{ "fst.s", {A_GREG_M,A_IMMS10BY4,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xb4000000
},
/* 001111mmmmmm1001nnnnnnzzzzzz0000 fstx.d <A_GREG_M>,<A_GREG_N>,<A_DREG_F> */
{ "fstx.d", {A_GREG_M,A_GREG_N,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x3c090000
},
/* 001111mmmmmm1101nnnnnnzzzzzz0000 fstx.p <A_GREG_M>,<A_GREG_N>,<A_FPREG_F> */
{ "fstx.p", {A_GREG_M,A_GREG_N,A_FPREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x3c0d0000
},
/* 001111mmmmmm1000nnnnnnzzzzzz0000 fstx.s <A_GREG_M>,<A_GREG_N>,<A_FREG_F> */
{ "fstx.s", {A_GREG_M,A_GREG_N,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x3c080000
},
/* 001101gggggg0011hhhhhhffffff0000 fsub.d <A_DREG_G>,<A_DREG_H>,<A_DREG_F> */
{ "fsub.d", {A_DREG_G,A_DREG_H,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x34030000
},
/* 001101gggggg0010hhhhhhffffff0000 fsub.s <A_FREG_G>,<A_FREG_H>,<A_FREG_F> */
{ "fsub.s", {A_FREG_G,A_FREG_H,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x34020000
},
/* 001110gggggg1011ggggggffffff0000 ftrc.dl <A_DREG_G>,<A_FREG_F> */
{ "ftrc.dl", {A_DREG_G,A_REUSE_PREV,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x380b0000
},
/* 001110gggggg1001ggggggffffff0000 ftrc.dq <A_DREG_G>,<A_DREG_F> */
{ "ftrc.dq", {A_DREG_G,A_REUSE_PREV,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x38090000
},
/* 001110gggggg1000ggggggffffff0000 ftrc.sl <A_FREG_G>,<A_FREG_F> */
{ "ftrc.sl", {A_FREG_G,A_REUSE_PREV,A_FREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x38080000
},
/* 001110gggggg1010ggggggffffff0000 ftrc.sq <A_FREG_G>,<A_DREG_F> */
{ "ftrc.sq", {A_FREG_G,A_REUSE_PREV,A_DREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x380a0000
},
/* 000101gggggg1110hhhhhhffffff0000 ftrv.s <A_FMREG_G>,<A_FVREG_H>,<A_FVREG_F> */
{ "ftrv.s", {A_FMREG_G,A_FVREG_H,A_FVREG_F}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x140e0000
},
/* 110000mmmmmm1111ssssssdddddd0000 getcfg <A_GREG_M>,<A_IMMS6>,<A_GREG_D> */
{ "getcfg", {A_GREG_M,A_IMMS6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc00f0000
},
/* 001001kkkkkk1111111111dddddd0000 getcon <A_CREG_K>,<A_GREG_M> */
{ "getcon", {A_CREG_K,A_GREG_D}, {OFFSET_20,OFFSET_4}, 0x240ffc00
},
/* 010001rrrbbb0101111111dddddd0000 gettr <A_TREG_A>,<A_GREG_D> */
{ "gettr", {A_TREG_B,A_GREG_D}, {OFFSET_20,OFFSET_4}, 0x4405fc00
},
/* 111000mmmmmm0101ssssss1111110000 icbi <A_GREG_M>,<A_IMMS6BY32> */
{ "icbi", {A_GREG_M,A_IMMS6BY32}, {OFFSET_20,OFFSET_10}, 0xe00503f0
},
/* 100000mmmmmmssssssssssdddddd0000 ld.b <A_GREG_M>,<A_IMMS10BY1>,<A_GREG_D> */
{ "ld.b", {A_GREG_M,A_IMMS10BY1,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x80000000
},
/* 100010mmmmmmssssssssssdddddd0000 ld.l <A_GREG_M>,<A_IMMS10BY4>,<A_GREG_D> */
{ "ld.l", {A_GREG_M,A_IMMS10BY4,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x88000000
},
/* 100011mmmmmmssssssssssdddddd0000 ld.q <A_GREG_M>,<A_IMMS10BY8>,<A_GREG_D> */
{ "ld.q", {A_GREG_M,A_IMMS10BY8,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x8c000000
},
/* 100100mmmmmmssssssssssdddddd0000 ld.ub <A_GREG_M>,<A_IMMS10BY1>,<A_GREG_D> */
{ "ld.ub", {A_GREG_M,A_IMMS10BY1,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x90000000
},
/* 101100mmmmmmssssssssssdddddd0000 ld.uw <A_GREG_M>,<A_IMMS10BY2>,<A_GREG_D> */
{ "ld.uw", {A_GREG_M,A_IMMS10BY2,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xb0000000
},
/* 100001mmmmmmssssssssssdddddd0000 ld.w <A_GREG_M>,<A_IMMS10BY2>,<A_GREG_D> */
{ "ld.w", {A_GREG_M,A_IMMS10BY2,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x84000000
},
/* 110000mmmmmm0110ssssssdddddd0000 ldhi.l <A_GREG_M>,<A_IMMS6>,<A_GREG_D> */
{ "ldhi.l", {A_GREG_M,A_IMMS6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc0060000
},
/* 110000mmmmmm0111ssssssdddddd0000 ldhi.q <A_GREG_M>,<A_IMMS6>,<A_GREG_D> */
{ "ldhi.q", {A_GREG_M,A_IMMS6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc0070000
},
/* 110000mmmmmm0010ssssssdddddd0000 ldlo.l <A_GREG_M>,<A_IMMS6>,<A_GREG_D> */
{ "ldlo.l", {A_GREG_M,A_IMMS6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc0020000
},
/* 110000mmmmmm0011ssssssdddddd0000 ldlo.q <A_GREG_M>,<A_IMMS6>,<A_GREG_D> */
{ "ldlo.q", {A_GREG_M,A_IMMS6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc0030000
},
/* 010000mmmmmm0000nnnnnndddddd0000 ldx.b <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "ldx.b", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x40000000
},
/* 010000mmmmmm0010nnnnnndddddd0000 ldx.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "ldx.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x40020000
},
/* 010000mmmmmm0011nnnnnndddddd0000 ldx.q <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "ldx.q", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x40030000
},
/* 010000mmmmmm0100nnnnnndddddd0000 ldx.ub <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "ldx.ub", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x40040000
},
/* 010000mmmmmm0101nnnnnndddddd0000 ldx.uw <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "ldx.uw", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x40050000
},
/* 010000mmmmmm0001nnnnnndddddd0000 ldx.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "ldx.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x40010000
},
/* 001010mmmmmm1010111111dddddd0000 mabs.l <A_GREG_M>,<A_GREG_D> */
{ "mabs.l", {A_GREG_M,A_GREG_D}, {OFFSET_20,OFFSET_4}, 0x280afc00
},
/* 001010mmmmmm1001111111dddddd0000 mabs.w <A_GREG_M>,<A_GREG_D> */
{ "mabs.w", {A_GREG_M,A_GREG_D}, {OFFSET_20,OFFSET_4}, 0x2809fc00
},
/* 000010mmmmmm0010nnnnnndddddd0000 madd.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "madd.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x08020000
},
/* 000010mmmmmm0001nnnnnndddddd0000 madd.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "madd.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x08010000
},
/* 000010mmmmmm0110nnnnnndddddd0000 madds.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "madds.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x08060000
},
/* 000010mmmmmm0100nnnnnndddddd0000 madds.ub <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "madds.ub", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x08040000
},
/* 000010mmmmmm0101nnnnnndddddd0000 madds.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "madds.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x08050000
},
/* 001010mmmmmm0000nnnnnndddddd0000 mcmpeq.b <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "mcmpeq.b", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x28000000
},
/* 001010mmmmmm0010nnnnnndddddd0000 mcmpeq.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "mcmpeq.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x28020000
},
/* 001010mmmmmm0001nnnnnndddddd0000 mcmpeq.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "mcmpeq.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x28010000
},
/* 001010mmmmmm0110nnnnnndddddd0000 mcmpgt.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "mcmpgt.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x28060000
},
/* 001010mmmmmm0100nnnnnndddddd0000 mcmpgt.ub <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "mcmpgt.ub", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x28040000
},
/* 001010mmmmmm0101nnnnnndddddd0000 mcmpgt.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "mcmpgt.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x28050000
},
/* 010010mmmmmm0011nnnnnnwwwwww0000 mcmv <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "mcmv", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x48030000
},
/* 010011mmmmmm1101nnnnnndddddd0000 mcnvs.lw <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "mcnvs.lw", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c0d0000
},
/* 010011mmmmmm1000nnnnnndddddd0000 mcnvs.wb <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "mcnvs.wb", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c080000
},
/* 010011mmmmmm1100nnnnnndddddd0000 mcnvs.wub <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "mcnvs.wub", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c0c0000
},
/* 001010mmmmmm0111nnnnnndddddd0000 mextr1 <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "mextr1", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x28070000
},
/* 001010mmmmmm1011nnnnnndddddd0000 mextr2 <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "mextr2", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x280b0000
},
/* 001010mmmmmm1111nnnnnndddddd0000 mextr3 <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "mextr3", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x280f0000
},
/* 001011mmmmmm0011nnnnnndddddd0000 mextr4 <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "mextr4", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c030000
},
/* 001011mmmmmm0111nnnnnndddddd0000 mextr5 <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "mextr5", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c070000
},
/* 001011mmmmmm1011nnnnnndddddd0000 mextr6 <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "mextr6", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c0b0000
},
/* 001011mmmmmm1111nnnnnndddddd0000 mextr7 <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "mextr7", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c0f0000
},
/* 010010mmmmmm0001nnnnnnwwwwww0000 mmacfx.wl <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "mmacfx.wl", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x48010000
},
/* 010010mmmmmm0101nnnnnnwwwwww0000 mmacnfx.wl <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "mmacnfx.wl", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x48050000
},
/* 010011mmmmmm0010nnnnnndddddd0000 mmul.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "mmul.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c020000
},
/* 010011mmmmmm0001nnnnnndddddd0000 mmul.m <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "mmul.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c010000
},
/* 010011mmmmmm0110nnnnnndddddd0000 mmulfx.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "mmulfx.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c060000
},
/* 010011mmmmmm0101nnnnnndddddd0000 mmulfx.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "mmulfx.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c050000
},
/* 010011mmmmmm1001nnnnnndddddd0000 mmulfxrp.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "mmulfxrp.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c090000
},
/* 010011mmmmmm1110nnnnnndddddd0000 mmulhi.wl <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "mmulhi.wl", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c0e0000
},
/* 010011mmmmmm1010nnnnnndddddd0000 mmullo.wl <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "mmullo.wl", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x4c0a0000
},
/* 010010mmmmmm1001nnnnnnwwwwww0000 mmulsum.wq <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "mmulsum.wq", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x48090000
},
/* 110011ssssssssssssssssdddddd0000 movi <A_IMMS16>,<A_GREG_D> */
{ "movi", {A_IMMS16,A_GREG_D}, {OFFSET_10,OFFSET_4}, SHMEDIA_MOVI_OPC
},
/* 001010mmmmmm1101nnnnnndddddd0000 mperm.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "mperm.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x280d0000
},
/* 010010mmmmmm0000nnnnnnwwwwww0000 msad.ubq <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "msad.ubq", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x48000000
},
/* 000011mmmmmm1010nnnnnndddddd0000 mshard.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "mshard.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x0c0a0000
},
/* 000011mmmmmm1001nnnnnndddddd0000 mshard.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "mshard.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x0c090000
},
/* 000011mmmmmm1011nnnnnndddddd0000 mshards.q <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "mshards.q", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x0c0b0000
},
/* 001011mmmmmm0100nnnnnndddddd0000 mshfhi.b <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "mshfhi.b", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c040000
},
/* 001011mmmmmm0110nnnnnndddddd0000 mshfhi.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "mshfhi.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c060000
},
/* 001011mmmmmm0101nnnnnndddddd0000 mshfhi.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "mshfhi.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c050000
},
/* 001011mmmmmm0000nnnnnndddddd0000 mshflo.b <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "mshflo.b", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c000000
},
/* 001011mmmmmm0010nnnnnndddddd0000 mshflo.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "mshflo.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c020000
},
/* 001011mmmmmm0001nnnnnndddddd0000 mshflo.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "mshflo.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x2c010000
},
/* 000011mmmmmm0010nnnnnndddddd0000 mshlld.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "mshlld.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x0c020000
},
/* 000011mmmmmm0001nnnnnndddddd0000 mshlld.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "mshlld.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x0c010000
},
/* 000011mmmmmm0110nnnnnndddddd0000 mshalds.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "mshalds.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x0c060000
},
/* 000011mmmmmm0101nnnnnndddddd0000 mshalds.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "mshalds.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x0c050000
},
/* 000011mmmmmm1110nnnnnndddddd0000 mshlrd.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "mshlrd.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x0c0e0000
},
/* 000011mmmmmm1101nnnnnndddddd0000 mshlrd.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "mshlrd.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x0c0d0000
},
/* 000010mmmmmm1010nnnnnndddddd0000 msub.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "msub.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x080a0000
},
/* 000010mmmmmm1001nnnnnndddddd0000 msub.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "msub.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x08090000
},
/* 000010mmmmmm1110nnnnnndddddd0000 msubs.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "msubs.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x080e0000
},
/* 000010mmmmmm1100nnnnnndddddd0000 msubs.ub <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "msubs.ub", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x080c0000
},
/* 000010mmmmmm1101nnnnnndddddd0000 msubs.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "msubs.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x080d0000
},
/* 000001mmmmmm1110nnnnnndddddd0000 muls.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "muls.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x040e0000
},
/* 000000mmmmmm1110nnnnnndddddd0000 mulu.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "mulu.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x000e0000
},
/* 01101111111100001111111111110000 nop */
{ "nop", {A_NONE}, {OFFSET_NONE},
SHMEDIA_NOP_OPC
},
/* 000000mmmmmm1101111111dddddd0000 nsb <A_GREG_M>,<A_GREG_D> */
{ "nsb", {A_GREG_M,A_GREG_D}, {OFFSET_20,OFFSET_4}, 0x000dfc00
},
/* 111000mmmmmm1001ssssss1111110000 ocbi <A_GREG_M>,<A_IMMS6BY32> */
{ "ocbi", {A_GREG_M,A_IMMS6BY32}, {OFFSET_20,OFFSET_10}, 0xe00903f0
},
/* 111000mmmmmm1000ssssss1111110000 ocbp <A_GREG_M>,<A_IMMS6BY32> */
{ "ocbp", {A_GREG_M,A_IMMS6BY32}, {OFFSET_20,OFFSET_10}, 0xe00803f0
},
/* 111000mmmmmm1100ssssss1111110000 ocbwb <A_GREG_M>,<A_IMMS6BY32> */
{ "ocbwb", {A_GREG_M,A_IMMS6BY32}, {OFFSET_20,OFFSET_10}, 0xe00c03f0
},
/* 000001mmmmmm1001nnnnnndddddd0000 or <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "or", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x04090000
},
/* 110111mmmmmmssssssssssdddddd0000 ori <A_GREG_M>,<A_IMMS10>,<A_GREG_D> */
{ "ori", {A_GREG_M,A_IMMS10,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xdc000000
},
/* 111000mmmmmm0001ssssss1111110000 prefi <A_GREG_M>,<A_IMMS6BY32> */
{ "prefi", {A_GREG_M,A_IMMS6BY32}, {OFFSET_20,OFFSET_10}, 0xe00103f0
},
/* 111010sssssssssssssssslrraaa0000 pta <A_PCIMMS16BY4>,<A_TREG_A> */
{ "pta/l", {A_PCIMMS16BY4,A_TREG_A}, {OFFSET_10,OFFSET_4},
SHMEDIA_PTA_OPC | SHMEDIA_LIKELY_BIT
},
/* 111010sssssssssssssssslrraaa0000 pta <A_PCIMMS16BY4>,<A_TREG_A> */
{ "pta", {A_PCIMMS16BY4,A_TREG_A}, {OFFSET_10,OFFSET_4},
SHMEDIA_PTA_OPC | SHMEDIA_LIKELY_BIT
},
/* 111010ssssssssssssssss0rraaa0000 pta/u <A_PCIMMS16BY4>,<A_TREG_A> */
{ "pta/u", {A_PCIMMS16BY4,A_TREG_A}, {OFFSET_10,OFFSET_4},
SHMEDIA_PTA_OPC
},
/* 0110101111110001nnnnnnl00aaa0000 ptabs <A_GREG_M>,<A_TREG_A> */
{ "ptabs/l", {A_GREG_N,A_TREG_A}, {OFFSET_10,OFFSET_4}, 0x6bf10200
},
/* 0110101111110001nnnnnnl00aaa0000 ptabs <A_GREG_M>,<A_TREG_A> */
{ "ptabs", {A_GREG_N,A_TREG_A}, {OFFSET_10,OFFSET_4}, 0x6bf10200
},
/* 0110101111110001nnnnnn000aaa0000 ptabs/u <A_GREG_M>,<A_TREG_A> */
{ "ptabs/u", {A_GREG_N,A_TREG_A}, {OFFSET_10,OFFSET_4}, 0x6bf10000
},
/* 111011sssssssssssssssslrraaa0000 ptb <A_PCIMMS16BY4>,<A_TREG_A> */
{ "ptb/l", {A_PCIMMS16BY4,A_TREG_A}, {OFFSET_10,OFFSET_4},
SHMEDIA_PTB_OPC | SHMEDIA_LIKELY_BIT
},
/* 111011sssssssssssssssslrraaa0000 ptb <A_PCIMMS16BY4>,<A_TREG_A> */
{ "ptb", {A_PCIMMS16BY4,A_TREG_A}, {OFFSET_10,OFFSET_4},
SHMEDIA_PTB_OPC | SHMEDIA_LIKELY_BIT
},
/* 111011ssssssssssssssss0rraaa0000 ptb/u <A_PCIMMS16BY4>,<A_TREG_A> */
{ "ptb/u", {A_PCIMMS16BY4,A_TREG_A}, {OFFSET_10,OFFSET_4},
SHMEDIA_PTB_OPC
},
/* 111010sssssssssssssssslrraaa0000 pt/l <A_PCIMMS16BY4>,<A_TREG_A> */
{ "pt/l", {A_PCIMMS16BY4_PT,A_TREG_A},
{OFFSET_10,OFFSET_4}, SHMEDIA_PT_OPC | SHMEDIA_LIKELY_BIT
},
/* 111010sssssssssssssssslrraaa0000 pt <A_PCIMMS16BY4>,<A_TREG_A> */
{ "pt", {A_PCIMMS16BY4_PT,A_TREG_A},
{OFFSET_10,OFFSET_4}, SHMEDIA_PT_OPC | SHMEDIA_LIKELY_BIT
},
/* 111010ssssssssssssssss0rraaa0000 pt/u <A_PCIMMS16BY4>,<A_TREG_A> */
{ "pt/u", {A_PCIMMS16BY4_PT,A_TREG_A},
{OFFSET_10,OFFSET_4}, SHMEDIA_PT_OPC
},
/* 0110101111110101nnnnnnl00aaa0000 ptrel <A_GREG_M>,<A_TREG_A> */
{ "ptrel/l", {A_GREG_N,A_TREG_A}, {OFFSET_10,OFFSET_4},
SHMEDIA_PTREL_OPC | SHMEDIA_LIKELY_BIT
},
/* 0110101111110101nnnnnnl00aaa0000 ptrel <A_GREG_M>,<A_TREG_A> */
{ "ptrel", {A_GREG_N,A_TREG_A}, {OFFSET_10,OFFSET_4},
SHMEDIA_PTREL_OPC | SHMEDIA_LIKELY_BIT
},
/* 0110101111110101nnnnnn000aaa0000 ptrel/u <A_GREG_M>,<A_TREG_A> */
{ "ptrel/u", {A_GREG_N,A_TREG_A}, {OFFSET_10,OFFSET_4},
SHMEDIA_PTREL_OPC
},
/* 111000mmmmmm1111ssssssyyyyyy0000 putcfg <A_GREG_M>,<A_IMMS6>,<A_GREG_D> */
{ "putcfg", {A_GREG_M,A_IMMS6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe00f0000
},
/* 011011mmmmmm1111111111jjjjjj0000 putcon <A_GREG_M>,<A_CREG_J> */
{ "putcon", {A_GREG_M,A_CREG_J}, {OFFSET_20,OFFSET_4}, 0x6c0ffc00
},
/* 01101111111100111111111111110000 rte */
{ "rte", {A_NONE}, {OFFSET_NONE}, 0x6ff3fff0
},
/* 000001mmmmmm0111nnnnnndddddd0000 shard <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "shard", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x04070000
},
/* 000001mmmmmm0110nnnnnndddddd0000 shard.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "shard.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x04060000
},
/* 110001mmmmmm0111ssssssdddddd0000 shari <A_GREG_M>,<A_IMMU6>,<A_GREG_D> */
{ "shari", {A_GREG_M,A_IMMU6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc4070000
},
/* 110001mmmmmm0110ssssssdddddd0000 shari <A_GREG_M>,<A_IMMU6>,<A_GREG_D> */
{ "shari.l", {A_GREG_M,A_IMMU6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc4060000
},
/* 000001mmmmmm0001nnnnnndddddd0000 shlld <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "shlld", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x04010000
},
/* 000001mmmmmm0000nnnnnndddddd0000 shlld.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "shlld.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x04000000
},
/* 110001mmmmmm0001ssssssdddddd0000 shlli <A_GREG_M>,<A_IMMU6>,<A_GREG_D> */
{ "shlli", {A_GREG_M,A_IMMU6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc4010000
},
/* 110001mmmmmm0000ssssssdddddd0000 shlli.l <A_GREG_M>,<A_IMMU5>,<A_GREG_D> */
{ "shlli.l", {A_GREG_M,A_IMMU5,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc4000000
},
/* 000001mmmmmm0011nnnnnndddddd0000 shlrd <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "shlrd", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x04030000
},
/* 000001mmmmmm0010nnnnnndddddd0000 shlrd.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "shlrd.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x04020000
},
/* 110001mmmmmm0011ssssssdddddd0000 shlri <A_GREG_M>,<A_IMMU6>,<A_GREG_D> */
{ "shlri", {A_GREG_M,A_IMMU6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc4030000
},
/* 110001mmmmmm0010ssssssdddddd0000 shlri.l <A_GREG_M>,<A_IMMU5>,<A_GREG_D> */
{ "shlri.l", {A_GREG_M,A_IMMU5,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc4020000
},
/* 110010sssssssssssssssswwwwww0000 shori <A_IMMU16>,<A_GREG_D> */
{ "shori", {A_IMMU16,A_GREG_D}, {OFFSET_10,OFFSET_4}, SHMEDIA_SHORI_OPC
},
/* 01101111111101111111111111110000 sleep */
{ "sleep", {A_NONE}, {OFFSET_NONE}, 0x6ff7fff0
},
/* 101000mmmmmmssssssssssdddddd0000 st.b <A_GREG_M>,<A_IMMS10BY1>,<A_GREG_D> */
{ "st.b", {A_GREG_M,A_IMMS10BY1,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xa0000000
},
/* 101010mmmmmmssssssssssdddddd0000 st.l <A_GREG_M>,<A_IMMS10BY4>,<A_GREG_D> */
{ "st.l", {A_GREG_M,A_IMMS10BY4,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xa8000000
},
/* 101011mmmmmmssssssssssdddddd0000 st.q <A_GREG_M>,<A_IMMS10BY8>,<A_GREG_D> */
{ "st.q", {A_GREG_M,A_IMMS10BY8,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xac000000
},
/* 101001mmmmmmssssssssssdddddd0000 st.w <A_GREG_M>,<A_IMMS10BY2>,<A_GREG_D> */
{ "st.w", {A_GREG_M,A_IMMS10BY2,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xa4000000
},
/* 111000mmmmmm0110ssssssdddddd0000 sthi.l <A_GREG_M>,<A_IMMS6>,<A_GREG_D> */
{ "sthi.l", {A_GREG_M,A_IMMS6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe0060000
},
/* 111000mmmmmm0111ssssssdddddd0000 sthi.q <A_GREG_M>,<A_IMMS6>,<A_GREG_D> */
{ "sthi.q", {A_GREG_M,A_IMMS6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe0070000
},
/* 111000mmmmmm0010ssssssdddddd0000 stlo.l <A_GREG_M>,<A_IMMS6>,<A_GREG_D> */
{ "stlo.l", {A_GREG_M,A_IMMS6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe0020000
},
/* 111000mmmmmm0011ssssssdddddd0000 stlo.q <A_GREG_M>,<A_IMMS6>,<A_GREG_D> */
{ "stlo.q", {A_GREG_M,A_IMMS6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xe0030000
},
/* 011000mmmmmm0000nnnnnndddddd0000 stx.b <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "stx.b", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x60000000
},
/* 011000mmmmmm0010nnnnnndddddd0000 stx.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "stx.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x60020000
},
/* 011000mmmmmm0011nnnnnndddddd0000 stx.q <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "stx.q", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x60030000
},
/* 011000mmmmmm0001nnnnnndddddd0000 stx.w <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "stx.w", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x60010000
},
/* 000000mmmmmm1011nnnnnndddddd0000 sub <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "sub", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x000b0000
},
/* 000000mmmmmm1010nnnnnndddddd0000 sub.l <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "sub.l", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x000a0000
},
/* 001000mmmmmm0011nnnnnnwwwwww0000 swap.q <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "swap.q", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x20030000
},
/* 01101111111100101111111111110000 synci */
{ "synci", {A_NONE}, {OFFSET_NONE}, 0x6ff2fff0
},
/* 01101111111101101111111111110000 synco */
{ "synco", {A_NONE}, {OFFSET_NONE}, 0x6ff6fff0
},
/* 011011mmmmmm00011111111111110000 trapa <A_GREG_M> */
{ "trapa", {A_GREG_M}, {OFFSET_20}, 0x6c01fff0
},
/* 000001mmmmmm1101nnnnnndddddd0000 xor <A_GREG_M>,<A_GREG_N>,<A_GREG_D> */
{ "xor", {A_GREG_M,A_GREG_N,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0x040d0000
},
/* 110001mmmmmm1101ssssssdddddd0000 xori <A_GREG_M>,<A_IMMS6>,<A_GREG_D> */
{ "xori", {A_GREG_M,A_IMMS6,A_GREG_D}, {OFFSET_20,OFFSET_10,OFFSET_4}, 0xc40d0000
},
{ NULL, {}, {}, 0 }
};
/* Predefined control register names as per SH-5/ST50-005-08. */
const shmedia_creg_info shmedia_creg_table[] = {
{ 0, "sr" },
{ 1, "ssr" },
{ 2, "pssr" },
{ 4, "intevt" },
{ 5, "expevt" },
{ 6, "pexpevt" },
{ 7, "tra" },
{ 8, "spc" },
{ 9, "pspc" },
{ 10, "resvec" },
{ 11, "vbr" },
{ 13, "tea" },
{ 16, "dcr" },
{ 17, "kcr0" },
{ 18, "kcr1" },
{ 62, "ctc" },
{ 63, "usr" },
{ -1, (char *) 0 }
};

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/* Declarations for SH64 opcodes.
Copyright (C) 2000, 2001 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#ifndef _SH64_OPC_INCLUDED_H
#define _SH64_OPC_INCLUDED_H
typedef enum
{
/* A placeholder. */
OFFSET_NONE = 0,
/* Bit number for where to insert operand. */
OFFSET_4 = 4,
OFFSET_9 = 9,
OFFSET_10 = 10,
OFFSET_20 = 20
} shmedia_nibble_type;
typedef enum {
/* First a placeholder. */
A_NONE = 0,
/* Registers. */
A_GREG_M,
A_GREG_N,
A_GREG_D,
A_FREG_G,
A_FREG_H,
A_FREG_F,
A_DREG_G,
A_DREG_H,
A_DREG_F,
A_FVREG_G,
A_FVREG_H,
A_FVREG_F,
A_FMREG_G,
A_FMREG_H,
A_FMREG_F,
A_FPREG_G,
A_FPREG_H,
A_FPREG_F,
A_TREG_A,
A_TREG_B,
A_CREG_K,
A_CREG_J,
/* This one is only used in a shmedia_get_operand. */
A_IMMM,
/* Copy of previous register. */
A_REUSE_PREV,
/* Unsigned 5-bit operand. */
A_IMMU5,
/* Signed 6-bit operand. */
A_IMMS6,
/* Signed operand, 6 bits << 5. */
A_IMMS6BY32,
/* Unsigned 6-bit operand. */
A_IMMU6,
/* Signed 10-bit operand. */
A_IMMS10,
/* Signed operand, 10 bits << 0. */
A_IMMS10BY1,
/* Signed operand, 10 bits << 1. */
A_IMMS10BY2,
/* Signed operand, 10 bits << 2. */
A_IMMS10BY4,
/* Signed operand, 10 bits << 3. */
A_IMMS10BY8,
/* Signed 16-bit operand. */
A_IMMS16,
/* Unsigned 16-bit operand. */
A_IMMU16,
/* PC-relative signed operand, 16 bits << 2, for PTA and PTB insns. */
A_PCIMMS16BY4,
/* PC relative signed operand, 16 bits << 2, for PT insns. Also adjusts
the opcode to be PTA or PTB. */
A_PCIMMS16BY4_PT,
} shmedia_arg_type;
typedef struct {
char *name;
shmedia_arg_type arg[4];
shmedia_nibble_type nibbles[4];
unsigned long opcode_base;
} shmedia_opcode_info;
extern const shmedia_opcode_info shmedia_table[];
typedef struct {
int cregno;
char *name;
} shmedia_creg_info;
extern const shmedia_creg_info shmedia_creg_table[];
#define SHMEDIA_LIKELY_BIT 0x00000200
#define SHMEDIA_PT_OPC 0xe8000000
#define SHMEDIA_PTB_BIT 0x04000000
#define SHMEDIA_PTA_OPC 0xe8000000
#define SHMEDIA_PTB_OPC 0xec000000
/* Note that this is ptrel/u. "Or" in SHMEDIA_LIKELY_BIT for ptrel/l. */
#define SHMEDIA_PTREL_OPC 0x6bf50000
#define SHMEDIA_MOVI_OPC 0xcc000000
#define SHMEDIA_SHORI_OPC 0xc8000000
#define SHMEDIA_ADDI_OPC 0xd0000000
#define SHMEDIA_ADD_OPC 0x00090000
#define SHMEDIA_NOP_OPC 0x6ff0fff0
#define SHMEDIA_TEMP_REG 25
#endif /* _SH64_OPC_INCLUDED_H */