* compile.c: Fix formatting.
This commit is contained in:
Kazu Hirata
parent
1a89f665fc
commit
d13351445b
2 changed files with 49 additions and 45 deletions
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@ -1,3 +1,7 @@
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2002-05-19 Kazu Hirata <kazu@cs.umass.edu>
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* compile.c: Fix formatting.
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2002-05-18 Kazu Hirata <kazu@cs.umass.edu>
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* compile.c: Fix formatting.
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@ -86,7 +86,7 @@ void sim_set_simcache_size PARAMS ((int));
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(N << 3) | (Z << 2) | (V<<1) | C;
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#define BUILDEXR() \
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if( h8300smode ) cpu.exr = ( trace<<7 ) | intMask;
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if (h8300smode) cpu.exr = (trace<<7) | intMask;
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#define GETSR() \
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c = (cpu.ccr >> 0) & 1;\
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@ -99,7 +99,7 @@ void sim_set_simcache_size PARAMS ((int));
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intMaskBit = (cpu.ccr >> 7) & 1;
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#define GETEXR() \
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if( h8300smode ) { \
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if (h8300smode) { \
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trace = (cpu.exr >> 7) & 1;\
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intMask = cpu.exr & 7; }
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@ -850,7 +850,7 @@ mop (code, bsize, sign)
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}
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#define ONOT(name, how) \
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case O(name, SB): \
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case O (name, SB): \
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{ \
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int t; \
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int hm = 0x80; \
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@ -858,7 +858,7 @@ case O(name, SB): \
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how; \
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goto shift8; \
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} \
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case O(name, SW): \
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case O (name, SW): \
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{ \
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int t; \
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int hm = 0x8000; \
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@ -866,7 +866,7 @@ case O(name, SW): \
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how; \
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goto shift16; \
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} \
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case O(name, SL): \
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case O (name, SL): \
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{ \
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int t; \
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int hm = 0x80000000; \
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@ -876,7 +876,7 @@ case O(name, SL): \
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}
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#define OSHIFTS(name, how1, how2) \
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case O(name, SB): \
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case O (name, SB): \
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{ \
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int t; \
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int hm = 0x80; \
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@ -891,7 +891,7 @@ case O(name, SB): \
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} \
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goto shift8; \
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} \
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case O(name, SW): \
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case O (name, SW): \
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{ \
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int t; \
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int hm = 0x8000; \
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@ -906,7 +906,7 @@ case O(name, SW): \
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} \
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goto shift16; \
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} \
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case O(name, SL): \
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case O (name, SL): \
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{ \
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int t; \
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int hm = 0x80000000; \
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@ -923,14 +923,14 @@ case O(name, SL): \
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}
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#define OBITOP(name,f, s, op) \
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case O(name, SB): \
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case O (name, SB): \
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{ \
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int m; \
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int b; \
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if (f) ea = fetch (&code->dst); \
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m=1<< fetch(&code->src); \
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m=1<< fetch (&code->src); \
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op; \
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if(s) store (&code->dst,ea); goto next; \
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if (s) store (&code->dst,ea); goto next; \
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}
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int
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@ -1021,15 +1021,15 @@ sim_resume (sd, step, siggnal)
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#define ALUOP(STORE, NAME, HOW) \
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case O(NAME,SB): HOW; if(STORE)goto alu8;else goto just_flags_alu8; \
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case O(NAME, SW): HOW; if(STORE)goto alu16;else goto just_flags_alu16; \
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case O(NAME,SL): HOW; if(STORE)goto alu32;else goto just_flags_alu32;
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case O (NAME,SB): HOW; if (STORE)goto alu8;else goto just_flags_alu8; \
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case O (NAME, SW): HOW; if (STORE)goto alu16;else goto just_flags_alu16; \
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case O (NAME,SL): HOW; if (STORE)goto alu32;else goto just_flags_alu32;
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#define LOGOP(NAME, HOW) \
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case O(NAME,SB): HOW; goto log8;\
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case O(NAME, SW): HOW; goto log16;\
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case O(NAME,SL): HOW; goto log32;
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case O (NAME,SB): HOW; goto log8;\
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case O (NAME, SW): HOW; goto log16;\
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case O (NAME,SL): HOW; goto log32;
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@ -1075,8 +1075,8 @@ sim_resume (sd, step, siggnal)
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res = rd + ea;
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goto alu8;
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#define EA ea = fetch(&code->src);
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#define RD_EA ea = fetch(&code->src); rd = fetch(&code->dst);
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#define EA ea = fetch (&code->src);
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#define RD_EA ea = fetch (&code->src); rd = fetch (&code->dst);
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ALUOP (1, O_SUB, RD_EA;
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ea = -ea;
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@ -1139,31 +1139,31 @@ sim_resume (sd, step, siggnal)
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case O (O_EEPMOV, SB):
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case O (O_EEPMOV, SW):
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if(h8300hmode||h8300smode)
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if (h8300hmode||h8300smode)
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{
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register unsigned char *_src,*_dst;
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unsigned int count = (code->opcode==O(O_EEPMOV, SW))?cpu.regs[R4_REGNUM]&0xffff:
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unsigned int count = (code->opcode == O(O_EEPMOV, SW))?cpu.regs[R4_REGNUM]&0xffff:
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cpu.regs[R4_REGNUM]&0xff;
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_src = cpu.regs[R5_REGNUM] < memory_size ? cpu.memory+cpu.regs[R5_REGNUM] :
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cpu.eightbit + (cpu.regs[R5_REGNUM] & 0xff);
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if((_src+count)>=(cpu.memory+memory_size))
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if ((_src+count)>=(cpu.memory+memory_size))
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{
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if((_src+count)>=(cpu.eightbit+0x100))
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if ((_src+count)>=(cpu.eightbit+0x100))
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goto illegal;
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}
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_dst = cpu.regs[R6_REGNUM] < memory_size ? cpu.memory+cpu.regs[R6_REGNUM] :
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cpu.eightbit + (cpu.regs[R6_REGNUM] & 0xff);
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if((_dst+count)>=(cpu.memory+memory_size))
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if ((_dst+count)>=(cpu.memory+memory_size))
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{
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if((_dst+count)>=(cpu.eightbit+0x100))
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if ((_dst+count)>=(cpu.eightbit+0x100))
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goto illegal;
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}
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memcpy(_dst,_src,count);
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cpu.regs[R5_REGNUM]+=count;
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cpu.regs[R6_REGNUM]+=count;
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cpu.regs[R4_REGNUM]&=(code->opcode==O(O_EEPMOV, SW))?(~0xffff):(~0xff);
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cpu.regs[R4_REGNUM]&=(code->opcode == O(O_EEPMOV, SW))?(~0xffff):(~0xff);
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cycles += 2*count;
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goto next;
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}
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@ -1248,21 +1248,21 @@ sim_resume (sd, step, siggnal)
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goto just_flags_inc32;
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#define GET_CCR(x) BUILDSR();x = cpu.ccr
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#define GET_EXR(x) BUILDEXR();x = cpu.exr
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#define GET_EXR(x) BUILDEXR ();x = cpu.exr
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case O (O_LDC, SB):
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case O (O_LDC, SW):
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res = fetch(&code->src);
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res = fetch (&code->src);
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goto setc;
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case O (O_STC, SB):
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case O (O_STC, SW):
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if(code->src.type==OP_CCR)
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if (code->src.type == OP_CCR)
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{
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GET_CCR(res);
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GET_CCR (res);
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}
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else if(code->src.type==OP_EXR && h8300smode)
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else if (code->src.type == OP_EXR && h8300smode)
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{
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GET_EXR(res);
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GET_EXR (res);
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}
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else
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goto illegal;
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@ -1270,11 +1270,11 @@ sim_resume (sd, step, siggnal)
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goto next;
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case O (O_ANDC, SB):
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if(code->dst.type==OP_CCR)
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if (code->dst.type == OP_CCR)
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{
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GET_CCR (rd);
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}
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else if(code->dst.type==OP_EXR && h8300smode)
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else if (code->dst.type == OP_EXR && h8300smode)
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{
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GET_EXR (rd);
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}
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@ -1285,11 +1285,11 @@ sim_resume (sd, step, siggnal)
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goto setc;
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case O (O_ORC, SB):
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if(code->dst.type==OP_CCR)
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if (code->dst.type == OP_CCR)
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{
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GET_CCR (rd);
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}
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else if(code->dst.type==OP_EXR && h8300smode)
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else if (code->dst.type == OP_EXR && h8300smode)
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{
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GET_EXR (rd);
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}
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@ -1300,11 +1300,11 @@ sim_resume (sd, step, siggnal)
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goto setc;
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case O (O_XORC, SB):
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if(code->dst.type==OP_CCR)
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if (code->dst.type == OP_CCR)
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{
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GET_CCR (rd);
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}
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else if(code->dst.type==OP_EXR && h8300smode)
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else if (code->dst.type == OP_EXR && h8300smode)
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{
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GET_EXR (rd);
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}
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@ -1410,7 +1410,7 @@ sim_resume (sd, step, siggnal)
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c = rd & (hm >> 1); v = (rd & (hm >> 1)) != ((rd & (hm >> 2)) << 2); rd <<= 2);
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OSHIFTS (O_SHAR,
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t = rd & hm; c = rd & 1; v = 0; rd >>= 1; rd |= t,
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t = rd & hm; c = rd & 2; v = 0; rd >>= 2; rd |= t | t >> 1 );
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t = rd & hm; c = rd & 2; v = 0; rd >>= 2; rd |= t | t >> 1);
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OSHIFTS (O_ROTL,
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c = rd & hm; v = 0; rd <<= 1; rd |= C,
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c = rd & hm; v = 0; rd <<= 1; rd |= C; c = rd & hm; rd <<= 1; rd |= C);
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@ -1534,9 +1534,9 @@ sim_resume (sd, step, siggnal)
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break;
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case O (O_TAS, SB):
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if( !h8300smode || code->src.type != X (OP_REG, SL) )
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if (!h8300smode || code->src.type != X (OP_REG, SL))
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goto illegal;
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switch(code->src.reg)
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switch (code->src.reg)
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{
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case R0_REGNUM:
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case R1_REGNUM:
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@ -1681,12 +1681,12 @@ sim_resume (sd, step, siggnal)
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abort ();
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setc:
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if(code->dst.type==OP_CCR)
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if (code->dst.type == OP_CCR)
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{
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cpu.ccr = res;
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GETSR ();
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}
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else if(code->dst.type==OP_EXR && h8300smode)
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else if (code->dst.type == OP_EXR && h8300smode)
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{
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cpu.exr = res;
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GETEXR ();
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@ -1873,7 +1873,7 @@ sim_resume (sd, step, siggnal)
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cpu.pc = pc;
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BUILDSR ();
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BUILDEXR();
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BUILDEXR ();
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cpu.mask = oldmask;
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signal (SIGINT, prev);
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}
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@ -1994,7 +1994,7 @@ sim_fetch_register (sd, rn, buf, length)
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init_pointers ();
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if(!h8300smode && rn >=EXR_REGNUM)
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if (!h8300smode && rn >=EXR_REGNUM)
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rn++;
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switch (rn)
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{
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