Prevent undefined FMOV instructions being accepted by the AArch64 assembler.
Detect illegal FMOV instructions that changes the size from 32 bits to 64
bits and vice versa. Add tests for these and other undefined FMOV
instructions.
PR 20319
gas * testsuite/gas/aarch64/illegal-3.s: Test if unallocated FMOV encodings
are detected as undefined.
* testsuite/gas/aarch64/illegal-3.d: Likewise.
* testsuite/gas/aarch64/illegal.s: Test if FMOV instructions that are
changing the size from 32 bits to 64 bits and vice versa trigger an
error.
* testsuite/gas/aarch64/illegal.l: Likewise.
opcodes * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
(aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
This commit is contained in:
Egeyar Bagcioglu
Nick Clifton
parent
fd161d860f
commit
cb36699271
7 changed files with 123 additions and 3 deletions
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@ -1,3 +1,14 @@
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2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
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PR 20319
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* testsuite/gas/aarch64/illegal-3.s: Test if unallocated FMOV encodings
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are detected as undefined.
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* testsuite/gas/aarch64/illegal-3.d: Likewise.
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* testsuite/gas/aarch64/illegal.s: Test if FMOV instructions that are
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changing the size from 32 bits to 64 bits and vice versa trigger an
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error.
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* testsuite/gas/aarch64/illegal.l: Likewise.
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2018-06-08 Tamar Christina <tamar.christina@arm.com>
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PR binutils/21446
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@ -12,3 +12,38 @@ Disassembly of section \.text:
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4: 4de2d4fc .inst 0x4de2d4fc ; undefined
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8: 4dc2f4ec .inst 0x4dc2f4ec ; undefined
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c: 4de2f4fc .inst 0x4de2f4fc ; undefined
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10: 1ea04000 .inst 0x1ea04000 ; undefined
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14: 1ea01000 .inst 0x1ea01000 ; undefined
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18: 2f00f400 .inst 0x2f00f400 ; undefined
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1c: 1ea60000 .inst 0x1ea60000 ; undefined
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20: 1ea70000 .inst 0x1ea70000 ; undefined
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24: 9ea60000 .inst 0x9ea60000 ; undefined
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28: 9ea70000 .inst 0x9ea70000 ; undefined
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2c: 9e260000 .inst 0x9e260000 ; undefined
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30: 9e270000 .inst 0x9e270000 ; undefined
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34: 1e660000 .inst 0x1e660000 ; undefined
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38: 1e670000 .inst 0x1e670000 ; undefined
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3c: 1e2e0000 .inst 0x1e2e0000 ; undefined
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40: 1e2f0000 .inst 0x1e2f0000 ; undefined
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44: 1e6e0000 .inst 0x1e6e0000 ; undefined
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48: 1e6f0000 .inst 0x1e6f0000 ; undefined
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4c: 1eae0000 .inst 0x1eae0000 ; undefined
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50: 1eaf0000 .inst 0x1eaf0000 ; undefined
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54: 1eee0000 .inst 0x1eee0000 ; undefined
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58: 1eef0000 .inst 0x1eef0000 ; undefined
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5c: 1e2e0000 .inst 0x1e2e0000 ; undefined
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60: 1e2f0000 .inst 0x1e2f0000 ; undefined
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64: 1e6e0000 .inst 0x1e6e0000 ; undefined
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68: 1e6f0000 .inst 0x1e6f0000 ; undefined
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6c: 1eee0000 .inst 0x1eee0000 ; undefined
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70: 1eef0000 .inst 0x1eef0000 ; undefined
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74: 9e2e0000 .inst 0x9e2e0000 ; undefined
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78: 9e2f0000 .inst 0x9e2f0000 ; undefined
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7c: 9e6e0000 .inst 0x9e6e0000 ; undefined
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80: 9e6f0000 .inst 0x9e6f0000 ; undefined
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84: 9eee0000 .inst 0x9eee0000 ; undefined
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88: 9eef0000 .inst 0x9eef0000 ; undefined
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8c: 1ea60000 .inst 0x1ea60000 ; undefined
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90: 1ea70000 .inst 0x1ea70000 ; undefined
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94: 9ea60000 .inst 0x9ea60000 ; undefined
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98: 9ea70000 .inst 0x9ea70000 ; undefined
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@ -7,3 +7,50 @@
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.inst 0x4dc2f4ec
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.inst 0x4de2f4fc
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// PR 20319:
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# Check FMOV for Unallocated Encodings
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# FMOV (register): type == 0x10
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.inst 0x1ea04000
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# FMOV (scalar, immediate): type == 0x10
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.inst 0x1ea01000
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# FMOV (vector, immediate): Q == 0 && op == 1
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.inst 0x2f00f400
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# FMOV (general):
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# type == 10 && rmode != 01
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.inst 0x1ea60000
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.inst 0x1ea70000
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.inst 0x9ea60000
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.inst 0x9ea70000
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# rmode == 00 && fltsize != 16 && fltsize != intsize
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.inst 0x9e260000
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.inst 0x9e270000
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.inst 0x1e660000
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.inst 0x1e670000
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# rmode == 01 && intsize != 64
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.inst 0x1e2e0000
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.inst 0x1e2f0000
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.inst 0x1e6e0000
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.inst 0x1e6f0000
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.inst 0x1eae0000
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.inst 0x1eaf0000
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.inst 0x1eee0000
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.inst 0x1eef0000
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# rmode == 01 && fltsize != 128
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.inst 0x1e2e0000
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.inst 0x1e2f0000
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.inst 0x1e6e0000
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.inst 0x1e6f0000
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.inst 0x1eee0000
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.inst 0x1eef0000
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.inst 0x9e2e0000
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.inst 0x9e2f0000
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.inst 0x9e6e0000
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.inst 0x9e6f0000
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.inst 0x9eee0000
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.inst 0x9eef0000
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# type == 10 && rmode != 01
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.inst 0x1ea60000
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.inst 0x1ea70000
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.inst 0x9ea60000
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.inst 0x9ea70000
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@ -573,4 +573,6 @@
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[^:]*:577: Error: .*`fmov d0,#0x8000000000000000'
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[^:]*:582: Error: .*`fcmgt v0\.4s,v0\.4s,#-0\.0'
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[^:]*:585: Error: .*`fcmgt v0\.2d,v0\.2d,#-0\.0'
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[^:]*:587: Error: .*
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[^:]*:589: Error: .*`fmov s9,x0'
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[^:]*:590: Error: .*`fmov d7,w1'
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[^:]*:592: Error: .*
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@ -584,4 +584,9 @@ one_label:
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fcmgt v0.2d, v0.2d, #0 // OK
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fcmgt v0.2d, v0.2d, #-0.0
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# PR 20319: FMOV instructions changing the size from 32 bits
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# to 64 bits and vice versa are illegal.
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fmov s9, x0
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fmov d7, w1
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// End (for errors during literal pool generation)
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@ -1,3 +1,9 @@
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2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
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PR 20319
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* aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
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(aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
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2018-06-06 Alan Modra <amodra@gmail.com>
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* xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
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@ -295,6 +295,13 @@
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QLF2(S_S,X), \
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}
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/* e.g. FMOV <Dd>, <Xn>. */
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#define QL_INT2FP_FMOV \
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{ \
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QLF2(S_S,W), \
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QLF2(S_D,X), \
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}
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/* e.g. SCVTF <Hd>, <Wn>. */
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#define QL_INT2FP_H \
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{ \
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@ -311,6 +318,13 @@
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QLF2(X,S_S), \
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}
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/* e.g. FMOV <Xd>, <Dn>. */
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#define QL_FP2INT_FMOV \
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{ \
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QLF2(W,S_S), \
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QLF2(X,S_D), \
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}
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/* e.g. FCVTNS <Hd>, <Wn>. */
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#define QL_FP2INT_H \
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{ \
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@ -3038,9 +3052,9 @@ struct aarch64_opcode aarch64_opcode_table[] =
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FF16_INSN ("fcvtas",0x1ee40000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF),
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__FP_INSN ("fcvtau",0x1e250000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF),
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FF16_INSN ("fcvtau",0x1ee50000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF),
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__FP_INSN ("fmov", 0x1e260000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF),
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__FP_INSN ("fmov", 0x1e260000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT_FMOV, F_FPTYPE | F_SF),
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FF16_INSN ("fmov", 0x1ee60000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF),
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__FP_INSN ("fmov", 0x1e270000, 0x7f3ffc00, float2int, 0, OP2 (Fd, Rn), QL_INT2FP, F_FPTYPE | F_SF),
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__FP_INSN ("fmov", 0x1e270000, 0x7f3ffc00, float2int, 0, OP2 (Fd, Rn), QL_INT2FP_FMOV, F_FPTYPE | F_SF),
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FF16_INSN ("fmov", 0x1ee70000, 0x7f3ffc00, float2int, OP2 (Fd, Rn), QL_INT2FP_H, F_FPTYPE | F_SF),
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__FP_INSN ("fcvtps",0x1e280000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF),
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FF16_INSN ("fcvtps",0x1ee80000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF),
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